5+ Years of Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concept Show more Show less
Job Summary We are looking for an experienced Senior RTL Design Engineer with a strong background in SoC architecture, logic design, and RTL development. This role is ideal for candidates who are passionate about software-driven digital hardware design and have in-depth knowledge of modern SoC systems, protocols, and low-power design Responsibilities : Design and implement scalable RTL architectures for complex SoC components using Verilog/SystemVerilog. Develop and maintain logic blocks aligned with architectural and functional specifications. Collaborate with design verification and architecture teams to define module interfaces and performance metrics. Implement low-power design techniques using software methodologies such as clock gating, power domain partitioning, etc. Model asynchronous interfaces and multi-clock domain logic for integration into larger SoC platforms. Analyze design performance and optimize RTL for area, power, and logical efficiency. Write clean, reusable, and synthesis-friendly RTL code following best practices and coding standards. Simulate and debug logic design using industry tools and waveform analysis. Integrate IPs and subsystems in a modular and maintainable way using software configuration and scripting Skills & Experience : 5+ years of experience in RTL design, logic development, and micro-architecture. Strong command over Verilog/SystemVerilog and digital design methodologies. Proven experience in designing software-driven SoC architectures with modular, configurable RTL. In-depth knowledge of AMBA protocols - AXI, AHB, APB. Experience in multi-clock domain logic and asynchronous interface design. Proficiency in low-power RTL techniques including power-aware coding and UPF/CPF flows (logic-level). Familiarity with RTL design tools such as Simulation (ModelSim/VCS), Linting, CDC/RDC tools. Scripting skills in TCL, Python, or Shell for automating RTL testbenches, configuration, or IP Qualifications : Bachelors or Masters degree in, Computer Engineering, or related field. Exposure to software-based SoC modeling or transaction-level modeling (TLM). Experience with design abstraction, reusable IP architecture, and configurable RTL components. Knowledge of interfaces such as USB, PCIe, SD/eMMC at RTL level. (ref:hirist.tech)
Company Description Tecquire Solutions Pvt Ltd is a one-stop solution provider for semiconductor design services. Founded by a team with over 25+ years of experience in the semiconductor industry, Tecquire has a strong track record in SOC design and first-time silicon success. . Role Description This is a full-time on-site role for a Sr Engineer / Lead Engineer in Physical Design. 4-8 For Senior Design Engineer 8 to 12 Years of Hands on Experience for Lead Engineer Block level Physical Design Implementation from RTL to GDSII or Netlist to GDSII, Block level Physical Signoff, Block level Timing Signoff and ECO generation. Block level Power signoff. Good skill on Automation (Perl/Tcl/Awk/Python) Able to provide technical guidance to Junior Engineer and lead 4-6 engineers. Must have led small project team. Good in communication skill as he/she would be single point of contact for client. .
Role Overview We are seeking an experienced Lead DFT Engineer to join our team in Bengaluru. This is a full-time, on-site role where you will be responsible for designing and implementing advanced DFT architectures, performing coverage gap analysis, executing silicon debug and pattern reduction, and developing comprehensive test cases. You will lead projects, collaborate with cross-functional teams, and ensure delivery of high-quality solutions that meet or exceed client expectations. Key Responsibilities Lead DFT design and implementation across multiple SoCs. Drive ATPG, MBIST, BSCAN, and silicon bring-up activities. Develop and manage DFT constraints from bring-up to final delivery. Conduct thorough silicon debug, pattern reduction, and coverage analysis. Mentor and guide junior team members to achieve optimal results. Interface effectively with clients, presenting solutions and discussing technical options. Qualifications & Experience Proven experience leading a DFT team for at least two SoC projects . Strong hands-on expertise in ATPG, MBIST, BSCAN , and silicon bring-up. Solid understanding of DFT constraints and their integration in the design process. Excellent leadership, mentoring, and problem-solving skills. Strong communication skills to interact with internal teams and clients. Compensation Competitive and based on experience, including track record in successfully building and managing DFT teams. Show more Show less
About The Job We are looking for a talented and detail-oriented DFT Engineer with a minimum of 3 years of hands-on experience in Design for Testability. The ideal candidate will possess a strong technical background in DFT methodologies, including ATPG, MBIST, Scan Insertion, and Silicon Debugging, along with excellent scripting and debugging skills. Key Responsibilities DFT Implementation : Develop and implement DFT architectures and methodologies for complex SoCs and ASICs. Perform Automatic Test Pattern Generation (ATPG), Memory Built-In Self-Test (MBIST), and Scan Insertion processes. Generate, simulate, and verify ATPG, MBIST, and LBIST (Logic Built-In Self-Test) patterns to ensure robust test coverage and design integrity. Pattern Porting & Verification Understand the requirements for pattern porting from block level to top level and execute them efficiently. Collaborate with design and verification teams to ensure seamless integration of DFT features across various design hierarchies. DFT Architecture & ICL Network Develop a thorough understanding of DFT architecture, including scan chains, boundary scan (JTAG), and BIST techniques. Apply knowledge of ICL (Interconnect Logic) network design and its impact on testability and design performance. Timing & STA Constraints Work with timing analysis teams to define and validate Static Timing Analysis (STA) constraints related to DFT modes. Ensure timing closure and resolve any STA violations in test modes. Silicon Debugging & Validation Participate in post-silicon bring-up and debug activities, analyzing test results, identifying failures, and providing solutions. Leverage silicon debug tools and methodologies to improve test coverage and reduce test time. Required Skills And Experience 3+ years of hands-on experience in DFT with a strong emphasis on debugging and scripting. Proficient in ATPG, MBIST, Scan Insertion, and pattern simulation/verification techniques. Strong understanding of DFT architecture, ICL network, and STA constraints. Experience with Silicon Debug and bring-up processes (preferred). Proficient in scripting languages such as TCL, Perl, Python, or similar, to automate design and verification tasks. Familiarity with industry-standard EDA tools for DFT (e.g., Synopsys, Mentor Graphics, Cadence). Excellent problem-solving skills and the ability to work effectively in a collaborative team environment. (ref:hirist.tech)
Company Description Tecquire Solutions Private Limited is a comprehensive provider of semiconductor design services. The company was founded by a team with over 25+ years of experience in the semiconductor industry. Tecquire Solutions provides tailored services in the areas of DFT architecture, DFT implementation, silicon debug, pattern reduction, and Netlist to GDSII implementation. The company has a strong track record of successful SOC design and first-time silicon success across multiple tape-outs. Job Summary: We are seeking an experienced and strategic Director of Physical Design to lead and grow our physical design team responsible for the implementation of complex SoC and ASIC designs. The ideal candidate will have a proven track record of delivering high-performance, low-power silicon products, leading multi-site teams, and driving execution from RTL to GDSII. This leadership role requires deep technical expertise, strong program management skills, and the ability to align physical design execution with overall company goals. Key Responsibilities: Lead and manage the entire Physical Design team across multiple projects and geographies. Drive end-to-end physical implementation: RTL handoff, floorplanning, place & route, clock tree synthesis, static timing analysis, physical verification (DRC/LVS), and tape-out. Own project planning, resource allocation, schedule management, and risk mitigation across multiple physical design programs. Collaborate with RTL, DFT, Verification, Packaging, and Process Technology teams to ensure successful chip integration and delivery. Define and enforce design methodologies, flows, and best practices to improve quality, efficiency, and tape-out success. Interface with EDA vendors to evaluate tools and improve tool flow and performance. Ensure design goals are met for power, performance, area (PPA), and yield. Hire, mentor, and develop a high-performing team of engineers and managers. Contribute to technology planning and roadmap discussions in alignment with product strategy. Requirements: Education & Experience: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field (PhD preferred). 15+ years of experience in VLSI/ASIC/SoC physical design, with at least 5-6 years in a leadership or director-level role. Proven experience in leading full-chip physical design to successful tape-out at advanced process nodes (e.g., 7nm, 5nm, 3nm). Technical Skills: Deep understanding of physical design flow and EDA tools (Cadence, Synopsys, Mentor, etc.). Strong expertise in STA, low-power design, DFT integration, IR drop analysis, EM, and signal integrity. Experience with hierarchical physical design methodologies and large SoC integration. Knowledge of advanced packaging (e.g., chiplets, 2.5D/3D IC) is a plus. Leadership & Communication: Proven ability to lead large teams and manage complex multi-disciplinary projects. Strong interpersonal and communication skills; able to influence across teams and executive stakeholders. Track record of mentoring and developing high-performing teams. Preferred Qualifications: Experience in working with foundries like TSMC, Samsung, Intel Foundry. Familiarity with ISO 26262, functional safety, or security standards (for automotive or safety-critical applications). Exposure to ML/AI acceleration, networking, or mobile SoC designs is an advantage. Why Join Us: Opportunity to shape next-generation semiconductor products. Collaborative and innovation-driven culture. Competitive compensation and stock options. Work on cutting-edge technology with world-class engineering teams.
Company Description Tecquire Solutions Private Limited is a comprehensive provider of semiconductor design services. The company was founded by a team with over 25+ years of experience in the semiconductor industry. Tecquire Solutions provides tailored services in the areas of DFT architecture, DFT implementation, silicon debug, pattern reduction, and Netlist to GDSII implementation. The company has a strong track record of successful SOC design and first-time silicon success across multiple tape-outs. Job Summary: We are seeking an experienced and strategic Director of Physical Design to lead and grow our physical design team responsible for the implementation of complex SoC and ASIC designs. The ideal candidate will have a proven track record of delivering high-performance, low-power silicon products, leading multi-site teams, and driving execution from RTL to GDSII. This leadership role requires deep technical expertise, strong program management skills, and the ability to align physical design execution with overall company goals. Key Responsibilities: Lead and manage the entire Physical Design team across multiple projects and geographies. Drive end-to-end physical implementation: RTL handoff, floorplanning, place & route, clock tree synthesis, static timing analysis, physical verification (DRC/LVS), and tape-out. Own project planning, resource allocation, schedule management, and risk mitigation across multiple physical design programs. Collaborate with RTL, DFT, Verification, Packaging, and Process Technology teams to ensure successful chip integration and delivery. Define and enforce design methodologies, flows, and best practices to improve quality, efficiency, and tape-out success. Interface with EDA vendors to evaluate tools and improve tool flow and performance. Ensure design goals are met for power, performance, area (PPA), and yield. Hire, mentor, and develop a high-performing team of engineers and managers. Contribute to technology planning and roadmap discussions in alignment with product strategy. Requirements: Education & Experience: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field (PhD preferred). 15+ years of experience in VLSI/ASIC/SoC physical design, with at least 5-6 years in a leadership or director-level role. Proven experience in leading full-chip physical design to successful tape-out at advanced process nodes (e.g., 7nm, 5nm, 3nm). Technical Skills: Deep understanding of physical design flow and EDA tools (Cadence, Synopsys, Mentor, etc.). Strong expertise in STA, low-power design, DFT integration, IR drop analysis, EM, and signal integrity. Experience with hierarchical physical design methodologies and large SoC integration. Knowledge of advanced packaging (e.g., chiplets, 2.5D/3D IC) is a plus. Leadership & Communication: Proven ability to lead large teams and manage complex multi-disciplinary projects. Strong interpersonal and communication skills; able to influence across teams and executive stakeholders. Track record of mentoring and developing high-performing teams. Preferred Qualifications: Experience in working with foundries like TSMC, Samsung, Intel Foundry. Familiarity with ISO 26262, functional safety, or security standards (for automotive or safety-critical applications). Exposure to ML/AI acceleration, networking, or mobile SoC designs is an advantage. Why Join Us: Opportunity to shape next-generation semiconductor products. Collaborative and innovation-driven culture. Competitive compensation and stock options. Work on cutting-edge technology with world-class engineering teams.