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DFT Engineer

DFT Engineer

5 - 10 years

|

8 - 9 Lacs

hubli mangaluru mysuru bengaluru belgaum

Posted:1 day ago| Platform:

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Skills Required

soc verification ace sbt soc simulation design verification scalability axi fpga design debugging assertions system verilog firmware architecture asic asic verification rtl uvm asic design verilog fabrics ddr silicon dft ownership pcie waveform

Work Mode

Work from Office

Job Type

Full Time

Job Description

Own end-to-end DFT architecture, planning, and implementation for complex SoCs.
Develop and integrate scan, MBIST/LBIST, boundary scan (IEEE 1149.1/1500), and compression.
Generate ATPG patterns, analyze coverage, and drive defect reduction/yield improvements.
Expertise with Tessent / DFTAdvisor / SpyGlass-DFT , ATPG, and fault simulation.
Hands-on with RTL/gate-level insertion, constraints, and timing/area/power trade-offs.
Silicon bring-up, ATE pattern debug, diagnostics, and failure analysis.
Strong RTL (Verilog/SystemVerilog), STA basics, scripting (TCL/Python/Perl).
Collaborate with design/PD/ATE teams; excellent communication and documentation.

Mandatory Skiils:

Scan chain design / ATPG
Verilog / SystemVerilog (HDL)
MBIST / LBIST / Boundary Scan (JTAG)
Tessent / Mentor / Cadence DFT tools + TCL/Python scripting

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