Associate II - VLSI SC Char

You will be responsible for executing internal projects or small tasks within customer projects related to VLSI Frontend, Backend, or Analog design with minimal supervision from the Lead. Your role will involve working as an Individual contributor on tasks such as RTL Design, Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will be expected to analyze and complete assigned tasks within the defined domain successfully and on time with minimal support from senior engineers, ensuring quality delivery as approved by the senior engineer or project lead. Quality of deliverables is a key focus, requiring clean delivery of modules that are easy to integrate at the top level, meeting functional specifications and design guidelines without deviation. Timely delivery is crucial, meeting project timelines set by the team lead or program manager and assisting in the delivery of intermediate tasks by other team members to ensure overall progress. Teamwork is essential, involving active participation and support for team members when needed, along with the ability to perform additional tasks if necessary. Innovation and creativity are encouraged, with a proactive approach towards automating tasks to save design cycle time and active participation in technical discussions. Your skills should include proficiency in languages and programming such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Spice. Familiarity with EDA tools like Cadence, Synopsys, and Mentor, along with technical knowledge in areas such as IP Spec Architecture, Micro Architecture, Bus Protocols, Physical Design, Circuit Design, and Analog Layout is required. Knowledge of technology including CMOS, FinFet, FDSOI, and experience in previous projects related to RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, or Analog Layout is beneficial. You should possess strong communication skills, good analytical reasoning, problem-solving abilities, attention to detail, and the capability to learn new skills as required. Delivering tasks with quality and on time, per quality guidelines and GANTT, is essential. Your role as an Assistant Engineer at UST will involve executing Standard Cell characterization tasks, debugging failures, and utilizing tools such as PrimeLib, Liberate, Redhawk, and CCSP/PGV characterization. Experience in Python coding and API coding is a plus. A Bachelor's or Master's degree in Engineering is required with 2-8 years of relevant experience.,