175 Analog Layout Jobs

JD: Analog Layout, TSMC, Intel, Samsung Foundries Nodes - Finfet like 2nm, 3nm, 5nm, 7 nm Location - HYD interested candidate, Kindly share with me your updated profile to anand.arumugam@modernchipsolutions.com Or call me 9900927620 for Discussion

Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in Analog Layout design Expertise in planar technology node / higher node (180nm - 28nm) is mandatory Expertise in EMIR analysis, ESD, antenna and related layout solutions Knowledge of advanced technology nodes (7nm & below) Good understanding of advanced semiconductor technology process and device physics Full-custom circuit layout/verification and RC extraction experience Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional

As a Custom Layout Engineer at our company, you will be responsible for acting as the focal point with customers and leading a team of 3-4 custom layout engineers. Your primary focus will be on analog layout, physical verification, and maintaining PDKs. Your expertise in critical layouts such as PLL, DLL, LNA, VGA, ADC, and LDO will be crucial for this role. Additionally, you should be able to quickly adapt to new technologies, tools, and flows. Key Responsibilities: - Work as a focal point with customers - Lead a team of 3-4 custom layout engineers - Handle analog layout, physical verification, and maintaining PDKs - Demonstrate expertise in critical layouts including PLL, DLL, LNA, VGA, ADC, and LDO - Adapt quickly to new technologies, tools, and flows - Mentor layout engineers - Collaborate with different teams and prioritize work based on project needs Qualifications Required: - BE/B.Tech /ME/M.Tech with 4-6 years of experience - Strong expertise in Custom Layout Standard Cells, I/O, or special analog designs - Experience in Pcell development, maintaining, and modifying PDKs - Proficiency in tools such as Virtuoso, Virtuoso-XL, Calibre, Hercules, and Assura - Expertise in SKILL Programming Language - Strong understanding of Analog Design - Good written and oral communication skills - Ability to clearly document plans In this role, you will play a critical part in the design and development process, ensuring the successful implementation of analog layouts and physical verification. Your ability to lead a team, collaborate with customers, and adapt to new technologies will be key to your success in this position.,

Dear Candidate We have immediate job openings for Analog layout and design openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Analog layout exp Skills Required: Analog Layout design and IO design Good to Have: Exposure to Analog layout, EDA tools Thanks Gayathri

Dear Candidate We have immediate job openings for Analog layout and design openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Analog layout exp Skills Required: Analog Layout design and IO design Good to Have: Exposure to Analog layout, EDA tools Thanks Gayathri

Physical Deisgn Lead Location: Bangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl Well versed with timing constraints, STA and timing closure. Mandatory Skills: VLSI Physical Place and Route. Experience: 5-8 Years.

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Analog Layout Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary: As a Software Development Engineer, you will engage in a dynamic work environment where you will analyze, design, code, and test various components of application code across multiple clients. Your typical day will involve collaborating with team members to perform maintenance and enhancements, ensuring that the application meets the highest standards of quality and functionality. You will also be responsible for developing new features and addressing any issues that arise, contributing to the overall success of the projects you are involved in. Roles & Responsibilities: - Expected to be an SME. - Collaborate and manage the team to perform. - Responsible for team decisions. - Engage with multiple teams and contribute on key decisions. - Provide solutions to problems for their immediate team and across multiple teams. - Mentor junior team members to enhance their skills and knowledge. - Continuously evaluate and improve development processes to increase efficiency. Professional & Technical Skills: -Strong GPIO layout skills -Experience in advanced nodes in IC layout, including 28nm, 22nm, 14nm, 8nm, 5nm and below. -Experience in IC layouts with frequencies up to 40GHz. -Experience in critical IC layouts, including GPIO Library, ESD Cell and so on. -Working knowledge in Linux -Proficiency in CAD tools including Cadence Virtuoso, Calibre LVS, DRC, and SkillCad. -Excellency in communications skills in the form of verbal, email, and in documentations. -Be able to work independently. -Good to have experience to lead a small team and tapeout an analog IC. - Must To Have Skills: Proficiency in Analog Layout. - Strong understanding of circuit design principles and methodologies. - Experience with layout tools such as Cadence or Mentor Graphics. - Familiarity with design for manufacturability and reliability. - Ability to troubleshoot and resolve layout-related issues effectively. Role & responsibilities Preferred candidate profile

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualification BE/BTech from any reputed University Masters Preferred Experience Between 3 to 10 years Hands on with any of the spice simulators (Hspice/ Spectre)

About The Role : To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification. Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below). Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects. Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks. Primary Skills : Analog Layout Design(Block/IP level) LVS/DRC Debugging FinFET Technology Node Experience(5nm, 7nm, 10nm, 14nm and below) EDA Tools Cadence Virtuoso Editor Calibre RVE Layout Optimization Area estimation Floorplanning Routing Secondary Skills : These support the primary responsibilities and enhance performance: Understanding of Physical Design Concepts: Matching Electromigration (EM) Electrostatic Discharge (ESD) Latch-Up Shielding Parasitics Short Channel Effects Critical Thinking & Problem Solving Interpersonal and Communication Skills Team Collaboration Educational Qualification: Bachelor"s or Master"s Degree.

We are looking For Analog Layout Engineer Skills: who worked on Lower nodes 3nm, 5 nm, 7 nm, 10 nm Exp: 4-9yrs Loc: HYD

Hands-on technical, finfet expertise (nodes 12nm or below) and manage a team of 5+ members. Proven track record of managing a team of >5 members. Experience within the service industry. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective actions if needed until result is successful Performs layout in such a way that final result meets the foundry layout rules. Provides extracted netlist for back annotation to DE as specified in the Design document, section layout. Translates sub block schematics to sub block layouts, taking care of the same hierarchical build-up and respecting the guidelines of the Block review document, section layout. Adds extra useful information to the Block review document, section layout.

Designation: Member Technical Staf No.of positions : Multiple Experience : 3- 15 Years Education : MTech VLSI / BE. ECE Industry Type : Education / E-Learning / Semiconductor Functional Area : Training category: Technical Filter: Full- time Job Description Extensive hands on and teaching experience on Digital,Verilog ,Analog, Mixed Signal Circuits. Extensive experience in Back-end design Responsible for development and support of Projects. Desired Candidate Profile Responsible for Training Delivery and Support Desired Candidate Profile Sound Knowledge on Digital / Verilog / Analog / SV / UVM / DFT 3 to 15 years industry/teaching experience Good communication skill

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory

General Summary: Posting Title: Analog/Mixed Signal PLL Analog Designers Bangalore (BDC), India Job Function Qualcomm Mixed-Signal IP team is actively seeking for analog circuit designers (3-10yrs) to join our growing team in Bangalore, India (BDC). You will be directly involved in delivering analog and mixed-signal integrated circuits for high-speed PLL/DLL/LDO IP for SoC and the integration into Qualcomm's Mobile, Auto, IoT & Compute SoC products in leading-nodes - finfets & beyond. Design goals include low-power & low voltage analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Architecture, design, and development of analog / mixed signal hard macros for the PLL IP Design team Experience in designing multiple analog building blocks Bias, References, Op-amp, LDOs, VCO/DCO etc & High-Speed custom digital like dividers, distribution etc. Perform custom circuit design in the latest FinFET CMOS processes technologies and deliver hard macros and support customer integration and testing. Able to setup, run & analyses circuit simulations(spice) & create behaviour models. Work closely with Layout, Digital designer, PD & HSIO Bench/ATE Team Participate in internal customer requirements discussions to create design specifications. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Skills & Experience A minimum of 2-years of transistor level analog mixed-signal design experience, preferably in PLL design, high-speed wireline SerDes, DDR or other high-speed applications Experience in using SPICE simulators, adexl & virtuoso. Familiar with custom analog layout parasitic LLEs optimization, post layout extraction, Verification & design review closure Understanding of signal integrity in high-speed wireline design is preferred. Scripting to automate circuit design and verification work. Able to work with teams across the globeand possess good communication and presentationskills. Preferred Mixed signal designexperience Keywords Analog circuit Design, PLL, VCO, DCO, Clock distribution

General Summary: 2026 Campus Hire_ Engineer_ HW Qualcomm is looking for an energetic, creative and self-driven engineer to work in Modem , Multimedia , Connectivity , Computer Vision and Image Processing , software implementation and hardware acceleration. The work will directly influence the various subsystems within the SoC. The ideal candidate would have very strong problem solving and analytical skills combined with creativity and a passion for innovation. They would be able to carry forward that new idea, concept, and/or application that will propel systems to new levels of effectiveness and efficiency. At Qualcomm you will perform detailed technical analysis, translate ideas into models, SW and/or HW and work closely with other teams to help deliver real products. At Qualcomm, the sky's the limit. College Graduates play important roles everywhere in the company. Many of our 27,000+ employees join us right out of school because we're working on the cutting edge in wireless. Complex wireless devices are only as powerful as the software that runs them. As a software engineer, you will develop, implement and maintain multimedia, gaming and application software for the world's leading-edge mobile devices. We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries from automotive to health care, from smart cities to robotics we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design\ Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Educational Background:Masters, Bachelors: Electrical Engineering , VLSI , Embedded and VLSI , ECE Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skills.

About The Role This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; About The Role - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are looking for an Layout Design Engineer someone who is excited to join a growing group of diverse individuals responsible for handling challenging analog circuit designs. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI the next era of computing. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life s work, to amplify human creativity and intelligence. What youll be doing: Execute IC layout of cutting edge, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 2nm, 3nm, 5nm, 7nm and lower nodes following industry best practices. Deliver layouts for Circuit Solutions Group specializing in digital cum analog IPs. IP layout will comprise of significant digital components and some analog components. Adopting and putting in place best layout practices/methodology for composing Analog and digital layouts Follow company procedures and practices for IC layout activities. Perform full custom layout of analog/mixed-signal blocks such as op-amps, bandgaps, PLLs, ADCs, DACs, LDOs, Voltage Regulators etc. Ensure design quality by adhering to matching, symmetry, and parasitic sensitivity requirements. Execute layout verification (DRC, LVS, ERC, Antenna checks, EMIR) and resolve violations. Optimize layouts for area, performance, and manufacturability. What we need to see: 4+ years of experience in high performance analog layout in advanced CMOS process. BE/M-Tech in Electrical & Electronics or equivalent experience. Thorough knowledge of industry standard EDA tools for Cadence. Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps etc. is required. Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines) Experience with floor planning, block level routing and macro level assembly. Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines. Demonstrated experience with analog layout for silicon chips in mass production. Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred. Experience working in distributed design team is a plus. Requires self-starter with the ability to define and adhere to a schedule. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Summary: The candidate will be responsible for developing and implementing test methodologies, maintaining automatic test suites, creating test specs, and developing automatic test suites for supporting custom routing solutions. He / She will be working closely with R&D, Product Engineering, and Software Release teams in order to enhance the quality of the products. Experience and Technical Skills required: We are looking for a candidate having 3-7 years of experience with sound knowledge in Custom Place & Route Solutions. Good Understanding of DRC/LVS & Analog layout Concepts. Must be familiar with advance process nodes in chip design. Understanding of Cadence SKILL, Perl, Python programming languages. Candidate must be passionate, self-motivated, fast learner and capable of significantly contributing individually as well as a team player. Qualifications Education : M. E. /MTech (Electronics or similar) or B. E/BTech. (Electronics or similar) We re doing work that matters. Help us solve what others can t.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Timing models for AMS macros in multiple formats as required. Review path, topology etc. reports Methodology and flow improvements using automation Characterization of Analog Mixed Signal macros Analog Digital interface timing model extraction Correlated timing model data to Hspice simulations for accuracy checks Follow QA checks for consistency and correctness. Skills Must have 3-4yrs hands-on exp in lib characterization for AMS macros. Must have experience with NanoTime Solid understanding of timing fundamentals. Experience in Hspice/Spectre simulators is desirable. Automation using shell/perl/tcl or python is a must. Nice to have Organized and methodical with effective communication skills.

Responsibilities: Must have solid understanding of analog & mixed signal design fundamentals Design of basic analog IPs like LDOs, DC-DC converters, ADC/DACs, PLLs,Oscillators, Temperature sensors, Bandgap references and voltage monitors. Circuit design implementation of SERDES blocks like Transmitter, CTLE, SAL,DLL, Phase Interpolator, DFE and FFE Working Experience in Die to Die interconnect high speed IO designs, HBM, DDRand UCIe protocols. Hands on experience on lower FINFET technology nodes Basic analog layout knowledge especially with FINFET technology Expertise in following tools and standards: Cadence and Synopsys mixed signal design tool flow Requirements: The Candidate should have at least 4 years of experience in Analog circuit designand be able to work independently Cadence and Synopsys mixed signal design tool flow Preferred Qualifications: Bachelors or masters degree in electrical engineering or Electronics &Communications.

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical design and execution issues related to physical verificationand sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/cores. Good hands on Calibre, Virtuoso etc. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Expertise in physical verification of Block/Partition/ Full-chip-level DRC, Experience and understanding of all phases of the IC design process from RTL-GDS2. LVS, ERC, DFM Tape out process on cutting edge nodes, Preferably worked on 3nm/5nm/7nm/12nm/14nm/16nm nodes at the major foundries Experience in debugging LVS issues at chip-level/block level with complex analog-mixed signal IPs Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.) Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc. Experience with ERC rules and ESD rules has an added advantage Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to Engineer and mentor junior engineers, fostering their professional growth and development. Preferred qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Proven track record with multiple successful final production tape-outs Proven ability to independently deliver results and be able to work hands-on as and guide/help peers to deliver their tasks Be able to work under limited supervision and take complete accountability. Excellent written and verbal communication skills Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration and Physical verification challenges.

This position is for an Analog Layout Engineer role who should have the below required knowledge and skills - - Should have good understanding of semiconductor / Analog Layout & Physical verification basics. - Good hands-on Block level scratch Layout work, floor plan, placement, routing - Hands on in 28nm/22nm/ 14nm/ 7nm/ 5nm is desirable - Should understand Analog layout concepts on BGR / LDO/ OPAMP/ ADC/ DAC etc - Hands on Layout exposure to matching techniques like Inter-digitization and common centroid on current mirrors and differential pairs. - Should have good understanding of full custom layout implementation and Layout dependent effects - Good matching and other analog layout related concepts and hands-on implementation from scratch. - Work hands-on critical tasks as and when needed Requirements Requirements Experience: - 5 - 10 years of Analog Layout experience is required - 5nm/7nm/ 10nm/14nm/16nm with Finfet experience is a MUST. - Hands-on expertise in layout techniques such as matching / Shielding / Handling Clocks Etc - Experience in block-level floor-plan, hierarchical layout methodologies / including Power Mesh - Should have performed Physical Verification checks (DRC/LVS/DFM checks) - Experience in analyzing and resolving failure mechanisms EM/IR/ANT/DENSITY/Latch-up - Experience in Tools like Cadence-Virtuoso -XL / Calibre/ PVS/ Custom Compiler/ ICV - Strong scripting skills with Perl/Python/SKILL is a plus Benefits Benefits Whats in it for you - Work on leading edge technologies - An opportunity for career development and growth - Competitive compensation & Exceptional benefits

Job Description Actively contribute to provide Custom Datapath solutions for next generation Memory in advanced CMOS technology nodes. Designing Datapath (custom and/or RTL) Blocks, Full chip Timing Finesim Design closure to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering (VLSI Design) Hands-on design knowledge on both Digital custom, Analog & mixed signal design environment. 4+ years o

Job Description Will be technically driving team Custom Circuit IO and Datapath solutions for next generation Memory in advanced CMOS technology nodes. Will work on architecture of High speed IO and DataPath solutions to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Hand-on design knowledge on both analog & mixed signal design environment. 8+ years of Experience on IO circuit blo

You are a Senior Principal Analog Layout Engineer at OnSemi, responsible for developing high-quality layout for complex AMS IP blocks including voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, and drivers. You will lead a team of 4-6 engineers, review their work, and drive continuous quality improvements. Your responsibilities include estimating schedules, managing manpower resources, and planning layout activities to ensure timely completion. In this role, you will contribute to area estimation, optimization, floor planning, power routing, shielding, and physical verification such as DRC, ERC, LVS, and ESD. Additionally, you will support the team in taping out high-performance microcontroller chips and collaborate with cross-functional teams including Chip team, Tech, and CAD. Developing scripts and methods for layout design automation will also be a part of your duties. Onsemi is dedicated to driving disruptive innovations in automotive and industrial markets to create a better future. The company focuses on megatrends like vehicle electrification, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a unique product portfolio, Onsemi develops intelligent power and sensing technologies to address complex global challenges and lead the way in building a safer, cleaner, and smarter world. Minimum qualifications for this role include a BS in Electrical Engineering or related field with 12 years of experience, or an MS with 10 years of experience. Preferred candidates should have experience in analog/mixed-signal layout design of deep submicron CMOS and BCD technologies. Proficiency in interpreting CALIBRE DRC, ERC, LVS reports, programming skills in SKILL, Perl, and/or Python, and experience with CADENCE or MENTOR GRAPHICS layout tools are desirable. Strong understanding of semiconductor manufacturing process, DFM techniques, and familiarity with Cadence Design Environment (CDE) and Unix OS are also required. Effective communication skills and a collaborative team spirit are essential for success in this role.,