340 Analog Layout Jobs

As an Analog Layout Engineer at our company, you will be responsible for designing high-speed analog and mixed-signal layouts on advanced FinFET nodes, particularly TSMC 2nm, 3nm, 5nm, and 7nm. Your expertise in custom layout for high-speed IPs such as PLLs, SERDES, clock buffers, and data paths will be critical in ensuring successful tapeouts. **Key Responsibilities:** - Hands-on experience in custom layout for high-speed IPs including PLLs, SERDES, clock buffers, and data paths - Proficiency in Cadence Virtuoso, Calibre DRC/LVS, and PEX flows - Deliver clean layouts with successful DRC/LVS/EM/IR sign-offs across multiple tapeouts - Expertise in layout techniques for matching, shielding, pa...

At Capgemini Engineering, as a part of the global team of engineers, scientists, and architects, you will have the opportunity to work on innovative projects that help the world's most innovative companies unleash their potential. Your role will involve working independently on block levels analog layout design, with a focus on critical analog layout design of various blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, and more. You will be expected to have good LVS/DRC debugging skills and experience with verifications for lower technology nodes like 14nm FinFet and below. Additionally, you...

Role Overview: You should have 8-10 years of work expertise in the field. You will be responsible for designing high performance analog layouts in advance CMOS process nodes. Your expertise in layouts of high performance and high-speed analog blocks such as ADC, DAC, PLL is required. High speed SERDES expertise is mandatory for this role. You should be well-versed in analog layout techniques like common centroid, interdigitation, shielding, dummy devices, EM aware routing on critical block, and must be familiar with VXL compliant methodology. Additionally, you will be responsible for physical verification checks including DRC, LVS, DFM, ERC, EM, IR, etc. Knowledge of layout automation using ...

Summary: As an Analog Circuit Design Engineer, you will engage in the design and development of analog circuits tailored for diverse applications. Your typical day will involve simulating and prototyping circuits, ensuring they meet performance and power efficiency standards. You will address challenges such as noise and signal integrity while collaborating with team members to integrate these circuits into larger systems. Extensive testing will be a key part of your role, allowing you to validate the circuits and ensure their reliability in real-world applications. Roles & Responsibilities: - Expected to be an SME. - Collaborate and manage the team to perform. - Responsible for team decisio...

Role & responsibilities :- • Lead design of analog IPs PLLs, Bandgaps, LDOs, ADCs, DACs, amplifiers, oscillators, etc. • Own end-to-end design: specs circuit design simulation layout post-layout silicon. • Perform PVT, Monte Carlo, noise, jitter, and reliability analysis. • Guide layout engineers and collaborate across design, AMS, and system teams. • Support silicon bring-up, debug, and characterization. • Mentor junior engineers and drive design best practices. Preferred candidate profile :- • 2+ years of experience in analog/mixed-signal circuit design. • Strong CMOS fundamentals and hands-on experience with Cadence/Spectre/HSPICE. • Proven tape-out and silicon validation experience. • Ex...

Skill set required : Should have a very good understanding of semiconductor and analog basics. Good hands-on experience in toplevel integration and block level analog layouts like ADC/DAC/PLL/high speed Serdes, Power Management blocks Hands-on experience in 7nm, 5nm. N3E or lower node experience is a plus. Good Experience with floor planning, matching, EM/IR and DFM issues and other analog layout related concepts and hands on implementation from scratch. Experience of LVS, Density, lower node DRCs, Parasitic reduction and other lower node challenges. Good experience in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reaso...

BE/B.Tech /ME/M.Tech 4 years to 8 years He/She should be able to act as focal point with customers, work and lead a team of 3-4 custom layout engineers on analog layout, physical verification, maintaining PDKs, ealuating them. The candidates should have a strong expertise in some critical layouts such as PLL, DLL, LNA, VGA, ADC, LDO. He/She should be able to adapt to new technologies/tools/flows pretty quickly. Expertise in Custom Layout Standard Cells, I/O or special analog designs such as RF transceivers, LNA, VGA, PLL, DLL, LDO, Bandgap, VCO, ADC,DAC. Strong Layout Design Concepts. Experience in Pcell development, maintaining and modifying PDKs. Experience in Layout Design tools such as V...

Job Description Actively contribute to provide Custom Datapath solutions for next generation Memory in advanced CMOS technology nodes. Designing Datapath (custom and/or RTL) Blocks, Full chip Timing Finesim Design closure to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering (VLSI Design) Hands-on design knowledge on both Digital custom, Analog & mixed signal design environment. 4+ years ...

The ideal candidate should possess deep expertise in memory layout techniques, design rule compliance, and physical verification methodologies used in sub-3nm technologies. Required Candidate profile Strong understanding of SRAM, ROM, and memory bit-cell architectures. Deep knowledge of DRC, LVS, and parasitic extraction flows. Hands-on experience with advanced FinFET process nodes (3nm or less). Perks and benefits custom memory layouts on 3nm or lower nodes.

Work Profile : - Work on development of custom Analog circuit boards for applications related to RF, interfaces etc. - Implement new features and bug fixes - Verify analog/mixed-signal integrated circuits - Develop test cases to verify new features and bug fixes - Review and update the user manuals for software tools. - Supporting digital modelling of analog circuits for mixed-signal verification - Creating design specifications and circuit schematics - Work both independently and in a team environment, with the opportunity to provide technical leadership to other members of the engineering team - Create and/or modify specification documents detailing system design and enhancements to meet m...

Hi All, Looking for skilled Analog Layout Engineer for our leading client at Bangalore location. Total exp- 4 years to 10 years Work Location-Bangalore Notice Period- Immediate to 30 days Skill- Analog Layout Design (Block/IP level) LVS/DRC Debugging FinFET Technology Node Experience (5nm, 7nm, 10nm, 14nm and below) EDA Tools Cadence Virtuoso Editor Calibre RVE Layout Optimization Area estimation Floorplanning Routing JD To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good un...

Modernize Chip Solutions are looking for Analog Layout Engineer Exp: 4-8yrs Loc: HYD If Interested, please share your profile to my mail id sushma.vunnam@modernchipsolutions.com

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Analog layout designer providing onsite support for advanced nodes, working with global layout and design team. - Candidate should work independently on block level and IP level Analog layout design, coordinating with the circuit designer & the layout team - Candidate should have minimum 8+ years of hands-on experience in Analog or RF layout. - Should have worked on floorplan and layout for analog modules like SerDes, ADC/DAC, PLL, etc. - Should have w...

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Analog layout designer providing onsite support for advanced nodes, working with global layout and design team. - Candidate should work independently on block level and IP level Analog layout design, coordinating with the circuit designer & the layout team - Candidate should have minimum 8+ years of hands-on experience in Analog or RF layout. - Should have worked on floorplan and layout for analog modules like SerDes, ADC/DAC, PLL, etc. - Should have w...

As an Analog Layout professional with 5+ years of experience, your responsibilities will include: - Designing and developing critical analog, mixed-signal, custom digital blocks, and providing full chip level integration support. - Implementing verification flows such as LVS/DRC/DFM/Antenna check/EMIR. - Ensuring on-time delivery of block-level layouts meeting quality standards. - Demonstrating expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS. - Working independently to meet project requirements. Qualifications required for this role: - BE or MTech in Electronics/VLSI Engineering. - Good communication skills for effective collaboration with cross-functional teams. - Hands-on e...

As an Analog Layout Design Lead with 7+ years of relevant work experience, you will be responsible for Analog Layout in advanced process technologies, catering to global Semiconductor product MNC clients. **Key Responsibilities:** - Perform Analog Layout in advanced process technologies for global Semiconductor product MNC clients - Work on advanced Analog VLSI projects - Collaborate with world-class VLSI MNC clients in Analog Layout projects - Utilize hands-on knowledge in analog and mixed-signal layout techniques - Experience with Cadence Layout tools (Virtuoso) and Mentor Graphics verification tools (Calibre) - Execute Custom Analog Layout for I/O, Amplifiers/OPAMP circuits, ADCs/DACs, LD...

As an Analog Layout Designer at UST, your role involves working independently on block level and chip level Analog layout design while coordinating with the circuit designer & the project lead. You should have a minimum of 3+ years of hands-on experience in Analog layout and custom layout experience in DAC, ADC, Band gap, Regulators, LDOs, etc. Knowledge of finfet or technology exposure to 28nm or below is considered an added advantage. It is essential to have a full understanding of IC fabrication and reliability issues along with full familiarity with Cadence-Virtuoso, PVS, ASSURA, and Calibre tools. Excellent written and verbal communication skills are required for effective collaboration...

As a Manager / Senior Role Physical Design Engineer at Radiant Semiconductors in Hyderabad, you will be responsible for the following key responsibilities: - Execute IP/Block level PnR activities from Netlist to GDS-II - Demonstrate proficiency in all PnR activities including Floor-planning, Placement, CTS, Routing, Timing closure (STA), and signoff checks like FEV, VCLP, EMIR, and PV - Implement all Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file - Handle signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff - Utilize knowledge of high performance and low power implementation methods - Showcase expertise in tools like ICC2/Fusion Co...

Role Overview: As a VLSI and Hardware Architect at Wipro Limited, your role involves designing and architecting VLSI and Hardware based products to enable delivery teams to provide exceptional client engagement and satisfaction. You will be responsible for defining product requirements, implementing VLSI and Hardware Devices, and continuously upgrading design tools and frameworks. Your ability to analyze components and hardware elements, conduct cost-benefit analysis, and develop architectural designs for new and existing products will be crucial in meeting business requirements and ensuring product success. Key Responsibilities: - Define product requirements, design, and implement VLSI and ...

Role Overview: As a VLSI and Hardware Architect at Wipro Limited, your role involves designing and architecting VLSI and Hardware based products to enable delivery teams to provide exceptional client engagement and satisfaction. You will be responsible for defining product requirements, designing and implementing VLSI and Hardware Devices, conducting cost-benefit analysis, developing architectural designs, debugging critical problems, evangelizing architecture, and continuously improving and simplifying designs to optimize cost and performance. Key Responsibilities: - Define product requirements, design and implement VLSI and Hardware Devices - Constantly upgrade and update design tools and ...

As an Analog Layout Engineer at our company, you will be responsible for the following: - Full-custom circuit layout/verification and RC extraction - Experience in areas such as Mixed signal/analog/high-speed layout (e.g., PLL, IO, RF, PMIC, OSC, DC-DC convertor, Temperature sensor, SRAM, TCAM, ROM, MRAM, ESD) - Familiarity with Cadence Virtuoso environment and various industry physical verification tools (DRC, LVS, DFM, etc.) - Expertise in advanced technology nodes under 16nm/14nm/7nm, with 5nm/3nm being an added advantage - Proficiency in Totem EMIR & Self-heating effects, Star RC extraction, and Calibre PV checks (DRC, LVS, Antenna, ERC, PERC etc.) - Good understanding of layout fundamen...

Role Overview: You will be responsible for designing analog and mixed signal circuits, with a focus on bandgap references, voltage monitors, and SERDES blocks. Your expertise in lower FINFET technology nodes and die-to-die interconnect high-speed IO designs will be crucial. Additionally, you will be expected to work independently and have a solid understanding of analog design fundamentals. Key Responsibilities: - Designing circuit implementations of SERDES blocks such as Transmitter, CTLE, SAL, DLL, Phase Interpolator, DFE, and FFE - Working on Die to Die interconnect high-speed IO designs, HBM, DDR, and UCIe protocols - Utilizing basic analog layout knowledge, especially with FINFET techno...

As an IC Layout Manager at Micron Technology, you will have the opportunity to lead a team in designing IC layout for intensive applications such as artificial intelligence and high-performance computing solutions like High Bandwidth Memory. Your role will involve collaborating with peer teams across Micron's global footprint to ensure the successful completion of multiple projects. **Responsibilities:** - Provide leadership in building and growing a Custom layout team to support Micron's global DRAM layout requirement. - Develop Analog and custom layout to meet schedule and milestone. - Train the team in technical skills and cultural healthiness. - Communicate effectively with engineering t...

Hiring Layout/Mask Designers (4–6 yrs) for Micron, Hyderabad. Work on analog/mixed-signal/custom digital layout, advanced nodes (7nm/5nm/3nm), DRC/LVS/DFM/Antenna checks. Tools: Cadence Virtuoso, Calibre. Strong TSMC experience preferred. Required Candidate profile Custom layout design for Analog / Mixed-Signal Advanced node experience: TSMC 7nm / 5nm / 3nm Cadence VLE/VXL Calibre DRC / LVS verification Strong understanding of DRC, LVS, DFM, Antenna, EMIR

Skill set required : Should have a very good understanding of semiconductor and analog basics. Good hands-on experience in toplevel integration and block level analog layouts like ADC/DAC/ PLL/high speed Serdes, Power Management blocks Hands-on experience in 7nm, 5nm. N3E or lower node experience is a plus.. Good Experience with floor planning, matching, EM/IR and DFM issues and other analog layout related concepts and hands on implementation from scratch. Experience of LVS, Density, lower node DRCs, Parasitic reduction and other lower node challenges. Good experience in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical rea...