6 Cdcrdc Jobs

You will be responsible for executing internal projects or small tasks within customer projects related to VLSI Frontend, Backend, or Analog design with minimal supervision from the Lead. Your role will involve working as an Individual contributor on tasks such as RTL Design, Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will be expected to analyze and complete assigned tasks within the defined domain successfully and on time with minimal support from senior engineers, ensuring quality delivery as approved by the senior engineer or project lead. Quality of deliverables is a key focus, requiring clean delivery of modules that are easy to integrate at the top level, meeting functional specifications and design guidelines without deviation. Timely delivery is crucial, meeting project timelines set by the team lead or program manager and assisting in the delivery of intermediate tasks by other team members to ensure overall progress. Teamwork is essential, involving active participation and support for team members when needed, along with the ability to perform additional tasks if necessary. Innovation and creativity are encouraged, with a proactive approach towards automating tasks to save design cycle time and active participation in technical discussions. Your skills should include proficiency in languages and programming such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Spice. Familiarity with EDA tools like Cadence, Synopsys, and Mentor, along with technical knowledge in areas such as IP Spec Architecture, Micro Architecture, Bus Protocols, Physical Design, Circuit Design, and Analog Layout is required. Knowledge of technology including CMOS, FinFet, FDSOI, and experience in previous projects related to RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, or Analog Layout is beneficial. You should possess strong communication skills, good analytical reasoning, problem-solving abilities, attention to detail, and the capability to learn new skills as required. Delivering tasks with quality and on time, per quality guidelines and GANTT, is essential. Your role as an Assistant Engineer at UST will involve executing Standard Cell characterization tasks, debugging failures, and utilizing tools such as PrimeLib, Liberate, Redhawk, and CCSP/PGV characterization. Experience in Python coding and API coding is a plus. A Bachelor's or Master's degree in Engineering is required with 2-8 years of relevant experience.,

As an ASIC RTL Engineer at Google, you will be part of a team that is dedicated to developing custom silicon solutions for Google's direct-to-consumer products. Your role will involve pushing boundaries and contributing to the innovation that drives products loved by millions worldwide. Your expertise will play a crucial role in shaping the next generation of hardware experiences, focusing on delivering unparalleled performance, efficiency, and integration. In this role, you will lead a team of ASIC RTL engineers, overseeing sub-system and chip-level integration activities. Your responsibilities will include planning tasks, conducting code and design reviews, and developing complex features. You will collaborate closely with the architecture team to develop implementation strategies that meet quality, schedule, performance, power, and area requirements for sub-system/chip-level integration. Additionally, you will work with a cross-functional team comprising Verification, Design for Test, Physical Design, and Software teams. Your role will involve making design decisions and representing project status throughout the development process. Your contributions will be essential in ensuring the successful execution of projects and meeting the goals set for each stage of development. If you have a Bachelor's degree in Electrical Engineering or Computer Science, along with 8 years of experience in high-performance design and multi-power domains with clocking, and have worked on multiple SoCs with silicon success, this role could be an exciting opportunity for you. Experience with Verilog or System Verilog language is essential, and familiarity with ASIC design methodologies for front quality checks and chip design flow will be advantageous. Join us at Google, where we combine the best of Google AI, Software, and Hardware to create radically helpful experiences. Our mission is to make the world's information universally accessible and useful, and your contributions as an ASIC RTL Engineer will play a significant role in achieving this goal.,

As an RTL Engineering Lead at Google, you will play a vital role in driving innovation and developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will be instrumental in shaping the future of hardware experiences that cater to millions of users worldwide. By leveraging your expertise, you will enhance performance, efficiency, and integration in the next generation of Google products. With a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience, along with 6 years of hands-on experience in micro-architecture and coding, particularly in memory compression, interconnects, coherence, cache, Dynamic Random-Access Memory controller, and Physical Layer Device, you are well-equipped to excel in this role. Proficiency in Verilog or SystemVerilog language is a must to thrive in this dynamic environment. Ideally, you possess experience in high-performance design, multi-power domains with complex clocking, and have a proven track record of delivering successful SoCs. Your expertise in microarchitecture design and system design will be pivotal in developing highly optimized IPs with excellent Power, Performance, and Area (PPA) metrics. Familiarity with chip design flow and quality checks at the front end, including Lint, CDC/RDC, Synthesis, and Line Echo Cancellation, will further enhance your capabilities. In this role, you will lead a team of RTL engineers, overseeing IP development plan tasks, conducting code and design reviews, and driving the development of complex features within the IP. Collaboration with the architecture team is essential to strategize microarchitecture and coding implementations that align with quality, schedule, and PPA goals. Additionally, you will work closely with cross-functional teams, including Verification, Design for Test, Physical Design, and Software teams, to make informed design decisions and ensure project progress is effectively communicated throughout the development lifecycle. Join our diverse team of passionate individuals who are committed to pushing boundaries and creating innovative solutions that enhance the lives of people globally. Together, we aim to make technology faster, seamless, and more powerful, ultimately realizing Google's mission of organizing the world's information and making it universally accessible and useful.,

As an ASIC RTL Engineer at Google, you will be part of a team that is dedicated to developing custom silicon solutions to power Google's direct-to-consumer products. Your role will involve contributing to the innovation that drives the creation of products loved by millions worldwide, shaping the next generation of hardware experiences for unparalleled performance, efficiency, and integration. Your responsibilities will include: - Contributing as an ASIC RTL engineer to sub-system and chip-level integration activities. This will involve task planning, conducting code and design reviews, and contributing to sub-system/chip-level integration. - Working closely with the architecture team to develop implementation strategies that meet quality, schedule, and power performance area requirements for sub-system/chip-level integration. - Collaborating with the subsystem team to plan SOC milestones, quality checks, and guide subsystem teams with SOC level requirements such as IPXACT, CSR, Lint, CDC, SDC, UPF, etc. - Engaging with a cross-functional team of verification, design for test, physical design, emulation, and software teams to make design decisions and provide project status updates throughout the development process. To be successful in this role, you should have a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. You should also have at least 3 years of experience in RTL coding using Verilog or SystemVerilog language, with experience in high-performance design, multi-power domains with clocking. Preferred qualifications include experience with multiple SoCs with silicon success, knowledge of ASIC design methodologies for front quality checks, and domain expertise in areas such as Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, PinMux. Additionally, an understanding of cross-domain activities involving domain validation, design for testing, physical design, and software will be beneficial. Join us at Google and be part of a team that combines the best of Google AI, Software, and Hardware to create radically helpful experiences. Help us research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to make people's lives better through technology.,

You will be responsible for executing customer projects independently with minimum supervision, guiding team members technically in various fields of VLSI Frontend Backend or Analog design. As an individual contributor, you will take ownership of tasks/modules such as RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, Signoff, etc., leading the team to achieve results. Your responsibilities will include completing assigned tasks successfully and on-time within the defined domain(s), anticipating, diagnosing, and resolving problems, coordinating with cross-functional teams as necessary, delivering on-time quality work approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost accepted by UST Manager and Client. Additionally, you will be expected to write papers, file patents, and devise new design approaches. Your performance will be measured based on the quality of deliverables, timely delivery, reduction in cycle time and cost, number of papers published, number of patents filed, and number of trainings presented to the team. You will be expected to ensure zero bugs in the design/circuit design, deliver clean design/modules for ease of integration, meet functional specifications/design guidelines without deviation, and document tasks and work performed. Furthermore, you will be responsible for meeting project timelines, facilitating other team members" progress by delivering intermediate tasks on time, and seeking help and support in case of any delays. Your role will also involve active participation in team work, supporting team members as needed, anticipating when support may be required, and being able to explain project tasks and support delivery to junior team members. Your creativity and innovation will be showcased through tasks such as automating processes to save design cycle time, participating in technical discussions, training forums, white paper or patent filings, and contributing to technical discussions. Your skill set should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, Makefile, Spice, and familiarity with EDA Tools like Cadence, Synopsys, Mentor tool sets, and various simulators. You should have strong technical knowledge in IP Spec Architecture Design, Micro Architecture, Bus Protocols, Physical Design, Circuit Design, Analog Layout, Synthesis, DFT, Floorplan, Clocks, P&R, STA, Extraction, Physical Verification, Soft/Hard/Mixed Signal IP Design, and Processor Hardening. Additionally, you should possess communication skills, analytical reasoning, problem-solving skills, and the ability to interact effectively with team members and clients. Your knowledge and experience should reflect leadership and execution of projects in areas such as RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and understanding of design flow and methodologies. Independent ownership of circuit blocks, clear communication, diligent documentation, and being a good team player are essential attributes for this role. Overall, your role will involve circuit design and verification of Analog modules in TSMC FinFet technologies, developing circuit architecture, optimizing designs, verifying functionality, performance, and power, as well as guiding layout engineers. Strong problem-solving skills, results orientation, attention to detail, and effective communication will be key to your success in this position.,

As an experienced professional with 7-9 years of experience, you will be responsible for executing customer projects independently with minimal supervision in the field of VLSI Frontend Backend or Analog design. Your role will involve guiding team members technically and taking ownership of specific tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will lead the team to achieve results, complete assigned tasks successfully and on-time, and anticipate, diagnose, and resolve problems as necessary. Your responsibilities will also include ensuring on-time quality delivery approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost. Additionally, you will be expected to write papers, file patents, and devise new design approaches. To measure the outcomes of your work, quality will be verified using relevant metrics by UST Manager/Client Manager, timely delivery will be assessed based on relevant metrics, and the reduction in cycle time and cost using innovative approaches will be monitored. The number of papers published, patents filed, and trainings presented to the team will also be considered. Your outputs are expected to demonstrate high quality deliverables with zero bugs in the design/circuit design, clean delivery of the design/module, meeting functional specs/design guidelines without deviation, and thorough documentation of tasks and work performed. Timely delivery, teamwork, innovation, and creativity will be key aspects of your role, along with participation in technical discussions and training forums. Your skills should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. You should have experience with EDA tools like Cadence, Synopsys, and Mentor tool sets, as well as technical knowledge in IP spec architecture design, bus protocols, physical design, circuit design, analog layout, synthesis, DFT, floorplan, clocks, P&R, STA, extraction, physical verification, and more. Strong communication skills, analytical reasoning, problem-solving abilities, attention to detail, and the ability to interact with team members and clients effectively are essential. You should also be well-versed in using available EDA tools, delivering tasks on time per quality guidelines, understanding standard specs and functional documents, and continuously learning new skills as needed. If you have led and executed projects in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and possess a good understanding of design flow and methodologies, this role could be a great fit for you. Additionally, experience in analog circuit design and verifications, knowledge of TSMC FinFet technologies, and familiarity with Cadence Virtuoso circuit design suite would be beneficial. In this role, you will be responsible for circuit design and verification of analog modules like Voltage regulator, LDOs, developing circuit architecture, optimizing designs, guiding layout engineers, problem-solving, and effective communication skills. Desired skills include solid CMOS Analog design fundamentals, hands-on experience with Cadence Virtuoso, technical knowledge of power-performance trade-offs, understanding device parameter variation, and being a good team player in a multi-site work environment. Join us at UST, a global digital transformation solutions provider, where you will work alongside the world's best companies to make a real impact through transformation. With deep domain expertise, innovation, and agility, UST partners with clients to embed innovation and create boundless impact, touching billions of lives in the process.,