5 Makefile Jobs

As a senior leader in the central physical design team at Marvell, you will shape the long-term vision for physical design capabilities and infrastructure in alignment with the company-wide technology strategy. You will lead RTL-to-GDSII implementation for multiple SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS). Your role will involve providing strategic leadership and technical direction to physical design teams, ensuring successful and timely tapeouts of complex, high-performance SoCs. Mentoring and developing engineering talent will be a key aspect of your responsibilities, fostering a culture of innovation, collaboration, and continuous improvement within the team. You will oversee team structure, hiring, performance management, and career development to build and retain a high-performing physical design organization. Driving cross-functional collaboration with design teams to influence design decisions and ensure successful project execution will also be part of your role. You will navigate and resolve cross-functional conflicts effectively, fostering alignment and maintaining momentum across diverse teams. It will be your responsibility to drive the development and adoption of next-generation physical design methodologies, flows, and automation to improve productivity and design quality. Managing project schedules, resources, and risks to ensure alignment with business goals and customer requirements will also fall under your purview. Representing the physical design function in cross-org and executive-level discussions, contributing to long-term technology and product strategy will be expected. Collaborating with EDA vendors and internal CAD teams to evaluate and deploy new tools and technologies is also a crucial aspect of the role. We are looking for candidates with a Bachelors, Masters, or PhD degree in Electrical Engineering, Computer Engineering, or a related field, along with 18+ years of progressive experience in back-end physical design and verification, including significant leadership roles. A proven track record in leading and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts under aggressive schedules is essential. Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges is required. Additionally, familiarity with AI/ML-driven optimization in physical design tools is considered a plus. Strong communication and collaboration skills, along with the ability to influence cross-functional teams and executive stakeholders, are also important qualities for this role. Proficiency in automation and scripting using Makefile, Tcl, Python, or Perl to enhance design efficiency and flow robustness is expected. Marvell offers competitive compensation, great benefits, and a workstyle that promotes shared collaboration, transparency, and inclusivity. The company is dedicated to providing its employees with the tools and resources they need to succeed in meaningful work, grow, and develop within the organization. For more information on working at Marvell, visit our Careers page.,

Key Skills: C++, Modern C++, OOPS, Object-Oriented Design, Windows Application Development, Network Programming (TCP/IP), Client-Server Architecture, Multithreading, Debugging (WinDbg, GDB), Windows/Linux System Internals, System Programming, IPC, Makefile, CMake, Database Programming, Azure DevOps, CI/CD Pipelines, Software Architecture, Algorithms. Roles and Responsibilities: Implement and maintain Windows-based applications to support local development environments. Integrate project functions and resources across the full product lifecycle, including planning, development, testing, deployment, and support. Work independently as an individual contributor, managing tasks and delivering on time. Design, develop, and implement software solutions using C++ programming with a strong focus on quality and performance. Apply object-oriented design principles and algorithms to solve complex problems. Design, develop, and maintain CI/CD pipelines using Azure DevOps for continuous integration, deployment, and delivery. Contribute to system architecture discussions and decision-making processes. Troubleshoot and debug applications using tools such as WinDbg, GDB, and dump analysis utilities. Experience Requirements: 5 to 8 years of professional experience in software development using C/C++. Proven experience in object-oriented design and modern C++ programming. Hands-on experience with TCP/IP network programming and client-server architecture. Solid understanding of multithreading, synchronization techniques, and system-level programming. Experience working with both Windows and Linux system internals. Demonstrated expertise in debugging and analyzing crash dumps using industry-standard tools. Experience with inter-process communication (IPC), Makefiles, and CMake build systems. Experience in database programming and integrating data operations into applications. Hands-on experience with CI/CD pipelines, specifically using Azure DevOps. Education: B.Tech M.Tech (Dual), B.E., B.Tech.

You will be responsible for executing customer projects independently with minimum supervision, guiding team members technically in various fields of VLSI Frontend Backend or Analog design. As an individual contributor, you will take ownership of tasks/modules such as RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, Signoff, etc., leading the team to achieve results. Your responsibilities will include completing assigned tasks successfully and on-time within the defined domain(s), anticipating, diagnosing, and resolving problems, coordinating with cross-functional teams as necessary, delivering on-time quality work approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost accepted by UST Manager and Client. Additionally, you will be expected to write papers, file patents, and devise new design approaches. Your performance will be measured based on the quality of deliverables, timely delivery, reduction in cycle time and cost, number of papers published, number of patents filed, and number of trainings presented to the team. You will be expected to ensure zero bugs in the design/circuit design, deliver clean design/modules for ease of integration, meet functional specifications/design guidelines without deviation, and document tasks and work performed. Furthermore, you will be responsible for meeting project timelines, facilitating other team members" progress by delivering intermediate tasks on time, and seeking help and support in case of any delays. Your role will also involve active participation in team work, supporting team members as needed, anticipating when support may be required, and being able to explain project tasks and support delivery to junior team members. Your creativity and innovation will be showcased through tasks such as automating processes to save design cycle time, participating in technical discussions, training forums, white paper or patent filings, and contributing to technical discussions. Your skill set should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, Makefile, Spice, and familiarity with EDA Tools like Cadence, Synopsys, Mentor tool sets, and various simulators. You should have strong technical knowledge in IP Spec Architecture Design, Micro Architecture, Bus Protocols, Physical Design, Circuit Design, Analog Layout, Synthesis, DFT, Floorplan, Clocks, P&R, STA, Extraction, Physical Verification, Soft/Hard/Mixed Signal IP Design, and Processor Hardening. Additionally, you should possess communication skills, analytical reasoning, problem-solving skills, and the ability to interact effectively with team members and clients. Your knowledge and experience should reflect leadership and execution of projects in areas such as RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and understanding of design flow and methodologies. Independent ownership of circuit blocks, clear communication, diligent documentation, and being a good team player are essential attributes for this role. Overall, your role will involve circuit design and verification of Analog modules in TSMC FinFet technologies, developing circuit architecture, optimizing designs, verifying functionality, performance, and power, as well as guiding layout engineers. Strong problem-solving skills, results orientation, attention to detail, and effective communication will be key to your success in this position.,

As an experienced professional with 7-9 years of experience, you will be responsible for executing customer projects independently with minimal supervision in the field of VLSI Frontend Backend or Analog design. Your role will involve guiding team members technically and taking ownership of specific tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will lead the team to achieve results, complete assigned tasks successfully and on-time, and anticipate, diagnose, and resolve problems as necessary. Your responsibilities will also include ensuring on-time quality delivery approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost. Additionally, you will be expected to write papers, file patents, and devise new design approaches. To measure the outcomes of your work, quality will be verified using relevant metrics by UST Manager/Client Manager, timely delivery will be assessed based on relevant metrics, and the reduction in cycle time and cost using innovative approaches will be monitored. The number of papers published, patents filed, and trainings presented to the team will also be considered. Your outputs are expected to demonstrate high quality deliverables with zero bugs in the design/circuit design, clean delivery of the design/module, meeting functional specs/design guidelines without deviation, and thorough documentation of tasks and work performed. Timely delivery, teamwork, innovation, and creativity will be key aspects of your role, along with participation in technical discussions and training forums. Your skills should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. You should have experience with EDA tools like Cadence, Synopsys, and Mentor tool sets, as well as technical knowledge in IP spec architecture design, bus protocols, physical design, circuit design, analog layout, synthesis, DFT, floorplan, clocks, P&R, STA, extraction, physical verification, and more. Strong communication skills, analytical reasoning, problem-solving abilities, attention to detail, and the ability to interact with team members and clients effectively are essential. You should also be well-versed in using available EDA tools, delivering tasks on time per quality guidelines, understanding standard specs and functional documents, and continuously learning new skills as needed. If you have led and executed projects in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and possess a good understanding of design flow and methodologies, this role could be a great fit for you. Additionally, experience in analog circuit design and verifications, knowledge of TSMC FinFet technologies, and familiarity with Cadence Virtuoso circuit design suite would be beneficial. In this role, you will be responsible for circuit design and verification of analog modules like Voltage regulator, LDOs, developing circuit architecture, optimizing designs, guiding layout engineers, problem-solving, and effective communication skills. Desired skills include solid CMOS Analog design fundamentals, hands-on experience with Cadence Virtuoso, technical knowledge of power-performance trade-offs, understanding device parameter variation, and being a good team player in a multi-site work environment. Join us at UST, a global digital transformation solutions provider, where you will work alongside the world's best companies to make a real impact through transformation. With deep domain expertise, innovation, and agility, UST partners with clients to embed innovation and create boundless impact, touching billions of lives in the process.,

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Job Duties: We are seeking a motivated and quick-to-learn Software Engineer to join the Electronic Design Automation (EDA) field, specifically to advance the Questa formal verification product family. In this multifaceted role, you will be involved in the entire project lifecycle, from writing functional specifications to designing algorithms, coding, and creating test plans. Collaboration with a team of talented engineers and supporting top-tier industry customers will be essential. The ideal candidate will have extensive software development experience, particularly in developing and customizing components around graph-based formal models, with hands-on programming and expertise in crafting efficient netlist representation models for formal applications. Our primary responsibilities will include crafting and developing new features, customizing existing solutions, and improving software components for formal verification, ensuring quality, scalability, modifiability, and testability. You will collaborate with other engineering teams, take ownership of specific components, and drive them to excellence. Additionally, you will help drive the best software practices within the team and mentor other specialists as needed, all while contributing to the businesss overall needs. Job Qualifications: We require candidates to have a BE/B-Tech/M.Tech in CSE/ECE from a reputed engineering college. We are looking for candidates with 5-10 years of software experience, preferably in the Design and Verification domain. Expert in C++ , design patterns, and algorithms. Strong understanding of data structures and algorithm complexities . Proficient in advanced data structures and their applications. Expert in one of the following hardware description languages: Verilog , System Verilog , or VHDL . Knowledge of scripting languages like Perl , Python , Bash , or Tcl . Proficient with development tools such as Makefile , gdb , valgrind , perforce/git , gcov , editors , and IDEs . Strong problem-solving and analytical skills . Experienced in the development and delivery of multi-man-month projects from start to finish. Familiarity with Linux platforms . Exposure to formal-based verification methodologies (model checking, equivalence checking, automated reasoning) is a plus. Soft Skills: Self-motivated and committed to work. Strong team player with the ability to work independently. Hardworking, sincere, and open to constructive feedback. Able to work in challenging environments and collaborate effectively with multi-cultural technical teams. Good to Have: Exposure to Synthesis, Simulation, and other verification methodologies like Assertion, Coverage, etc. Strong presentation, listening, and communication skills for effective team interactions.