61 Finfet Jobs

JD: Analog Layout, TSMC, Intel, Samsung Foundries Nodes - Finfet like 2nm, 3nm, 5nm, 7 nm Location - HYD interested candidate, Kindly share with me your updated profile to anand.arumugam@modernchipsolutions.com Or call me 9900927620 for Discussion

About The Role : To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification. Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below). Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects. Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks. Primary Skills : Analog Layout Design(Block/IP level) LVS/DRC Debugging FinFET Technology Node Experience(5nm, 7nm, 10nm, 14nm and below) EDA Tools Cadence Virtuoso Editor Calibre RVE Layout Optimization Area estimation Floorplanning Routing Secondary Skills : These support the primary responsibilities and enhance performance: Understanding of Physical Design Concepts: Matching Electromigration (EM) Electrostatic Discharge (ESD) Latch-Up Shielding Parasitics Short Channel Effects Critical Thinking & Problem Solving Interpersonal and Communication Skills Team Collaboration Educational Qualification: Bachelor"s or Master"s Degree.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (8+ years) analog circuit designers to work on high speedSerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO,high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globeand possess good communication and presentationskills. Preferred Mixed signal designexperience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

Hands-on technical, finfet expertise (nodes 12nm or below) and manage a team of 5+ members. Proven track record of managing a team of >5 members. Experience within the service industry. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective actions if needed until result is successful Performs layout in such a way that final result meets the foundry layout rules. Provides extracted netlist for back annotation to DE as specified in the Design document, section layout. Translates sub block schematics to sub block layouts, taking care of the same hierarchical build-up and respecting the guidelines of the Block review document, section layout. Adds extra useful information to the Block review document, section layout.

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (16+ years) analog circuit designers to work on high speedSerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO,high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globeand possess good communication and presentationskills. Preferred Mixed signal designexperience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

General Summary: Posting Title: Analog/Mixed Signal PLL Analog Designers Bangalore (BDC), India Job Function Qualcomm Mixed-Signal IP team is actively seeking for analog circuit designers (3-10yrs) to join our growing team in Bangalore, India (BDC). You will be directly involved in delivering analog and mixed-signal integrated circuits for high-speed PLL/DLL/LDO IP for SoC and the integration into Qualcomm's Mobile, Auto, IoT & Compute SoC products in leading-nodes - finfets & beyond. Design goals include low-power & low voltage analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Architecture, design, and development of analog / mixed signal hard macros for the PLL IP Design team Experience in designing multiple analog building blocks Bias, References, Op-amp, LDOs, VCO/DCO etc & High-Speed custom digital like dividers, distribution etc. Perform custom circuit design in the latest FinFET CMOS processes technologies and deliver hard macros and support customer integration and testing. Able to setup, run & analyses circuit simulations(spice) & create behaviour models. Work closely with Layout, Digital designer, PD & HSIO Bench/ATE Team Participate in internal customer requirements discussions to create design specifications. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Skills & Experience A minimum of 2-years of transistor level analog mixed-signal design experience, preferably in PLL design, high-speed wireline SerDes, DDR or other high-speed applications Experience in using SPICE simulators, adexl & virtuoso. Familiar with custom analog layout parasitic LLEs optimization, post layout extraction, Verification & design review closure Understanding of signal integrity in high-speed wireline design is preferred. Scripting to automate circuit design and verification work. Able to work with teams across the globeand possess good communication and presentationskills. Preferred Mixed signal designexperience Keywords Analog circuit Design, PLL, VCO, DCO, Clock distribution

Key Responsibilities: Perform custom layout design of high-performance and low-power memory blocks (SRAM, ROM, Register Files, CAM, etc.). Work on floorplanning, transistor-level layout, device matching, and parasitic optimization. Ensure DRC/LVS clean layouts with adherence to foundry design rules. Collaborate with circuit design teams to achieve optimal PPA (Performance, Power, Area). Conduct parasitic extraction, EM/IR analysis, and reliability checks for memory layouts. Deliver high-quality layouts meeting project deadlines and silicon success. Required Skills: Strong expertise in memory layout (SRAM, ROM, CAM, Register Files). Hands-on experience with Cadence Virtuoso, Mentor Calibre, Synopsys tools. Deep knowledge of foundry design rules (DRC, LVS, ERC, ANT, etc.). Familiarity with advanced process nodes (7nm/5nm/3nm preferred). Strong understanding of layout-dependent effects (LDE), electromigration, IR drop. Good communication and ability to work in cross-functional teams. Good to Have: Experience with automation scripts (Perl/Python/Tcl) for layout productivity. Knowledge of EDA flow development for memory layout. Experience in custom analog layout is a plus. Education: B.E/B.Tech/M.Tech in Electronics, Electrical, VLSI, or related field.

8+ years of experience in Memory/Custom Layout design. Memory Leafcell layout library design from scratch Knowledge on different types of memory architectures. Knowledge in optimized layout design for better performance. Knowledge & hands on experience in Finfet technology, layout design and DRC limitations. Proficient in physical verification flow & debug Proficient in Cadence Virtuoso layout editor and Calibre Interested can contact me at shubhanshi@incise.in

You will be responsible for memory layout design, including important memory building blocks such as control, sense amplifiers, I/O Blocks, bit cell array, and decoders in the compiler context. Your hands-on experience should include working with 16nm/14nm/10nm/7nm/Finfet process technologies. You will be expected to have expertise in top-level memory integration, DRC, LVS, density verification, and cleaning physicals across the compiler space. It is essential to have a good understanding of IR/EM related issues in memory layouts and experience with Cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks. A strong knowledge of ultra-deep sub-micron layout design challenges and DFM guidelines is required. Experience or a strong interest in memory compilers is a plus. As a team player, you should be capable of working effectively with external customers and in cross-functional teams. Key Skills: Memory Layout, Finfet, Cadence, Layout Design About UST: UST is a global digital transformation solutions provider with a track record of partnering with leading companies for over 20 years. UST's approach is powered by technology, inspired by people, and led by purpose, supporting clients from design to operation. With a workforce of over 30,000 employees in 30 countries, UST aims to embed innovation and agility into its clients" organizations, making a boundless impact and touching billions of lives in the process.,

As an Analog Layout Design Engineer at Synopsys, you will play a pivotal role in developing cutting-edge layouts for next-generation DDR/HBM/UCIe IPs. Your primary responsibilities will include creating floorplans, routing, and conducting physical verifications to ensure high-quality deliverables that meet stringent quality standards within specified timelines. You will collaborate closely with design engineers to optimize layouts for performance, power efficiency, and area utilization. By implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation, you will contribute to the enhancement of the performance and reliability of semiconductor IPs. Ensuring compliance with DRC, LVS, ERC, and antenna rules will be a key part of your role to mitigate risks associated with layout design. Your expertise in deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies at 7nm and below will be crucial in driving the development of high-performance silicon chips. Your problem-solving skills, along with effective communication abilities, will enable you to work efficiently with cross-functional teams and convey complex technical concepts concisely. As a valuable member of the team at Synopsys, you will contribute to the mission of leading in chip design and software security by accelerating time-to-market for innovative technologies while fostering a collaborative and inclusive work environment. Your commitment to continuous learning and professional development will be instrumental in your success within our dynamic and innovative team. Join us at Synopsys to be a part of a forward-thinking organization that values collaboration, inclusivity, and continuous improvement. We offer a comprehensive range of rewards and benefits to cater to your needs, including health, wellness, and financial benefits. Your recruiter will provide you with more details about the salary range and benefits during the hiring process.,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and highly skilled engineer committed to advancing the field of high-speed analog design. You bring a wealth of experience in designing critical analog and mixed-signal blocks, particularly for cutting-edge PCIe 6 and PCIe 7 or SerDes PHY solutions. Your technical expertise encompasses transistor-level design, deep knowledge of CMOS (including finFET and SOI processes), and a proven ability to create robust high-speed building blockssuch as LDOs, Bandgap references, ADC/DACs, PLLs, and DLLsthat consistently meet rigorous performance, power, and area targets. You thrive in collaborative, multidisciplinary environments, where your clear communication and mentoring skills empower both peers and junior engineers to excel. Your proactive approach to problem-solving and your dedication to continuous improvement ensure that you stay at the forefront of technology trends. You are adept at analyzing and mitigating jitter, maintaining signal integrity, and ensuring compliance with demanding industry standards. Your experience with porting PHY designs across technology nodes demonstrates your adaptability and commitment to delivering high-quality, innovative solutions. You value documentation, knowledge sharing, and actively contribute to a culture of learning and technical excellence. Most importantly, you are excited to join a team that values diversity, encourages bold ideas, and is committed to shaping the future of high-speed connectivity. You see challenges as opportunities and bring a growth mindset to every project you undertake. What Youll Be Doing: Designing and developing advanced analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY architectures under the guidance of senior technical leaders. Ensuring that all designs strictly adhere to PCIe protocol standards, optimizing for performance, power, and area efficiency. Porting high-speed PHY designs to various technology nodes while maintaining signal integrity and maximizing performance. Collaborating with cross-functional teamsincluding digital, verification, and layout groupsto successfully integrate analog circuits into complex SerDes PHY systems. Implementing innovative verification strategies for high-speed analog/mixed-signal circuits using state-of-the-art simulation and modeling tools. Working closely with layout teams to minimize parasitics, device stress, and process variation impacts on overall circuit performance. Analyzing simulation and silicon measurement data to validate designs and ensure compliance with PCIe standards. Mentoring junior engineers and promoting best practices in analog/mixed-signal design and verification. Documenting design features, specifications, and test methodologies for future reference and team knowledge sharing. Partnering with characterization teams to validate electrical performance of circuits in silicon and resolve technical challenges. The Impact You Will Have: Drive the development of next-generation PCIe 6 and PCIe 7 PHY designs, advancing high-speed interface technologies that power tomorrows data-driven world. Ensure Synopsys analog/mixed-signal circuits exceed industry standards, reinforcing our reputation for technical excellence and innovation. Facilitate seamless integration of analog circuits into sophisticated SerDes PHY systems, enhancing overall performance and reliability. Mentor and develop junior engineers, fostering a collaborative and innovative team environment. Lead successful porting of PHY designs across multiple technology nodes, delivering versatile and scalable solutions for diverse customer needs. Strengthen verification and validation processes, resulting in robust, reliable, and high-performing analog/mixed-signal circuits. What Youll Need: PhD with 3+ years, or MTech/MS with 7+ years of experience in analog/mixed-signal circuit design focused on high-speed interfaces such as PCIe 6/7 or SerDes PHY designs. Proven expertise in transistor-level design of high-speed analog building blocks (e.g., LDOs, Bandgap references, ADC/DACs, PLLs, DLLs). Demonstrated silicon experience in developing PHY circuits compliant with PCIe standards. Strong background in high-speed SerDes AFE development, including CTLE and CDR design. Experience designing high-speed SerDes transmitters and deep knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis). Solid foundation in jitter budgeting analysis and expertise in minimizing jitter impact on signal integrity. Experience porting PHY designs across different technology nodes and deep knowledge of CMOS, finFET, and gate-all-around processes. Comprehensive understanding of the PCIe protocol, signal integrity, jitter performance, and high-speed clocking. Ability to collaborate with layout teams to minimize parasitics, process variations, and electromigration effects. Proven track record of effective teamwork and successful project outcomes across multidisciplinary teams. Who You Are: Innovative thinker with a passion for high-speed analog design and technology advancement. Collaborative team player who values diversity and inclusion. Effective communicator, able to translate complex technical concepts to a variety of audiences. Mentor and coach, eager to support the development of junior engineers. Detail-oriented problem solver with a commitment to quality and continuous improvement. Adaptable and resourceful, thriving in fast-paced, changing environments. The Team Youll Be A Part Of: You will join a world-class analog/mixed-signal design team at Synopsys, focused on developing high-speed interface IP for next-generation semiconductor products. The team is composed of passionate engineers from diverse backgrounds, collaborating closely to deliver innovative solutions that drive the future of connectivity. Our culture emphasizes technical excellence, knowledge sharing, and continuous learning, providing an environment where your skills and ideas are valued and your career can thrive. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

As a Senior R&D Engineer at Synopsys, you will play a crucial role in characterizing and modeling standard cells for various technologies and foundries. Your deep knowledge of MOSFET and FINFET technologies will be instrumental in conducting quality analysis of characterized liberty and Verilog models, ensuring accuracy in terms of timing, power, and functionality. By validating characterization and simulation tool versions, you will contribute to the enhancement of our standard cell models and tools" reliability. Your commitment to providing daily status updates and ensuring on-time, high-quality releases will be essential in driving innovation and continuous improvement within our engineering processes. Your collaborative nature and excellent communication skills will enable you to work effectively within and outside your team, making significant contributions to our projects. Your responsibilities will include applying your expertise in MOSFET and FINFET technologies, characterizing standard cells, conducting quality analysis of liberty and Verilog models, validating characterization and simulation tools, and providing daily status updates for project transparency. Your proactive approach, attention to detail, and commitment to meeting deadlines will be key in delivering high-quality results. You will be part of a highly skilled and motivated engineering team dedicated to ensuring the accuracy, reliability, and quality of our standard cell models and tools. Together, we will drive innovation and continuous improvement in our processes, making significant contributions to the advancement of technology applications. Join us at Synopsys to transform the future through continuous technological innovation. Explore the comprehensive range of health, wellness, and financial benefits we offer, tailored to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.,

You will be responsible for developing block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Your role will involve applying an understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. You will conduct analyses, tests, and verify designs using different tools and techniques to identify and troubleshoot issues. It is essential to stay abreast of new verification methods and work collaboratively with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. To qualify for this position, you must have a Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or a related field and a minimum of 2 years of experience designing custom layouts in a relevant domain. Alternatively, an Associate's degree in a related field with 4+ years of experience or a High School diploma with 6+ years of relevant experience will also be considered. Additionally, you should have at least 2 years of experience using layout design and verification tools such as cadence, LVS, and rmap. Qualcomm India Private Limited is a company of inventors seeking to revolutionize the CPU market. As an SRAM Mask Layout Designer, you will have the opportunity to work with a highly talented team to create designs that push the envelope on performance, energy efficiency, and scalability. The role involves developing block or macro level layouts and floorplans for high-performance custom memories based on project requirements and design schematics. Preferred qualifications for this role include a good understanding of device parasitics and reliability considerations during layout, knowledge of leading-edge processes, experience in layout design of library cells and memories in deep sub-micron technologies, and proficiency in industry-standard custom design tools and flows. Good communication skills are essential to work effectively with different teams and accurately describe issues. Key responsibilities include designing layout for custom memories and digital circuits, reading and interpreting design rule manuals, owning the entire layout process from floorplanning to physical verification, and providing insight into strategic decisions regarding memory layout. You should be able to work independently, execute memory layout with minimal supervision, and provide realistic schedules for layout completion. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com. It is important to abide by all applicable policies and procedures, including security and confidentiality requirements.,

Expertise in working on memory layout design for advanced nodes (TSMC 3nm, 5nm,), including FinFET architecture and challenges such as variability and manufacturability Expertise in working on address process-dependent effects like electro-migration (EM), IR drop Expertise in optimizing layouts for yield enhancement and manufacturing robustness Expertise in performing debugging of silicon failures and identify layout-related issues Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler Perform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Schematic) rules Work closely with circuit designers to ensure the layout meets electrical and performance specifications, such as timing, power, and area (PPA) Provide feedback on circuit designs to improve layout efficiency Utilize EDA tools for layout design, simulation, and verification, ensuring compliance with foundry-specific PDKs (Process Design Kits) Automate repetitive tasks and improve workflow efficiency using scripting (eg Python, SKILL) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations Preferred resources with valid regional work permit Location - Bangalore, Beijing, Moscow, Romania, Taiwan

You will be responsible for executing internal projects or small tasks within customer projects related to VLSI Frontend, Backend, or Analog design with minimal supervision from the Lead. Your role will involve working as an Individual contributor on tasks such as RTL Design, Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will be expected to analyze and complete assigned tasks within the defined domain successfully and on time with minimal support from senior engineers, ensuring quality delivery as approved by the senior engineer or project lead. Quality of deliverables is a key focus, requiring clean delivery of modules that are easy to integrate at the top level, meeting functional specifications and design guidelines without deviation. Timely delivery is crucial, meeting project timelines set by the team lead or program manager and assisting in the delivery of intermediate tasks by other team members to ensure overall progress. Teamwork is essential, involving active participation and support for team members when needed, along with the ability to perform additional tasks if necessary. Innovation and creativity are encouraged, with a proactive approach towards automating tasks to save design cycle time and active participation in technical discussions. Your skills should include proficiency in languages and programming such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Spice. Familiarity with EDA tools like Cadence, Synopsys, and Mentor, along with technical knowledge in areas such as IP Spec Architecture, Micro Architecture, Bus Protocols, Physical Design, Circuit Design, and Analog Layout is required. Knowledge of technology including CMOS, FinFet, FDSOI, and experience in previous projects related to RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, or Analog Layout is beneficial. You should possess strong communication skills, good analytical reasoning, problem-solving abilities, attention to detail, and the capability to learn new skills as required. Delivering tasks with quality and on time, per quality guidelines and GANTT, is essential. Your role as an Assistant Engineer at UST will involve executing Standard Cell characterization tasks, debugging failures, and utilizing tools such as PrimeLib, Liberate, Redhawk, and CCSP/PGV characterization. Experience in Python coding and API coding is a plus. A Bachelor's or Master's degree in Engineering is required with 2-8 years of relevant experience.,

Expertise in working on memory layout design for advanced nodes (TSMC 3nm, 5nm,), including FinFET architecture and challenges such as variability and manufacturability Expertise in working on address process-dependent effects like electro-migration (EM), IR drop Expertise in optimizing layouts for yield enhancement and manufacturing robustness Expertise in performing debugging of silicon failures and identify layout-related issues Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler Perform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Schematic) rules Work closely with circuit designers to ensure the layout meets electrical and performance specifications, such as timing, power, and area (PPA) Provide feedback on circuit designs to improve layout efficiency Utilize EDA tools for layout design, simulation, and verification, ensuring compliance with foundry-specific PDKs (Process Design Kits) Automate repetitive tasks and improve workflow efficiency using scripting (e.g., Python, SKILL) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations Preferred resources with valid regional work permit. Location- Bengaluru, Taiwan,Beijing, Moscow, Romania

You are a passionate and skilled Analog Layout Design Engineer with a keen eye for detail and a deep understanding of advanced semiconductor technologies You thrive in dynamic environments and possess a strong problem-solving aptitude With a profound expertise in developing high-quality layouts and physical verification techniques, you are ready to contribute to cutting-edge DDR/HBM/UCIe IP development You excel in collaboration, fostering accountability and ownership within teams, and have excellent written, verbal communication, and interpersonal skills Your commitment to diversity and inclusion aligns with Synopsysvalues, and you are eager to work in an environment that welcomes all perspectives, What Youll Be Doing: Hands-on development of layout for next-generation DDR/HBM/UCIe IPs, Solving complex problems and debugging issues effectively, Executing layout floor planning, routing, and physical verifications to meet stringent quality requirements, Ensuring compliance with DRC, LVS, ERC, and antenna rules, Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below), Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation, The Impact You Will Have: Enhancing the performance and reliability of SynopsysDDR/HBM/UCIe IPs, Accelerating the integration of advanced capabilities into SoCs, Reducing risk and improving time-to-market for differentiated products, Driving innovation in semiconductor technology and design, Contributing to the success of SynopsysSilicon IP business, Fostering a collaborative and inclusive work environment, What Youll Need: BTech/MTech degree in a relevant field, 4+ years of experience in analog layout design, Proven track record in developing high-quality layouts and meeting verification timelines, Strong understanding of deep submicron effects and floorplan techniques, Exposure to layout matching, ESD, latch-up, EMIR, DFM, and LEF generation, Who You Are: Detail-oriented with excellent problem-solving skills, Collaborative and able to foster accountability and ownership, Strong written, verbal communication, and interpersonal skills, Committed to diversity and inclusion, The Team Youll Be A Part Of: You will be part of a dynamic team focused on developing next-generation DDR/HBM/UCIe PHY IPs Our team values innovation, collaboration, and continuous improvement, driving the success of SynopsysSilicon IP business, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Experience: 3 to 10 Years Employment Type: Full-Time Notice Period: 30 Days Key Responsibilities: 1. Design and implementation of custom analog and mixed-signal layouts for circuits such as amplifiers, ADC/DACs, PLLs, and more. 2. Perform layout verification tasks, including DRC, LVS, and parasitic extraction using industry-standard tools. 3. Optimize layout designs for performance, area, and power while ensuring compliance with design rules and process constraints. 4. Collaborate closely with circuit design engineers to interpret specifications and requirements. 5. Participate in design reviews and contribute to the enhancement of layout methodologies. 6. Work on advanced nodes, ensuring high-quality layouts for high-performance, low-power designs. Required Skills and Qualifications: 1. Experience: 3 to 10 years in analog layout design, with expertise in full-custom IC design. 2. Proficiency in layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or equivalent. 3. Strong knowledge of semiconductor process technologies, including FinFETs and advanced nodes (e.g., 7nm, 5nm). 4. Hands-on experience with parasitic-aware design, matching, and signal integrity. 5. Familiarity with EDA tools for verification, such as Calibre or Assura. 6. Excellent analytical and problem-solving skills with attention to detail. 7. Strong communication and interpersonal skills to work effectively in a team environment. What We Offer: 1. Competitive compensation package and benefits. 2. Opportunity to work on innovative and challenging projects. 3. Dynamic and collaborative work environment. 4. Career growth and learning opportunities. Apply Now! If you meet the above qualifications and are ready to take on this exciting challenge, we would love to hear from you. Share your resumes at info@silcosys.com

About the Role: We are seeking a talented and experienced Analog Layout Engineer to join our team in Bangalore. The ideal candidate will have a strong background in analog layout design and will contribute to the development of cutting-edge semiconductor products. If you are passionate about VLSI design and eager to work in a collaborative, innovation-driven environment, this opportunity is for you! Location: Bangalore Experience: 3 to 10 Years Employment Type: Full-Time Notice Period: 90 Days Key Responsibilities: 1. Design and implementation of custom analog and mixed-signal layouts for circuits such as amplifiers, ADC/DACs, PLLs, and more. 2. Perform layout verification tasks, including DRC, LVS, and parasitic extraction using industry-standard tools. 3. Optimize layout designs for performance, area, and power while ensuring compliance with design rules and process constraints. 4. Collaborate closely with circuit design engineers to interpret specifications and requirements. 5. Participate in design reviews and contribute to the enhancement of layout methodologies. 6. Work on advanced nodes, ensuring high-quality layouts for high-performance, low-power designs. Required Skills and Qualifications: 1. Experience: 3 to 10 years in analog layout design, with expertise in full-custom IC design. 2. Proficiency in layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or equivalent. 3. Strong knowledge of semiconductor process technologies, including FinFETs and advanced nodes (e.g., 7nm, 5nm). 4. Hands-on experience with parasitic-aware design, matching, and signal integrity. 5. Familiarity with EDA tools for verification, such as Calibre or Assura. 6. Excellent analytical and problem-solving skills with attention to detail. 7. Strong communication and interpersonal skills to work effectively in a team environment. What We Offer: 1. Competitive compensation package and benefits. 2. Opportunity to work on innovative and challenging projects. 3. Dynamic and collaborative work environment. 4. Career growth and learning opportunities.

About The Role About The Role : 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is necessary. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc. Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience and collaborating with cross functional teams will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Multiple foundries experience is an added plus. Minimum Educational Qualification : Educational Bachelor"s, Electrical or Electronics Engineering or equivalent Role And Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, EM, quality check and documentation. Responsible for on-time delivery of block-level/top-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work Should have good experience in working with cross-functional team. Ensure standard processes and procedures are followed to resolve all client queries. Handle technical escalations through effective diagnosis and troubleshooting of client queries Manage and resolve technical roadblocks/ escalations to timely deliverable with high quality. Troubleshoot all client queries in a user-friendly, courteous, and professional manner. Offer alternative solutions to clients (where appropriate) with the objective of retaining customers" and clients" business. Build people capability to ensure operational excellence and maintain superior customer service levels of the existing account/client. Contribute to effective project-management. Effectively communicating with engineering teams in different Geographical locations to assure the success of the layout project. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders.

Qualcomm India Private Limited is seeking a Layout Engineer to develop block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. In this role, you will utilize your understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. You will conduct analyses, tests, and verify designs using various tools and techniques to identify and troubleshoot issues, while staying updated on new verification methods. Collaborating with multiple internal and external stakeholders, you will align on projects, provide updates, and resolve issues. The ideal candidate should have a Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or a related field with 2+ years of experience in designing custom layouts in relevant domains such as analog, mixed signal, RF, or digital design. Alternatively, an Associate's degree with 4+ years of experience or a High School diploma with 6+ years of experience in custom layout design is also acceptable. Additionally, a minimum of 2 years of experience using layout design and verification tools such as Cadence, LVS, rmap is required. Qualcomm is a company focused on innovation in the CPU market and is looking for a skilled SRAM Mask Layout Designer to join their high-performance CPU team. As an SRAM Mask Layout Designer, you will be responsible for developing block or macro level layouts and floorplans for high-performance custom memories based on project requirements and design schematics. The minimum qualifications for this role include 5+ years of experience with a high school diploma or equivalent, or 5+ years of experience with a BS in Electrical Engineering, or 3+ years of experience with an MS in Electrical Engineering. Direct experience with custom SRAM layout, familiarity with industry-standard custom design tools and flows, knowledge of leading-edge FinFET and/or nanosheet processes, and experience in layout design of library cells, datapaths, and memories in deep sub-micron technologies are preferred qualifications. Key responsibilities of the SRAM Mask Layout Designer include designing layouts for custom memories and digital circuits, interpreting design rule manuals for optimal layout creation, owning the entire layout process from floorplanning to physical verification, using industry-standard verification tools, providing layout fixes as needed, and collaborating with different teams to accurately describe issues and ensure completion. Applicants interested in this position at Qualcomm are encouraged to apply, as Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. For more information about this role, interested individuals can contact Qualcomm Careers directly.,

KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

We are looking for an experienced Analog Layout Engineer with 8+ years of hands-on experience in full custom layout of analog and mixed-signal blocks. The ideal candidate should have expertise in advanced CMOS technologies and be capable of delivering high-quality layout from specifications to tape-out. Key Responsibilities: Execute full custom layout for analog/mixed-signal blocks (OpAmps, Bandgaps, LDOs, ADCs, etc.) Floorplanning, device matching, parasitic optimization, and electromigration compliance Perform DRC/LVS/ERC checks and work closely with verification teams Collaborate with circuit designers to optimize performance and area Ensure quality layout delivery in accordance with tape-out schedules Support post-layout simulation and debug efforts Requirements: 8+ years of experience in analog/custom layout Strong understanding of matching, shielding, and analog layout best practices Hands-on experience with layout tools (Virtuoso, IC Compiler, Calibre, etc.) Knowledge of various technology nodes (180nm to FinFET) Good communication, teamwork, and problem-solving skills Apply Now! If you meet the above qualifications and are ready to take on this exciting challenge, we would love to hear from you. Share your resumes at info@silcosys.com