57 Redhawk Jobs

Job Description Role Summary We are seeking a strategic and technically hands-on leader to drive end-to-end Physical Design execution across multiple design centers in APAC. The ideal candidate will combine deep technical mastery in implementation flows with proven experience managing distributed teams toward predictable execution, industry-leading PPA (Performance, Power, Area), and first-silicon success. Key Responsibilities Leadership & Strategy Define and execute a long-term physical design strategy aligned with business and product goals. Build, mentor, and scale a world-class PD organization across APAC sites (Hyderabad, Singapore, etc.). Champion flow automation, design methodology in...

Physical Design Engineer Location: Bengaluru, India Experience: 6+ years About the Role We are seeking an experienced Lead Physical Design Engineer with strong expertise in Cadence Innovus and EMIR analysis to join our VLSI design team in Bengaluru. The ideal candidate will have hands-on experience driving the full RTL-to-GDSII flow and ensuring robust chip-level power, performance, and area (PPA) optimization. Key Responsibilities Execute full-chip and block-level physical design using Cadence Innovus, from floorplanning to GDSII. Perform timing closure, power optimization, and signal integrity analysis at advanced technology nodes. Conduct EM/IR (EMIR) analysis and sign-off to ensure robus...

As a Principal Physical Design Engineer at the company, your role will involve taking the lead as part of a Physical Design team with expertise in Low Power Design. You will be expected to excel in an aspect of the low power physical design skill set and have significant responsibility for delivering skilled tasks and/or the full chip from RTL to GDS. Additionally, you will act as the team lead, serving as the customer interface, reporting project aspects, and ensuring proper allocation of tools and resources to meet company commitments. **Responsibilities:** - Perform comprehensive power analysis at various design stages from RTL to GDS. - Contribute to developing, improving, and automating...

Best Nanotech is expanding its VLSI team in Bengaluru ! We are looking for a Senior Physical Design Engineer with 7+ years of experience to take ownership of complex high-speed blocks from Netlist to GDSII in advanced technology nodes (5nm/3nm). Position: Senior/Lead Physical Design Engineer Location: Bengaluru (On-site/Hybrid) Experience: 7+ Years Your Impact: Ownership: Lead the complete PnR flow (Floorplan, Placement, CTS, Routing) for multi-million gate IP/SoC blocks. Closure: Drive timing, power, and physical signoff (DRC/LVS) to convergence. Optimization: Solve complex congestion, IR drop, and signal integrity issues in FinFET technologies. Mentorship: Guide junior engineers on flow me...

As a Hardware Engineer at Qualcomm India Private Limited, your primary role will involve planning, designing, optimizing, verifying, and testing electronic systems. You will work on various aspects such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams will be essential to meet performance requirements. Key Responsibilities: - Plan, design, and optimize electronic systems - Verify and test circuits, mechanical systems, and various other components - Collaborate with cross-functional teams to develop solutions - Meet perform...

5+ Years Able to make IO Ring and RDL routing. • Should have good hands on of Clock Tree Synthesis using Innovus. • Should be able to perform EMIR analysis with Ansys Redhawk. • Should be able to perform Physical Verification with Calibre

Experience: Expertisein Digital Full Custom Circuit Design and memory architecture development. Responsibilities: Design memory blocks (bitcell, decoding,rowdec, SA, IO block). Develop complex blocks like RA, WA, self-timed read/write circuits. Perform library circuit verification at compiler level (Sense Amp,Selftime, ESPCV). Conduct timing, power, leakagecharacterizationand LVF analysis. Work on CAD tools for IR/EM analysis and high sigma simulations. Technical Skills: Strong knowledge of memory architectures and circuit design. Experience with simulators (XA, Eldo) and CAD tools (RedHawk, MASIS). Familiarity withFinFETtechnology and high sigma analysis.

Role : Sr Physical Design Lead/BE Integration This position is for senior level engineer Full Chip Physical Design/Integrations/ SoC Floor planning/Bump Planning/ Pin Assignments /Feed through/ LFU Optimization/Physical Verification, Power design/implementation/signoff. He must have hands on Physical Design experience and must have handled RTL to GDS II at Top level Key Responsibilities: Expertise in hierarchical RTL2GDSII design implementation Expertise in pin assignment, Power planning, IO/Bump Planning, Pad Ring Creation, Die File Creation, RDL Routing, working with Package Team for Optimize the Bumps Full chip Hierarchical Floor Planning, Block planning , block level constraints, hierarc...

Director- Physical Design About Semifive Founded in Seoul in 2019, SEMIFIVE is basing its foundation on Korea's semiconductor design competency that was amassed for more than 20 years. With expertise spanning front-end to back-end design, SEMIFIVE has become the fastest growing silicon design company that offers the most comprehensive design solutions. SEMIFIVE's core business is its innovative SoC Platform that enables low-cost and high-efficiency SoC design, and also provides full turnkey design services for global customers through its diverse network. As the cost of developing an SoC and the demand for customized silicon continue to grow rapidly, SEMIFIVE's SoC Platform will play a key r...

As a Senior Application Engineer at Ansys, you will play a crucial role in deploying Ansys EDA products, with a primary focus on RedHawk-SC for Power Integrity and EMIR signoff across top Semiconductor companies. Your responsibilities will involve collaborating with Software developers, Architects, and Product Specialists to develop the product and implement it on cutting-edge SoCs in Semiconductor companies. Your key focus areas will include addressing challenges related to IP/SoC/3DIC Power Integrity, Signal Integrity, Reliability aspects such as EM/ESD/Thermal, Advanced timing/jitter, and Packaging on advanced nodes like 7/5/3/2 nm. As a senior member of the Application Engineering Team, ...

Work on Low-power implementation and/or EMIR(electro-migration/IR-drop) analysis of state-of-the-art SOCs at cutting edge FinFET technology nodes for various customers. This position is for a senior-level physical design engineer who will work on Low-power implementation of of a complex SOC/block-level based on UPF/CPF EMIR analysis of complex SOC/Block-level Static/Dynamic analysis, power calculation Work hands-on to solve critical design and execution issues related to low-power, EMIR Own power-domain implementation flows, sign-off methodologies for execution of SoCs Interested can send updated resumes to basheer.unnisa@leadsoc.com

Were Hiring: Physical Design Engineer Location: Bangalore, India Experience: 5+ Years Key Responsibilities: Create IO Ring and RDL routing Perform Clock Tree Synthesis (CTS) using Cadence Innovus Conduct EMIR analysis with Ansys Redhawk Execute Physical Verification using Calibre Requirements: Strong understanding of physical design flow & methodologies Excellent problem-solving and debugging skills Ability to thrive in a fast-paced, collaborative environment Apply Now: Send your resume to surapandey@allegisglobalsolutions.com

Role Overview: You will be responsible for executing internal projects or small tasks of customer projects in the VLSI Frontend, Backend, or Analog design field with minimal supervision from the Lead. Key Responsibilities: - Work as an Individual contributor on tasks such as RTL Design, Module Verification, Physical Design, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, Signoff, etc. - Analyze and complete assigned tasks within defined domains successfully and on-time with minimal support from senior engineers - Ensure quality delivery approved by senior engineers or project lead - Verify quality using relevant metrics by Lead/Manager - Ensure timely delivery as per proje...

The Role We are seeking an experienced Physical Design Manager to lead SoC/IP implementation on advanced nodes (7nm and below). The role requires strong technical expertise, leadership, and ownership of execution from RTL to GDSII for first-pass silicon success. Key Responsibilities Lead end-to-end Physical Design flow (RTL-to-GDSII) for SoCs/IPs. Own floorplanning, placement, CTS, routing, STA, IR/EM, and signoff. Drive PPA optimisation, ECO closure, and physical verification. Collaborate with RTL, verification, architecture, and packaging teams. Lead EDA flow automation and scripting for efficiency. Mentor and manage a high-performing physical design team. Key Skills & Experience Our USP 1...

Position: Physical Design Engineer Experience: 4+ yrs Location: Bangalore, Hyderabad Notice Period: Preferably 0 to 45 days Summary: Strong expertise in Physical Design and RTL-to-GDSII implementation flow, including synthesis, floor planning, place-and-route, timing closure, and sign-off. Proven ability to close full-chip and block-level designs from RTL to GDSII, addressing timing, noise, power, IR drop, physical verification, and equivalence checks. Hands-on experience with advanced technology nodes (7nm, 5nm, and below), managing challenges related to performance, power, and area (PPA). Proficient in Synopsys and Cadence tool suites, including Fusion Compiler, ICC2, Design Compiler, Prim...

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to ...

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to ...

Job Requirements We are looking for a highly experienced and technically strong Senior Lead Physical Design Engineer with 12+ years of hands-on expertise on complex block or subsystem-level physical design on complete RTL to GDSII activities and must be passionate about driving power and area efficiency, methodology innovation, and signoff convergence. Key Responsibilities: Drive RTL-to-GDSII activities including synthesis, floor planning, power planning, , placement, CTS, routing, and signoff tasks. Experience on multi-voltage and multi-power domain designs using UPF and low power verification (VCLP/CLP) Perform dynamic and leakage power analysis (using PTPX) and optimization across design ...

Hi All, Eximietas Hiring Senior Physical Design Leads/Managers (EMIR). Experience: 10+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US. About the job Qualification Required: (EMIR). Block / Subsystem / Partition Role: EM/IR. EDA Tool: Redhawk & Node: TSMC 3nm / 5nm. ESD resistance, PG Grid, Static/Dynamic power, SRP, BQM checks - Running/ Analysis/Fixes. Tcl, Perl, Python Scripting mandatory. Interested Candidates please start sharing your resumes: [HIDDEN TEXT]

Role Overview: You will be joining our Flow Development Team as an EDA Flow Developer, where you will play a crucial role in designing and developing Flows for IR and EM technology-based solutions for ASIC designs. Your main focus will be on ensuring signal integrity, power integrity, and thermal management for cutting-edge projects. Collaborating with cross-functional teams and staying updated with the latest advancements in IR and EM technology will also be key aspects of your role. Key Responsibilities: - Design and develop Flows for IR and EM technology-based solutions for ASIC designs, with a focus on signal integrity, power integrity, and thermal management. - Collaborate with cross-fu...

EDA Flow Developer We are seeking an experienced IR & EM Technology Expert to join our Flow Development Team. The successful candidate will have a strong background in CAD design and a deep understanding of IR & EM technology. This is an excellent opportunity for a motivated individual to contribute to the development of cutting-edge Flows, ensuring the highest level of performance, power efficiency, and reliability. Location: Bangalore Job Description In your new role you will: • Design and develop Flows for IR and EM technology-based solutions for ASIC designs, focusing on signal integrity, power integrity, and thermal management. • Collaborate with cross-functional teams, including archit...

Job Description: Broadcom is looking for a staff level physical design engineer. In this highly visible role, you will be contributing to ASIC for Storage/ AI products. Qualifications: Education and Experience : Master's degree in Electronics/Computer Engineering with over 10 years of experience in physical design. Physical Design Expertise : Extensive experience in Place & Route using Synopsys FC or Cadence Innovus tools is essential. Proficiency in STA using Primetime and/or Tempus. Demonstrated knowledge of Clock Tree Implementation Techniques for High-Speed Design Implementation. Ability to drive front-end and back-end implementation from RTL to GDSII, including synthesis, formal verific...

You will be part of ACE India, in the P-Core design team driving Intel's latest CPUs in the latest process technology. In this position, you will be responsible for power delivery network design, IR Drop analysis, and convergence of complex core design. Your responsibilities will include: - Responsible for power delivery network design including package/bump to device level delivery for over 5GHz frequency and low-power digital designs. - Deep understanding of RV and IR Drop concepts. - Load line definition. - Closely work with SD, Integration, and Floor plan teams. Qualifications: - You must possess a master's degree in Electrical or Electronics Engineering with at least 6 or more years of ...

Job Description: You should have a BTech/MTech in E & C and a minimum of 4 years of experience. Your expertise should include hands-on experience using Redhawk and Voltus tools for IR signoff. Additionally, you should be proficient in both full chip flat and block design closure. Qualification Required: - BTech/MTech in E & C Key Responsibilities: - Hands-on experience using Redhawk and Voltus tools for IR signoff - Proficient in both full chip flat and block design closure,

Job Title: Physical Design Engineer Experience: 4+ Years Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated Physical Design Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure. Key Responsibilities: Own block-level or full-chip implementation from RTL to GDSII. Perform: Floorplanning and placement Clock tree synthesis (CTS) Routing and optimization Run and close timing (STA), IR drop, EM, DRC, LVS, and a...