13 Redhawk Jobs

You will be joining Quest Global, an organization known for its innovation and rapid growth in engineering services. With expertise in various industries and a commitment to excellence, we are on a journey to become a centenary company. We are seeking individuals who are both humble and brilliant, believing that engineering can turn the impossible into possible. As part of our diverse team of engineers, you will play a crucial role in designing a brighter future through your work. We are looking for innovators who are driven by technology and constantly strive to design, develop, and test solutions for our Fortune 500 clients. Collaboration and continuous learning are at the core of our values, as we believe in collective success and growth. The ideal candidate for this role should possess the following characteristics and skills: - Proficiency in physical design at a block level with a thorough understanding of the PnR cycle - Strong grasp of physical design fundamentals - Hands-on experience with industry-standard PnR tools such as ICC2/Innovus - Familiarity with signoff tools like Prime Time, Redhawk, and Calibre - Ability to mentor junior engineers in resolving technical issues - Proficiency in tools such as ICC/Innovus, Prime Time, StarRC, Redhawk, Calibre DRC/LVS - Experience with scripting languages like TCL and Perl If you are an achiever who thrives on challenges and is passionate about driving innovation, we invite you to be a part of our team. Your contributions will be valued, and your growth will be supported as we work together towards success.,

Qualcomm India Private Limited is a leading technology innovator that drives digital transformation to create a smarter, connected future for all. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. The ideal candidate should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3+ years of experience in Hardware Engineering. Alternatively, a Master's degree with 2+ years of relevant experience or a PhD with 1+ year of experience is also acceptable. The desired experience range for this role is 7 to 10 years. Key responsibilities include the physical design of block levels with a full understanding of the PnR cycle, a good grasp of Physical design fundamentals, and hands-on experience with industry-standard pnr tools like ICC2/Innovus. Additionally, familiarity with signoff tools such as Prime Time, Redhawk, and calibre is necessary. The candidate should possess the ability to guide junior engineers in resolving technical issues. Proficiency in tools like ICC/Innovus, PT, StarRC, Redhawk, Calibre DRC/LVS, and scripting languages like TCL and Perl is required for this role. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information and proprietary data. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities at Qualcomm and is not to be used by staffing or recruiting agencies. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not respond to requests for application updates or resume inquiries through the provided email address. For further information about this role, please reach out to Qualcomm Careers.,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. You will work on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. In order to be considered for this role, you must have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience will also be considered. As a Physical Design Electrical Analysis Engineer, you will be responsible for driving the electrical analysis and closure at both the block and top level. The ideal candidate should have 4 to 7 years of experience in EM/IR/PDN. Key responsibilities include performing various electrical analyses at block and top levels, including static/dynamic IR, power/signal EM, and ESD. You will also drive block and top-level electrical verification closure, develop power grid specs based on power/performance/area targets of different SOC blocks, and work closely with the PI team to optimize the overall PDN performance. Additionally, you will collaborate with CAD and tool vendors to develop and validate new flows and methodologies. Preferred qualifications for this role include a BS/MS/PhD degree in Electrical Engineering with 4+ years of practical experience, in-depth knowledge of EMIR tools such as Redhawk and Voltus, experience in developing and implementing power grids, good knowledge of system-level PDN and power integrity, practical experience with PnR implementation, verification, power analysis, and STA, proficiency in scripting languages (TCL/Perl/Python), experience with industry-standard EMIR tools, basic knowledge of the physical design flow and industry-standard PnR tools, and the ability to communicate effectively with cross-functional teams. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you can contact Qualcomm via email at disability-accommodations@qualcomm.com or through their toll-free number. Qualcomm expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. Please note that unsolicited submissions from staffing and recruiting agencies are not accepted. Individuals seeking a job at Qualcomm should use the Careers Site for applications. For more information about this role, you can contact Qualcomm Careers directly.,

Qualcomm India Private Limited is a leading technology innovator that drives digital transformation to create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. The ideal candidate should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field. We are seeking PDN engineers with EMIR and PG planning expertise and a minimum of 4 years of experience. Responsibilities include IR signoff for CPU/high-performance cores, Signal EM & Power EM Signoff for Chip TOP level & Block level CPU/DSP, Development of PG Grid spec for different HM, and validating PG Grid and IR Drops. Additionally, working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations is crucial to enhance PDN Design. The desired skill set includes hands-on experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level, proficiency in scripting languages like Tcl and Perl, and familiarity with tools such as Redhawk, Redhawk_SC, Innovus, and Fusion Compiler. The ability to communicate effectively with global cross-functional teams and experience in Power Planning/Floorplanning and Physical Verification is an added advantage. Qualcomm is an equal opportunity employer committed to providing accessible accommodations for individuals with disabilities during the application/hiring process. If you require assistance, please contact disability-accommodations@qualcomm.com. Abiding by all applicable policies and procedures, including security requirements, is expected from Qualcomm employees. Please note that our Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through this platform. Unsolicited submissions will not be considered. For more information about this role, please reach out to Qualcomm Careers directly.,

Qualcomm India Private Limited is seeking a Hardware Engineer to join their Engineering Group, specifically focusing on Hardware Engineering. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to contribute to the development of cutting-edge, world-class products. Collaboration with cross-functional teams to meet performance requirements is a key aspect of this role. Key responsibilities for this position include: - IR Signoff CPU/high performance cores - Signal EM & Power EM Signoff for Chip TOP level & Block level CPU/DSP and other HMs - Development of PG Grid spec for different HM - Validating the PG Grid using Grid Resistance & Secondary PG Resistance Checks - Validating the IR Drops using Static IR, Dynamic IR Vless & VCD Checks for validating Die & Pkg Components of IR Drops - Working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations to improve overall PDN Design - Good knowledge on PD would is desirable - Proficiency in Python, Perl, TCL The ideal candidate should possess the following qualifications and skills: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field - 4+ years of experience in PDN engineering with EMIR and PG planning expertise - Hands-on experience in PDN Signoff using Redhawk/RHSC/Voltus at block level/SOC Level - Good understanding of Power Integrity Signoff Checks - Proficiency in scripting languages (Tcl and Perl) - Familiarity with Innovus for RDL/Bump Planning/PG eco - Ability to effectively communicate with global cross-functional teams - Experience with tools such as Redhawk, Redhawk_SC, Innovus/Fusion Compiler, Power Planning/Floorplanning, and Physical Verification Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com or Qualcomm's toll-free number. It is essential for Qualcomm employees to adhere to all applicable policies and procedures, including confidentiality requirements. Staffing and recruiting agencies are advised not to use Qualcomm's Careers Site for submissions, as unsolicited applications will not be considered. For more information about this role, please reach out to Qualcomm Careers directly.,

Qualcomm India Private Limited is seeking a Hardware Engineer to plan, design, optimize, verify, and test electronic systems. In this role, you will work on cutting-edge technologies in areas such as Digital/Analog/RF/optical systems, FPGA, and DSP systems to develop world-class products. Collaboration with cross-functional teams is key to meeting performance requirements and creating innovative solutions. Candidates for this position should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 2 years of Hardware Engineering experience. Alternatively, a Master's degree with 1 year of relevant experience or a PhD in a related field is also acceptable. The Qualcomm Noida CPU team is specifically looking for individuals to contribute to the development of high-performance and power-optimized custom CPU cores. Responsibilities include handling the hardening of complex HMs from RTL to GDS, which involves tasks such as Synthesis, PNR, and Timing. Desired experience for this role includes 2-5 years of experience in Physical design and STA. Proficiency in industry-standard tools for physical implementation such as Genus, Innovus, FC, PT, Tempus, Voltas, and redhawk is required. Candidates should have a strong understanding of the design flow from floorplan to PRO, timing signoff, IR drop, and physical verification aspects. Experience in deep submicron process technology nodes and knowledge of high-performance and low-power implementation methods are preferred. Strong fundamentals and expertise in Perl and TCL language are also desired. Qualcomm offers a dynamic and inclusive work environment where employees have the opportunity to collaborate with some of the most talented engineers in the world. The company is committed to providing reasonable accommodations to support individuals with disabilities during the application/hiring process. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies, and individuals represented by an agency are not authorized to apply through the Qualcomm Careers Site. For more information about this role, please reach out to Qualcomm Careers directly.,

You should possess in-depth knowledge and hands-on experience in Netlist2GDSII Implementation, including tasks such as Floorplanning, Power Grid Design, Placement, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), Power Integrity Analysis, Physical Verification, and Chip finishing. It is essential to have experience with Physical Design Methodologies and sub-micron technology, particularly in 16nm and lower technology nodes. Moreover, you should have expertise in Analog and Mixed Signal Design and be familiar with handling designs with more than 5M instance count and operating at a frequency of 1.5GHz. Proficiency in programming languages such as Tcl, Tk, and Perl is required to automate the design process and enhance efficiency. Hands-on experience with PnR Suite from Cadence & Synopsys, specifically Innovus & ICC2, is a must. Additionally, you should have a strong background in Static Timing Analysis using tools like PrimeTime for SI analysis, EM/IR-Drop analysis with PT-PX and Redhawk, as well as Physical Verification using Calibre. Understanding the practical application of methodologies, Physical Design Tools, Flow Automation, and driving improvements in these areas is highly beneficial. Experience in complex SOC integration, Low Power and High-Speed Design, as well as proficiency in Advanced Physical Verification Techniques, are desirable skills for this role.,

Youzentech Technologies is currently seeking an experienced Analog IC Layout Engineer to be a part of our team in Hyderabad. If you possess 5-10 years of expertise in Custom Mixed-Signal Layout Design, we are eager to hear from you. The position is based in Hyderabad/Bangalore and requires the following qualifications and responsibilities: - Proficiency in Full Custom & Semi-Custom Analog IP & IC Layout, starting from schematic to verification - Hands-on experience with various components including Temperature Sensor, SerDes, PLL, ADC, DAC, LDO, Bandgap, Charge Pump, Current Mirrors, Differential Amplifier, and more - Skilled in LVS/DRC debugging & verification for 16FF and below nodes (TSMC, Samsung, GF) - Strong understanding of EM, ESD, Shielding, Parasitic, and Layout-dependent effects - Familiarity with Cadence, Calibre, Assura, Redhawk, and Totem for verification purposes - Experience in supporting multiple Tape-outs and collaborating with cross-functional teams - Knowledge of Layout automation (SKILL/PERL) would be an added advantage - Mandatory experience with TSMC 7nm technology If you meet the requirements and are interested in this opportunity, please share your resume with us at amith.m@youzentech.com.,

When visionary companies need to know how their world-changing ideas will perform, they close the gap between design and reality with Ansys simulation. For more than 50 years, Ansys software has enabled innovators across industries to push boundaries by using the predictive power of simulation. From sustainable transportation to advanced semiconductors, from satellite systems to life-saving medical devices, the next great leaps in human advancement will be powered by Ansys. Innovate With Ansys, Power Your Career. Summary / Role Purpose As Senior Application Engineer, you will be part of the team deploying Ansys EDA products across all top Semiconductor companies. This involves working with Software developers, Architects, & Product Specialists to get the product developed, and deploy it on leading edge SoCs across Semiconductor companies. Key focus areas will include all areas related to IP/SoC/3DIC Power Integrity, Signal Integrity, Reliability aspects like EM/ESD/Thermal, Advanced timing/jitter, Packaging the top challenges for any chip design on advanced nodes like 7/5/3 nm. Key Duties and Responsibilities Be a senior member of Application Engineering Team that: Works with Global-Customers / IP-providers / Foundries to understand design challenges of cutting-edge SoCs & 3DICs on 7/5/3 nm and creates EDA product specifications. Works with Product development team to get state-of-the-art EDA products developed. Works on Ansys-Seascape platform - Semiconductor Industrys First and Only True Big-Data design Platform! Works with top Semiconductor companies around the globe to deploy EDA products for solving Power/Signal/Reliability challenges across Chip-Package-System at 7/5/3 nm. Works on RedHawk and RedHawk-SC to help users and to perform EMIR/power-integrity sign-off analysis. Provides expert guidance / consultation to Customers around the globe for solving design challenges. Minimum Education/Certification Requirements and Experience BS in Engineering, Electrical/Electronics Engineering, Computer Science, or related field with 5 years’ experience, MS with 3 years’ experience, or PhD 3+ years of prior experience in either of a) ASIC Physical design, b) Power-Integrity/Signal-Integrity/Reliability Closure c) Custom circuit design and simulation Bachelor’s/Master’s degree in Electronics Engineering/VLSI from Top Institutions Strong problem-solving skills Good programming skills Excellent verbal and written communication skills Preferred Qualifications and Skills Passion to learn and deploy new technologies. Ability for minimal travel At Ansys, we know that changing the world takes vision, skill, and each other. We fuel new ideas, build relationships, and help each other realize our greatest potential in the knowledge that every day is an opportunity to observe, teach, inspire, and be inspired. Together as One Ansys, we are powering innovation that drives human advancement. Our Commitments: Amaze with innovative products and solutions Make our customers incredibly successful Act with integrity Ensure employees thrive and shareholders prosper Our Values: Adaptability: Be open, welcome whats next Courage: Be courageous, move forward passionately Generosity: Be generous, share, listen, serve Authenticity: Be you, make us stronger Our Actions: We commit to audacious goals We work seamlessly as a team We demonstrate mastery We deliver outstanding results OUR ONE ANSYS CULTURE HAS INCLUSION AT ITS CORE We believe diverse thinking leads to better outcomes. We are committed to creating and nurturing a workplace that fuels this by welcoming people, no matter their background, identity, or experience, to a workplace where they are valued and where diversity, inclusion, equity, and belonging thrive. At Ansys, you will find yourself among the sharpest minds and most visionary leaders across the globe. Collectively we strive to change the world with innovative technology and transformational solutions. With a prestigious reputation in working with well-known, world-class companies, standards at Ansys are high met by those willing to rise to the occasion and meet those challenges head on. Our team is passionate about pushing the limits of world-class simulation technology, empowering our customers to turn their design concepts into successful, innovative products faster and at a lower cost. At Ansys, it's about the learning, the discovery, and the collaboration. It's about the what's next as much as the mission accomplished. And it's about the melding of disciplined intellect with strategic direction and results that have, can, and do impact real people in real ways. All this is forged within a working environment built on respect, autonomy, and ethics. CREATING A PLACE WE'RE PROUD TO BE Ansys is an S&P 500 company and a member of the NASDAQ-100. We are proud to have been recognized for the following more recent awards, although our list goes on: Americas Most Loved Workplaces, Gold Stevie Award Winner, Americas Most Responsible Companies, Fast Company World Changing Ideas, Great Place to Work Certified (China, Greece, France, India, Japan, Korea, Spain, Sweden, Taiwan, U.K.). For more information, please visit us at www.ansys.com Ansys is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, and other protected characteristics. Ansys does not accept unsolicited referrals for vacancies, and any unsolicited referral will become the property of Ansys. Upon hire, no fee will be owed to the agency, person, or entity.

When visionary companies need to know how their world-changing ideas will perform, they close the gap between design and reality with Ansys simulation. For more than 50 years, Ansys software has enabled innovators across industries to push boundaries by using the predictive power of simulation. From sustainable transportation to advanced semiconductors, from satellite systems to life-saving medical devices, the next great leaps in human advancement will be powered by Ansys. Innovate With Ansys, Power Your Career. Summary / Role Purpose As a Product Specialist II , you will be part of the team responsible for overall development and validation of Ansys EDA Products. This involves working with Software developers, Architects, Application Engineers, and Semiconductor Customers, from ideation all the way to final product release and deployment. Key focus areas will include all areas related to IP/SoC/3DIC Power Integrity, Signal Integrity, Reliability aspects like EM/ESD/Thermal, Advanced timing/jitter, Packaging the top challenges for any chip design on advanced nodes like 7/5/3 nm. Key Duties and Responsibilities Be part of Product Engineering Team that Works with Global-Customers / IP-providers / Foundries to understand design challenges of cutting-edge SoCs & 3DICs on 7/5/3 nm and creates EDA product specifications. Works with Software developers to develop state-of-the-art EDA products solving Power-Noise-Reliability challenges across Chip-Package-System Works on Ansys-Seascape platform - Semiconductor Industrys First and Only True Big-Data design Platform! Performs in-depth validation to ensure Product meets accuracy and other requirements. Collaborates with Application Engineers to support Global Customers in solving their design challenges on leading edge SoCs. Minimum Education/Certification Requirements and Experience Bachelor’s/Master’s degree in Electronics Engineering/VLSI from Top Institutions (NITs/IITs and likes) Strong problem-solving skills Good programming skills Excellent verbal and written communication skills Preferred Qualifications and Skills Passion to learn and deploy new technologies. Ability for minimal travel 2-3 years of prior experience in either of a) ASIC Physical design, b) Power-Integrity/Signal-Integrity/Reliability Closure c) Custom circuit design and simulation At Ansys, we know that changing the world takes vision, skill, and each other. We fuel new ideas, build relationships, and help each other realize our greatest potential in the knowledge that every day is an opportunity to observe, teach, inspire, and be inspired. Together as One Ansys, we are powering innovation that drives human advancement. Our Commitments: Amaze with innovative products and solutions Make our customers incredibly successful Act with integrity Ensure employees thrive and shareholders prosper Our Values: Adaptability: Be open, welcome whats next Courage: Be courageous, move forward passionately Generosity: Be generous, share, listen, serve Authenticity: Be you, make us stronger Our Actions: We commit to audacious goals We work seamlessly as a team We demonstrate mastery We deliver outstanding results OUR ONE ANSYS CULTURE HAS INCLUSION AT ITS CORE We believe diverse thinking leads to better outcomes. We are committed to creating and nurturing a workplace that fuels this by welcoming people, no matter their background, identity, or experience, to a workplace where they are valued and where diversity, inclusion, equity, and belonging thrive. At Ansys, you will find yourself among the sharpest minds and most visionary leaders across the globe. Collectively we strive to change the world with innovative technology and transformational solutions. With a prestigious reputation in working with well-known, world-class companies, standards at Ansys are high met by those willing to rise to the occasion and meet those challenges head on. Our team is passionate about pushing the limits of world-class simulation technology, empowering our customers to turn their design concepts into successful, innovative products faster and at a lower cost. At Ansys, it's about the learning, the discovery, and the collaboration. It's about the what's next as much as the mission accomplished. And it's about the melding of disciplined intellect with strategic direction and results that have, can, and do impact real people in real ways. All this is forged within a working environment built on respect, autonomy, and ethics. CREATING A PLACE WE'RE PROUD TO BE Ansys is an S&P 500 company and a member of the NASDAQ-100. We are proud to have been recognized for the following more recent awards, although our list goes on: Americas Most Loved Workplaces, Gold Stevie Award Winner, Americas Most Responsible Companies, Fast Company World Changing Ideas, Great Place to Work Certified (China, Greece, France, India, Japan, Korea, Spain, Sweden, Taiwan, U.K.). For more information, please visit us at www.ansys.com Ansys is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, and other protected characteristics. Ansys does not accept unsolicited referrals for vacancies, and any unsolicited referral will become the property of Ansys. Upon hire, no fee will be owed to the agency, person, or entity.

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 15 years or MSEE/CE + 12 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 15 years or MSEE/CE + 12 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Staff Power Delivery Network and Reliability Engineer Mulya Technologies Greater Bengaluru Area (Hybrid) Staff Power Delivery Network and Reliability Engineer Bangalore Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Power Delivery Network and Reliability Engineer Expertise in Power Grid design and in-depth knowledge of IR drop & EM(electromigration) concepts Knowledge of PDN tool algorithms and hands-on experience with industry-standard tools like Voltus and Redhawk/Redhawk-SC, Exposure to implementation tools like Innovus/ICC2 is a plus Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"