86 Cmos Jobs

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Solid experience of 8 to 12 years in developing high speed IO/ESD/Analog layout design. Expertise in working on FinFet layouts in lower nodes, preference to TSMCN 7nm and below. Expertise in using the best and latest features of Cadence VXL and Calibre DRC/LVS. Basic understanding of IO/ESD designs. Knowledge on Basic /PERL. Capable of working independently and with team and getting work done with contract work force. The ability to work & communicate effectively with global engineering teams.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing ]. We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. Desired experience: 5+ years experience in physical verification post BTECH / MTECH. Expertise in DRC, LVS, PERC, ERC, SOFTCHECK, DFM etc. Efficient fixing of DRCs in INNOVUS OR FC. Completely aware about CALIBRE , VIRTUSO Good scripting skills and automation.

Job Area: Interns Group, Interns Group > Interim Engineering Intern - HW Qualcomm Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary: We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries "” from automotive to health care, from smart cities to robotics"” we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Educational Background:Masters, BachelorsElectrical Engineering , VLSI , Embedded and VLSI , ECE

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Responsibilities: STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS ICC, Innovous , PT/Tempus Familiar with process technology enablementCircuit simulations using Hspice/FineSim, Monte Carlo.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Additional 7-14 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Job Overview In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in addition to developing in-house productivity & QoR automation solutions for improving overall design methodology. Minimum Qualifications Bachelors or masters in electrical engineering, Computer Science, or related field. 6+ years of industry experience in CAD/EDA or PDK development Knowledge of Virtuoso suite of tools- Schematic, Layout, Analog Design Environment etc. Proficiency in one or more of the programming/scripting languages- , Python, Perl and TCL. Good understanding of CMOS fundamentals and Circuit Design Concepts Strong aptitude for programming and automation Good communication skills and ability to work collaboratively in a team environment Preferred Qualifications Familiarity with SPICE simulation tools (Hspice, SpectreX/APS, AFS/Solido SPICE , PrimeSim SPICE, ADS, GoldenGate etc.) Experience with Electromagnetic tools, like Peakview and EMX, is a plus. Knowledge of FinFet & SOI processes is a plus Educational RequiredBachelor's, Electrical Engineering

Role & responsibilities 1) Ability to handle projects independently 2) Should meet productivity and quality per assigned targets 3) Should ensure daily schedule are met. Ability to plan and schedule. Preferred candidate profile 1) In-depth knowledge of copyediting style guidelines and capability to perform review for L1, L2, and L3 projects. 2) Master's Degree in Humanities/STMS - Science or English background 3) Hands-on experience in copyediting STMS and humanities books/journal articles and adequate knowledge of style guides such the Chicago Manual of Style, APA, and the Oxford Style Manual. Experience in handling both humanities and STMS manuscripts is vital. 4) Knowledge of different workflows (books, journals)

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLLAdditional responsibilities:logic (RTL) design, timing closure, CDC analysis etc.Understand and Design Power efficient logic.Agile project planning and execution.Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 5+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

Job TitleAI/ML Engineer - Time Series Forecasting & Clustering LocationBangalore Experience2+ Years Job TypeFull-Time Mandatory Skills: AI/ML Engineer with Time Series Forecasting & Clustering experience Responsibilities in Brief: Time Series Forecasting Build models to predict trends from time series data. Clustering Develop algorithms to group and analyze data segments. Data Insights Analyze data to enhance model performance. Team Collaboration Work with teams to integrate models into products. Stay Updated Apply the latest AI techniques to improve solutions. Qualifications: Education Bachelor s/Master s in Computer Science or related field. Experience Hands-on experience with time series forecasting and clustering. Skills Proficient in Python, R, and relevant ML tools Perks & Benefits: Health and WellnessHealthcare policy covering your family and parents. FoodEnjoy scrumptious buffet lunch at the office every day. Professional DevelopmentLearn and propel your career. We provide workshops, funded online courses and other learning opportunities based on individual needs. Rewards and RecognitionsRecognition and rewards programs in place to celebrate your achievements and contributions. Why join Relanto Health & FamilyComprehensive benefits for you and your loved ones, ensuring well-being. Growth MindsetContinuous learning opportunities to stay ahead in your field. Dynamic & InclusiveVibrant culture fostering collaboration, creativity, and belonging. Career LadderInternal promotions and clear path for advancement. Recognition & RewardsCelebrate your achievements and contributions. Work-Life HarmonyFlexible arrangements to balance your commitments. To find out more about us, head over to our Website and LinkedIn

Good communication skills, Should have exposure of VLSI teaching. Knowledge of advance digital design, Verilog, System Verilog, VHDL, FPGA, CMOS. Hands on experience with industry Standard Tools Having experience of min 3 years in relevant field.

Good communication skills, Should have exposure of VLSI teaching. Knowledge of advance digital design, Verilog, System Verilog, VHDL, FPGA, CMOS. Hands on experience with industry Standard Tools Having experience of min 3 years in relevant field.

Research and analyze emerging memory technologies, to understand their characteristics, advantages, and limitations. Collaborate with system architects and product teams to define memory requirements Health insurance Provident fund Annual bonus

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

You are a skilled Layout Engineer with 3-6 years of experience, specializing in Analog and Mixed-Signal IP layout. You have a background in Electronics or Electrical Engineering, holding a B.Tech or M.Tech degree. You possess a strong understanding of high-speed analog layout and have a solid grasp of CMOS and FinFET layouts. Your expertise extends to using CAD tools such as Custom Designer/Cadence Virtuoso, Calibre, ICV, and STAR-RCXT. You are adapt at working independently, determining and developing solutions with minimal supervision. You frequently collaborate with senior personnel and are proactive in learning new technologies, demonstrating excellent analytical and problem-solving skills. Your strong communication skills enable effective interaction with internal development teams. What You'll Be Doing: Developing physical layout of high-speed Analog Integrated Circuits for the Analog and Mixed Signal IP group. Collaborating with a team of Analog/Mixed Signal Custom Layout Design Engineers on SerDes and Analog Mixed Signal IP blocks. Using advanced floor-planning techniques to optimize layout designs. Performing verification flows and ensuring compliance with DRC/LVS, LPE standards. Debugging and troubleshooting layout issues, utilizing your analytical skills. Providing regular updates to the manager on project status and networking with internal and external personnel. The Impact You Will Have: Contributing to the development of high-performance silicon chips that drive modern technology. Enhancing the reliability and efficiency of Analog and Mixed-Signal IP blocks. Ensuring the successful integration of high-speed signal layouts in cutting-edge applications. Improving the verification and validation processes through meticulous layout designs. Supporting the continuous innovation of Synopsys product offerings. Playing a key role in the development of next-generation electronic devices. What You'll Need: Experience in Analog Mixed-signal IP layout and verification of high-speed analog layout. Advanced understanding of Deep submicron effects and mitigation techniques. Expertise in CMOS and FinFET layouts and process technology. Familiarity with ESD and latchup layout design considerations. Proficiency in CAD tool usage, including Custom Designer/Cadence Virtuoso, Calibre, ICV, and STAR-RCXT.

Skills Requirements: Bachelors or Master s degree, Electrical Engineering, Telecommunication or related fields Proficient with CMOS memory design, circuit simulation, memory layout designs, layout parasitic extraction and knowledge of layout verification tools and debugging techniques. Programming capability- C-Shell, Perl. C++ or Java script a plus Excellent analytical and problem solving skills along with attention to details. Can develop a document, report or presentation for a range of tasks Microsoft Office: Word, Excel, PowerPoint, Shared point and Outlook Self-motivated, self-directed, detailed oriented and well organized Good analytical, problem solving and negotiation skills Ability to lead/mentor trainees and junior engineers as well as lead and manage projects. A strong command of English both verbal and written Strong interpersonal communication and team working skills Professionalism, Critical/Logical thinking, future goals focused High commitment to continuous learning

Requirements- Qualification: BTech/MTech Skills/Experience: MTech+3years / BTech+5years Knowledge of CMOS processes and issues in deep submicron process technologies. CMOS circuit design and layout methodology & flow; basic understanding of analog/mixed signal circuitry, familiarity with basic ESD concepts is an advantage. Familiarity with ASIC design flow. Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus. Ability to execute assigned circuit design tasks with best product quality and efficiency. Good written and verbal communication skills in interactions with internal development teams.

What You ll Need: Looking for 2+yrs experience with BTech / MTech in VLSI / Electronics/Microelectronics Knowledge or hands-onexpertise/analysis of Analog and digital CMOS circuit designs Knowledge on electrical circuit networks and analysis Knowledge or hands-on Verilog/System Verilog languages and supported methodologies like VMM, UVM Must be able write/modify testcases, checkers, scoreboards in a system Verilog based test environment AMS verification experience in high speed Serdes designs supportingmulti-protocols is an advantage. Experience with the Synopsys Analog mixed-signal design tool set is an advantage. Modelling languages Verilog-a/ams can be an advantage Programming/scripting know-how e. g. tcl, perl, python Experience with Linux Good communication skills, ability to take ownership Self-organized to ensure that project timescales are met

What You ll Need: BTech/MTech in Electrical Engineering or related field. Minimum of 3 years of experience with MTech or 5 years with BTech in CMOS circuit design and layout methodology. Strong knowledge of deep submicron process technologies and CMOS processes. Familiarity with JEDEC requirements for DDR interfaces and standards. Experience with ASIC design flow and ESD concepts is an advantage.

Designing and developing high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, clock cells, and other complex circuits. Creating and refining environments for post-layout netlist extraction. Applying your expertise in CMOS device characteristics, design rules, latch-up, and electromigration to ensure robust designs. Optimizing digital circuits for better performance, power, and area (PPA). Performing statistical and variation analysis to enhance the reliability of designs. Collaborating with cross-functional teams to integrate designs into larger systems. The Impact You Will Have: Contributing to the creation of cutting-edge semiconductor technologies that power a wide range of applications. Enhancing the performance and efficiency of standard cell circuits, impacting the overall quality of our products. Driving innovation in power optimization and clock cell design, leading to more energy-efficient solutions. Improving the reliability and robustness of our designs through meticulous analysis and optimization. Collaborating on projects that shape the future of technology and influence industry standards. Leveraging your skills to solve complex engineering challenges, contributing to the success of Synopsys. What You ll Need: Experience in Standard Cell Circuit design of high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, and clock cells. Strong knowledge and hands-on experience in developing environments and extracting post-layout netlists. Good understanding of CMOS device characteristics, design rules, latch-up, and electromigration. Proficiency in digital circuit design and optimization for better PPA. Hands-on experience in statistical/variation analysis

Job Title: Technical Support Engineer (GCS - Multiphysics System Analysis) Organization: GCS Organization, MSA (Multiphysics System Analysis) Role Summary: As a member of the GCS Organization for the MSA (Multiphysics System Analysis), you will partner with world-wide Cadence customers to provide post-sales technical consultation for IC level Power System analysis products, enabling them to implement cutting-edge designs. Key Responsibilities & Activities: Customer Engagement: Work closely with customers to understand and debug complex issues, enabling progress in design cycle phases. Tool Leverage: Help customers leverage the latest tool capabilities and guide them with software implementation in their design methodologies. Knowledge Contribution: Acquire breadth and depth of technical knowledge, gain exposure to latest industry design practices, and demonstrate expertise by authoring high-impact knowledge content. Technology Evolution: Participate in the evolution of key technology solutions for pressing design problems. Product Improvement: Work with product teams to identify and prioritize product improvement initiatives through timely feedback and observations. Support & Satisfaction: Provide technical support for the Voltus product (from the MSA toolset) with focus on productivity and customer satisfaction. Tool/Method Support: Support multiple tools/methods, requiring general domain knowledge and developing business experience. Content Creation: Assist in creation of high-quality and impactful knowledge content in the MSA domain. Independent Work: Work independently at Cadence or customer facilities to deliver quality results according to schedule requirements. Problem Solving: Work on problems of moderate scope that may require analysis of situations, data, or tool problems. Qualifications: Bachelor's Degree: Electrical / Electronics / Electronics and Communication / VLSI Engineering with 5-7 years related experience. Master's Degree: 3-4 years of related experience. PhD: 1 year of related experience. Required Experience & Technical Skills: Industry Experience: 3-7 years relevant industry experience in: EMIR analysis PDN analysis with digital signoff tools Digital Physical implementation (as designer or methodology/flow expert) Strong Background in: Digital logic Design CMOS logic Design Power IR drop analysis Circuit Design and Analysis Digital and Behavioral simulation fundamentals related to IC and Package Design Debugging Expertise: Debugging of Low power and multiple power domain analysis for chip power integrity sign-off. Excellent debugging skills and ability to separate out critical from trivial issues. Ability to solve interface-level problems emanating from IC Implementation side and System analysis side. (Plus) Ability to debug Timing and thermal issues in relation to IR and EM. Cadence Tool Knowledge: Understanding of Digital design toolsets (Genus / Innovus / Tempus / Conformal). Knowledgeable of at least 50% of a given flow; detailed knowledge in one CDN tool, learning others. Ability to analyze customer's environment and evaluate appropriate support solutions. Learning competitive tools/technologies. Hardware Description Languages (HDLs): Good understanding of VHDL, Verilog, System Verilog. Scripting: Knowledge on TCL, Perl, or Python. Required Behavioral Skills: Communication: Strong written, verbal, and presentation skills. Relationship Building: Ability to establish close working relationships with both customer peers and management. Problem Solving: Explore what's possible to get the job done, including creative use of unconventional solutions. Collaboration: Work effectively across functions and geographies. Integrity & Drive: Push to raise the bar while always operating with integrity.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: We are seeking a highly motivated Product Engineer who is passionate about advancing technology and solving complex design challenges You are innovative, dependable, and have a strong technical background in transistor-level analysis With a minimum of 5 years of hands-on experience, you possess exceptional expertise in debugging circuit-level issues for SRAM, RF, ROM memories, and Standard Cells You have a deep understanding of static timing concepts and CMOS engineering fundamentals, coupled with proficiency in TCL or other scripting languages Your excellent communication and social skills enable you to collaborate effectively with cross-functional teams, including R&D, Field AEs, Sales, and Marketing You thrive in a dynamic environment, driving new products and features that exceed customer expectations and contribute to the success of Synopsys, What Youll Be Doing: Drive new products and new product features that exceed customer needs, Work with R&D to enable timely implementation of new products and features, and important bug fixes, Provide consultation to prospective users and/or product capability assessment and validation, Provide tool trainings to customers and Field AEs, Provide technical expertise to sales staff through sales presentations and product demonstrations, Assist the sales staff in assessing potential application of company products to meet customer needs and preparing detailed product specifications for the development and implementation of customer applications/solutions, The Impact You Will Have: Influence technology and solution roadmaps through collaboration with R&D, Ensure overall consistency of end-to-end design and analysis flow to meet customer needs, Drive new tool evaluations and help customers with the adoption and continuous usage of our tools, Enable Chip Design customers to achieve optimal Timing, Power, and Characterization goals, Enhance predictability and productivity for designers through advanced tool features, Identify and resolve design issues early-on, minimizing costly late-stage silicon problems, What Youll Need: BS degree in Electrical Engineering or related field, Minimum of 5 years of recent hands-on experience in transistor-level analysis, Expertise in debugging circuit-level issues for SRAM, RF, ROM memories, and Standard Cells, Proficiency in static timing concepts and CMOS engineering fundamentals, Knowledge of TCL and/or other scripting languages, Who You Are: Innovative and motivated, Dependable and detail-oriented, Excellent communicator and collaborator, Proactive problem solver, Adaptable and eager to learn, The Team Youll Be A Part Of: You will be part of a dynamic and collaborative team focused on developing state-of-the-art Static Timing, Characterization, and Library Modelling tools This team works closely with various departments, including R&D, Field AEs, Sales, and Marketing, to ensure the delivery of high-quality solutions that meet customer needs and drive technological innovation, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Job Summary: We are seeking a highly skilled and experienced Senior Analog Circuit Design Engineer with 8+ years of industry experience in designing and validating precision analog circuits. The ideal candidate will have deep expertise in custom analog/mixed-signal IC design, low-noise and low-power design techniques, and strong analytical skills to drive innovation in next-generation electronic systems. Key Responsibilities: Lead the design, simulation, layout, and validation of analog and mixed-signal circuits (e.g., amplifiers, ADCs/DACs, regulators, PLLs, filters). Define architecture and specifications for analog sub-systems based on system requirements. Collaborate with layout engineers to optimize layout for performance, area, and manufacturability. Perform pre- and post-layout simulations (corner, Monte Carlo, noise, mismatch, etc.). Own and drive IP development from concept through silicon validation and production support. Conduct design reviews and provide mentorship to junior engineers. Work closely with cross-functional teams including digital design, verification, test, and packaging. Support silicon bring-up, debug, and characterization of analog blocks in the lab. Evaluate and select components for board-level analog circuitry when applicable. Qualifications: Bachelors or Master’s degree in Electrical Engineering or related field; Ph.D. preferred. 8+ years of hands-on experience in analog/mixed-signal IC design. Strong knowledge of CMOS/BiCMOS technologies. Expertise in using tools such as Cadence Virtuoso, Spectre, HSPICE, or similar EDA tools. Experience with silicon validation using lab equipment (oscilloscopes, spectrum analyzers, etc.). Proven track record of successful tape-outs and production-quality silicon. Excellent problem-solving and debugging skills. Strong communication and documentation abilities. Preferred Skills: Experience with analog front-end design for sensor interfaces or RF front ends. Familiarity with low-power design for portable/wearable devices. Understanding of layout techniques to mitigate parasitics, latch-up, and ESD. Knowledge of reliability and failure analysis (e.g., electromigration, hot-carrier effects). Experience with scripting languages (Python, Perl, TCL) for automation. Why Join Us? Be part of cutting-edge innovation in analog/mixed-signal technology. Work in a collaborative environment with industry veterans and emerging talent. Competitive compensation, performance bonuses, and comprehensive benefits. Career development opportunities and exposure to global projects. Interested candidates can share their resumes to shubhanshi@incise.in

• Drive Area estimation, Floor Planning, Placement, Routing, Power planning, Verification, EMIR, ESD-LUP Verification & Tape out. • Understanding of low parasitic, high frequency design techniques. • Finfet process & Lower nodes; 2nm/3nm/5nm/7nm Required Candidate profile • Exp with Cadence (Virtuoso), Synopsys (CC), Calibre & ICV verification tools like LVS, DRC, Extraction. • Debugging/fixing LVS/DRC errors • Experience with EMIR, PERC tools. • Skill/TCL scripting.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Overview In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in addition to developing in-house productivity & QoR automation solutions for improving overall design methodology. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications Bachelors or Masters in Electrical Engineering, Computer Science, or related field. 2+ years of industry experience in CAD or PDK development Knowledge of Virtuoso suite of tools- Schematic, Layout, Analog Design Environment etc. Proficiency in one or more of the programming/scripting languages- , Python, Perl and TCL. Good understanding of CMOS fundamentals and Circuit Design Concepts Strong aptitude for programming and automation Good communication skills and ability to work collaboratively in a team environment Preferred Qualifications Familiarity with SPICE simulation tools (Hspice, SpectreX/APS, AFS/Solido SPICE , PrimeSim SPICE, ADS, GoldenGate etc.) Experience with Electromagnetic tools, like Peakview and EMX, is a plus. Knowledge of FinFet & SOI processes is a plus Educational Requirements RequiredBachelor's, Electrical Engineering Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.