40 Calibre Jobs

As a Custom Layout Engineer at our company, you will be responsible for acting as the focal point with customers and leading a team of 3-4 custom layout engineers. Your primary focus will be on analog layout, physical verification, and maintaining PDKs. Your expertise in critical layouts such as PLL, DLL, LNA, VGA, ADC, and LDO will be crucial for this role. Additionally, you should be able to quickly adapt to new technologies, tools, and flows. Key Responsibilities: - Work as a focal point with customers - Lead a team of 3-4 custom layout engineers - Handle analog layout, physical verification, and maintaining PDKs - Demonstrate expertise in critical layouts including PLL, DLL, LNA, VGA, ADC, and LDO - Adapt quickly to new technologies, tools, and flows - Mentor layout engineers - Collaborate with different teams and prioritize work based on project needs Qualifications Required: - BE/B.Tech /ME/M.Tech with 4-6 years of experience - Strong expertise in Custom Layout Standard Cells, I/O, or special analog designs - Experience in Pcell development, maintaining, and modifying PDKs - Proficiency in tools such as Virtuoso, Virtuoso-XL, Calibre, Hercules, and Assura - Expertise in SKILL Programming Language - Strong understanding of Analog Design - Good written and oral communication skills - Ability to clearly document plans In this role, you will play a critical part in the design and development process, ensuring the successful implementation of analog layouts and physical verification. Your ability to lead a team, collaborate with customers, and adapt to new technologies will be key to your success in this position.,

As an RFIC/MMIC Layout Engineer, you will be responsible for the design, planning, scheduling, and execution of Full Chip development involving analog and digital components. Your key responsibilities will include: - Performing Full chip feasibility and die size estimation for different bonding schemes - Demonstrating expertise in floorplan design, power schemes, signal planning, routing, physical verification, and quality check - Ensuring the delivery of quality full chip layout on-schedule while meeting design intent criteria such as Speed, Capacitance, Resistance, Power, Noise, and Area - Handling complex issues and using judgment to select appropriate methods for obtaining results - Establishing strong business relationships with cross-functional teams to facilitate project execution - Collaborating closely with Synaptic Global Analog and Digital Design and CAD engineering teams Your basic qualifications for this role include: - Bachelor's degree in electrical engineering, Electronics, Physics, or a related field - Experience in RF and MMIC design, with expertise in areas such as RF switches, power amplifiers, LNA, VCO, mixers, and couplers layout Preferred skills and experience that would be beneficial for this role: - Solid understanding of active and passive devices, circuits, and electrical fundamentals - Expertise in CMOS, FDSOI, and FinFET fabrication concepts, as well as Deep Nwell and triple well processes - Proficiency in analog layout techniques, electromigration, ESD, latch-up, crosstalk, shielding, and deep sub-micron challenges - Familiarity with SOC and ASIC design flows, procedures, and deliverables - Hands-on experience with tools such as Virtuoso L/XL/GXL, Calibre, PERC, STARRC, Totem, and ESRA - Strong analytical, debugging, and problem-solving skills to resolve layout design challenges and physical verification issues - Ability to work effectively in a cross-functional and multi-site team environment across different time zones - Excellent verbal and written communication skills This job description provides a comprehensive overview of the responsibilities and qualifications required for the RFIC/MMIC Layout Engineer role.,

**Role Overview:** As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams will be essential to meet performance requirements and deliver innovative solutions. **Key Responsibilities:** - Excellent understanding of PV rules such as DRC, LVS, Antenna, Density, DFM, DFY, DPT at lower technology nodes and capable of resolving these issues in Innovus/Fusion compiler. - Proficiency in setting up PV flows like DRC, LVS, and Fill insertion, along with expertise in script-based design cleanup. - Experience with industry standard tools like ICV, Calibre, PVS, Innovus. - Knowledge of Package PV checks, IO/Bump PV cleanup, PDN, Floorplan, and Power planning is advantageous. - Understanding of Layout design. - Familiarity with Python, SVRF, TCL, Perl scripting is a plus. - Ability to address Calibre DRC, LVS, antenna issues based on PNR based markers. - Previous experience in leading a team is desirable. - Preferred experience in Innovus based RDL, floorplan, and PNR. **Qualifications Required:** - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of Hardware Engineering or related work experience. - OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering or related work experience. - OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 1+ year of Hardware Engineering or related work experience. - 5-8 years of overall experience. - Knowledge of Python, SVRF, TCL, and Perl scripting is an added advantage. **Additional Company Details:** Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you can contact disability-accommodations@qualcomm.com or Qualcomm's toll-free number. The company emphasizes compliance with all policies and procedures, including security protocols for protecting confidential information. Staffing and recruiting agencies are not authorized to use Qualcomm's Careers Site.,

Join our ambitious team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our mission is to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You will have the opportunity to work on groundbreaking products and collaborate with talented hardware and software engineers to create disruptive infrastructure solutions that excite our customers. We are seeking talented engineers experienced in physically implementing large-scale networking and computing semiconductor products. You will be part of a dynamic startup environment and contribute to the full lifecycle of complex chip development, from CAD tool flow setup to physical verification and tapeout. This role is based in India, with options for hybrid/remote work. Candidates capable of in-office participation in Hyderabad or Bangalore are preferred. Responsibilities: - Develop and maintain the CAD tool flow for physical implementation in a cloud-first environment. - Collaborate with architects on chip-level floorplan and block partitioning, considering tradeoffs in functional partitioning and interface complexity. - Design major physical structures like clock architecture, power delivery network, and interconnect topologies. - Execute physical implementation at block, cluster, and top levels, including synthesis, floorplan, timing closure, and tapeout. - Liaise with foundry and library partners on 3rd party IP integration and process technology issues. Skills/Qualifications: - Proven track record in physical implementation of high-performance network switching/routing fabrics, NICs, CPUs, or GPUs in the latest silicon process nodes. - Proficiency in CAD tools like Cadence Genus, Synopsys ICC2, and analysis tools such as Redhawk. - Experience with scripting languages like Perl, Python, and SystemVerilog. - Minimum BSEE/CE + 10 years or MSEE/CE + 5 years experience with products shipped in high volume. Company Background: We are a well-funded startup based in Mountain View, CA, founded by industry veterans and backed by top-tier investors. Our diverse team excels in co-designing hardware/software solutions and has a proven track record in processing global data center traffic. Note: The above job description is based on the mentioned details in the provided job description.,

The role involves layout design of memory circuit/digital design on the latest technology nodes. As an Engineer, you are expected to have a good attitude, seek new challenges, possess good analytical and communication skills. You should have the ability and desire to learn quickly and excel as a team player. Your key responsibilities will include implementing the layout of digital circuits, conducting DRC, LVS, and other physical verification checks, designing floor-plans, routing, addressing crosstalk fixes, electro-migration fixes, and IR fixes. You will also be handling different tools such as Calibre and Virtuoso. Preferred experience for this role includes a strong background with tools for schematics and layout, proficiency in scripting languages to automate layout flow, excellent communication skills, ability to multitask across projects, collaborate with geographically spread-out teams, experience in FinFET & Dual Patterning nodes like 16/7/5/3nm, a good understanding of CMOS basics and digital circuits, strong analytical and problem-solving skills with attention to detail. To qualify for this position, you should hold a Bachelor's degree in Electronics/Electrical Engineering and possess skills in electro-migration fixes, design rule checking (DRC), physical verification checks, layout design, scripting languages, LVS, Calibre, crosstalk fixes, routing, IR fixes, Virtuoso, skill scripts, floor-plan design, and digital design.,

As a Physical Verification Engineer at Alphawave Semi, you will play a crucial role in accelerating data communication for the digital world of tomorrow. Your responsibilities will revolve around implementing Physical Verification processes with a focus on project completion and tapeout activities. You will be tasked with owning and executing the Physical Verification flow, showcasing expertise in analyzing and resolving issues related to DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck using tools like Calibre/ICV. Collaborating closely with the PD team, you will address PV challenges and contribute to SoC-level PV sign-off checks. To excel in this role, you should bring to the table at least 10 years of experience in Physical Verification, along with a strong background in checks such as DRC, LVS, Antenna, ERC, PERC, ESD using Calibre/ICV. Your proficiency in debugging and rectifying issues related to base DRC, metal DRC, particularly in advanced process nodes, will be essential. Hands-on experience in fixing DRC/LVS in environments like Innovus/Fusion Compiler is a must, along with expertise in LVS/antenna debugging and runtime reduction techniques. Additionally, you should possess scripting skills in Unix, Perl, Python, SVRF, and Tcl to facilitate timely tapeouts, and a solid understanding of full chip integration and flows would be advantageous. At Alphawave Semi, we prioritize the well-being and growth of our employees. We offer a flexible work environment that supports personal and professional development. In addition, you will benefit from a comprehensive compensation package, including Restricted Stock Units (RSUs), opportunities for advanced education from premium institutes and eLearning providers, medical insurance, wellness benefits, educational assistance, advance loan support, and office lunch and snacks facilities. Alphawave Semi is committed to fostering a diverse and inclusive workplace. We are an equal opportunity employer that values diversity and provides accommodations throughout the recruitment process to ensure all applicants have an equal opportunity to thrive, irrespective of age, gender, race, disability, or other protected characteristics.,

Wipro Limited is a leading technology services and consulting company dedicated to creating innovative solutions that cater to the most complex digital transformation requirements of clients. With a global presence spanning 65 countries and a workforce of over 230,000 employees and business partners, Wipro is committed to helping customers, colleagues, and communities thrive in an ever-evolving world. For more information, please visit www.wipro.com. As a Physical Design Lead, you will be based in Bangalore, Hyderabad, or Pune with a minimum of 8 years of experience. Your responsibilities will include handling Netlist2GDSII Implementation tasks such as Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, and Physical Verification. You should possess expertise in Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Proficiency in programming languages like Tcl/Tk/Perl and hands-on experience with Synopsys/Cadence tools (Innovus, ICC2, Primetime, PT-PX, Calibre) is essential. Additionally, you should be well-versed in timing constraints, STA, and timing closure. Your key duties will involve leading end-to-end VLSI components and hardware systems, providing customer support and governance of VLSI components and hardware systems, and managing a team. You will be responsible for resourcing, talent management, performance management, and employee satisfaction and engagement within your team. In terms of deliverables, you will be evaluated based on verification timeliness, quality, and coverage, compliance with UVM standards, customer responsiveness, project documentation and MIS generation, team training on new skills, team attrition percentage, and employee satisfaction score (ESAT). The mandatory skills required for this role include expertise in VLSI Physical Place and Route with 5-8 years of experience. If you are inspired by reinvention and are looking to evolve your career in a dynamic environment, Wipro offers the opportunity to be part of a modern, purpose-driven organization that empowers you to design your own reinvention. Join us at Wipro and realize your ambitions. Applications from individuals with disabilities are warmly welcomed.,

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors in a fast-paced environment with cutting-edge technology. THE PERSON: Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high-performance designs. Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc. Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow - Perl/Tcl/Python Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in advanced sub 7nm nodes Excellent physical design and timing background. A good understanding of computer architecture is preferred. Strong analytical/problem-solving skills and pronounced attention to detail. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering #LI-SR4 Benefits offered are described: . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

You will be responsible for executing internal projects or small tasks within customer projects related to VLSI Frontend, Backend, or Analog design with minimal supervision from the Lead. Your role will involve working as an Individual contributor on tasks such as RTL Design, Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will be expected to analyze and complete assigned tasks within the defined domain successfully and on time with minimal support from senior engineers, ensuring quality delivery as approved by the senior engineer or project lead. Quality of deliverables is a key focus, requiring clean delivery of modules that are easy to integrate at the top level, meeting functional specifications and design guidelines without deviation. Timely delivery is crucial, meeting project timelines set by the team lead or program manager and assisting in the delivery of intermediate tasks by other team members to ensure overall progress. Teamwork is essential, involving active participation and support for team members when needed, along with the ability to perform additional tasks if necessary. Innovation and creativity are encouraged, with a proactive approach towards automating tasks to save design cycle time and active participation in technical discussions. Your skills should include proficiency in languages and programming such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Spice. Familiarity with EDA tools like Cadence, Synopsys, and Mentor, along with technical knowledge in areas such as IP Spec Architecture, Micro Architecture, Bus Protocols, Physical Design, Circuit Design, and Analog Layout is required. Knowledge of technology including CMOS, FinFet, FDSOI, and experience in previous projects related to RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, or Analog Layout is beneficial. You should possess strong communication skills, good analytical reasoning, problem-solving abilities, attention to detail, and the capability to learn new skills as required. Delivering tasks with quality and on time, per quality guidelines and GANTT, is essential. Your role as an Assistant Engineer at UST will involve executing Standard Cell characterization tasks, debugging failures, and utilizing tools such as PrimeLib, Liberate, Redhawk, and CCSP/PGV characterization. Experience in Python coding and API coding is a plus. A Bachelor's or Master's degree in Engineering is required with 2-8 years of relevant experience.,

As an EPUB & XML Developer at Exatech in Venjaramoodu, with 12 years of experience, you will play a crucial role in supporting the digital publishing team. Your responsibilities will involve creating, editing, and troubleshooting EPUB files using HTML, CSS, and XML. Collaborating closely with content teams, you will ensure seamless digital publication experiences across various platforms. Your key responsibilities will include developing and converting content into EPUB formats, creating responsive and accessible digital books, and maintaining high-quality standards for layout, typography, and formatting. Additionally, you will troubleshoot EPUB validation issues, convert from other formats to clean HTML/EPUB, and implement interactive and rich media elements as required. Your role will also involve collaborating with content writers, designers, and developers to deliver exceptional digital publishing solutions. To excel in this role, you should possess strong knowledge of HTML5 and CSS3, along with experience working with EPUB2 and EPUB3 standards. Familiarity with XML, XHTML, and JavaScript for EPUB enhancements is essential, as well as knowledge of accessibility standards such as WCAG and ARIA. Proficiency in tools like Sigil, Calibre, Adobe InDesign, Oxygen XML Editor, and version control tools like Git is beneficial. Preferred qualifications for this position include a Bachelor's degree in Computer Science, Publishing, or related field, experience with LMS platforms or e-learning content, basic scripting knowledge in Python and JavaScript, and an understanding of digital rights management (DRM) systems. In return, you will have the opportunity to work with leading publishers, receive continuous learning and upskilling support, and follow a day shift schedule from Monday to Saturday. Join us in shaping the future of digital publishing with your expertise in EPUB & XML development.,

You are a skilled embedded non-volatile memory (eNVM) Bitcell Layout Design Engineer / Lead interested in joining the eNVM team at Tata Electronics Private Limited (TEPL) to lead the development and optimization of eNVM bitcells. In this role, you will be responsible for designing layout and implementing eNVM bitcells across a wide range of Foundry CMOS technologies, from 130nm to 28nm, including BCD and advanced FinFET technology nodes. Your work will contribute to building high-yield, high-performance memory IP for various applications in automotive, IoT, and mobile markets. To excel in this position, you should ideally have 5-10 years of experience in the semiconductor industry with expertise in memory bit cell and array layout. A background in microelectronics, semiconductor physics, or related fields (Bachelors, Masters, or PhD) is preferred. Proficiency in using EDA tools such as Cadence or Calibre for layout design, including verification by DRC and LVS, is essential. Additionally, knowledge of memory bit cells and arrays like SRAM, MRAM, RRAM, components included in PDK, and experience with bench measurement would be advantageous. Your responsibilities will involve designing eNVM bitcell layout (eFuse, eFlash, RRAM, MRAM) across various foundry processes, creating, optimizing, and verifying bitcell kits, conducting root cause analysis of device and bitcell issues, driving infrastructure improvement for bitcell kit and SLM creation, evaluating foundry PDK changes, and collaborating with design & layout teams to fix violations. Moreover, you will work with diverse engineering teams in different geographic locations and time zones, provide advice on ESD & latch-up prevention techniques, and contribute to indigenous IP development and filing disclosures. For the lead position, strong leadership skills with experience in mentoring and motivating high-performing teams are expected. Effective communication and collaboration across global, cross-functional groups, adaptability to diverse environments, curiosity, resilience, data-driven problem-solving, humility, innovation, and agility are desirable attributes for this role. If you are passionate about driving innovation in eNVM bitcell layout design and keen on contributing to the development of cutting-edge semiconductor products at Tata Electronics, we welcome you to apply for this exciting opportunity.,

Experience: 3 to 10 Years Employment Type: Full-Time Notice Period: 30 Days Key Responsibilities: 1. Design and implementation of custom analog and mixed-signal layouts for circuits such as amplifiers, ADC/DACs, PLLs, and more. 2. Perform layout verification tasks, including DRC, LVS, and parasitic extraction using industry-standard tools. 3. Optimize layout designs for performance, area, and power while ensuring compliance with design rules and process constraints. 4. Collaborate closely with circuit design engineers to interpret specifications and requirements. 5. Participate in design reviews and contribute to the enhancement of layout methodologies. 6. Work on advanced nodes, ensuring high-quality layouts for high-performance, low-power designs. Required Skills and Qualifications: 1. Experience: 3 to 10 years in analog layout design, with expertise in full-custom IC design. 2. Proficiency in layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or equivalent. 3. Strong knowledge of semiconductor process technologies, including FinFETs and advanced nodes (e.g., 7nm, 5nm). 4. Hands-on experience with parasitic-aware design, matching, and signal integrity. 5. Familiarity with EDA tools for verification, such as Calibre or Assura. 6. Excellent analytical and problem-solving skills with attention to detail. 7. Strong communication and interpersonal skills to work effectively in a team environment. What We Offer: 1. Competitive compensation package and benefits. 2. Opportunity to work on innovative and challenging projects. 3. Dynamic and collaborative work environment. 4. Career growth and learning opportunities. Apply Now! If you meet the above qualifications and are ready to take on this exciting challenge, we would love to hear from you. Share your resumes at info@silcosys.com

About the Role: We are seeking a talented and experienced Analog Layout Engineer to join our team in Bangalore. The ideal candidate will have a strong background in analog layout design and will contribute to the development of cutting-edge semiconductor products. If you are passionate about VLSI design and eager to work in a collaborative, innovation-driven environment, this opportunity is for you! Location: Bangalore Experience: 3 to 10 Years Employment Type: Full-Time Notice Period: 90 Days Key Responsibilities: 1. Design and implementation of custom analog and mixed-signal layouts for circuits such as amplifiers, ADC/DACs, PLLs, and more. 2. Perform layout verification tasks, including DRC, LVS, and parasitic extraction using industry-standard tools. 3. Optimize layout designs for performance, area, and power while ensuring compliance with design rules and process constraints. 4. Collaborate closely with circuit design engineers to interpret specifications and requirements. 5. Participate in design reviews and contribute to the enhancement of layout methodologies. 6. Work on advanced nodes, ensuring high-quality layouts for high-performance, low-power designs. Required Skills and Qualifications: 1. Experience: 3 to 10 years in analog layout design, with expertise in full-custom IC design. 2. Proficiency in layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or equivalent. 3. Strong knowledge of semiconductor process technologies, including FinFETs and advanced nodes (e.g., 7nm, 5nm). 4. Hands-on experience with parasitic-aware design, matching, and signal integrity. 5. Familiarity with EDA tools for verification, such as Calibre or Assura. 6. Excellent analytical and problem-solving skills with attention to detail. 7. Strong communication and interpersonal skills to work effectively in a team environment. What We Offer: 1. Competitive compensation package and benefits. 2. Opportunity to work on innovative and challenging projects. 3. Dynamic and collaborative work environment. 4. Career growth and learning opportunities.

About Tata Electronics: Tata Electronics, a wholly owned subsidiary of Tata Sons Pvt. Ltd., is at the forefront of building India's first AI-enabled state-of-the-art Semiconductor Foundry. The cutting-edge facility is dedicated to producing chips for a wide range of applications including power management IC, display drivers, microcontrollers (MCU), and high-performance computing logic. These chips cater to the increasing demand in sectors like automotive, computing, data storage, wireless communications, and artificial intelligence. Tata Electronics, being a subsidiary of the prestigious Tata group, aligns itself with the group's global mission of enhancing the quality of life in communities worldwide through sustainable value creation and leadership built on trust. Key Responsibilities: - Collaborate closely with customers to comprehend their design requirements and extend technical support throughout the project lifecycle. - Aid customers in configuring their design environment utilizing the Foundry provided PDKs, design rules, and reference flows. - Identify, troubleshoot, and resolve design issues including DRC, LVS, peracetic extraction, and other verification checks to ensure a successful tapeout. - Engage in internal collaboration with PDK, IP, and CAD teams to provide valuable feedback to customers. - Proficiency in utilizing relevant EDA tools such as Virtuoso, Custom compiler, Calibre, and PrimeTime. - Willingness to travel to customer sites as needed. Qualifications: - Bachelor's or master's degree in electrical engineering or a related field. - Demonstrated experience of a minimum of 8 years as an analog chip designer or in customer support. - Strong problem-solving abilities and adeptness at working under pressure. - Excellent communication and interpersonal skills. - Hands-on experience with EDA tools like Cadence, Synopsys, and Mentor Graphics.,

As an Analog Layout Engineer with 3-5 years of experience in advanced semiconductor technologies (5nm and below), you will be responsible for executing full custom layout designs for high-speed analog and mixed-signal blocks. Your expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre will be crucial in collaborating closely with circuit design teams to interpret and implement layout specifications. Your key responsibilities will include performing layout verification, ensuring compliance with foundry design rules and layout best practices, addressing issues related to electromigration, IR drop (EMIR), and layout-dependent effects, as well as optimizing layouts for performance, area, and reliability across PVT corners. Additionally, you will support tape-out and post-layout verification activities, participate in design reviews, and maintain proper documentation of layout guidelines and review skills. You should have proven experience in custom analog layout for high-speed and precision circuits, a strong working knowledge of FinFET nodes, proficiency in layout tools like Cadence Virtuoso and Calibre, and sound knowledge of DRC, LVS, and EMIR verification methodologies. Understanding of layout effects such as matching, shielding, symmetry, and noise isolation, as well as familiarity with EDA scripting (Skill, Tcl, Python), will be beneficial. Strong problem-solving skills, attention to detail, and good communication and collaboration abilities in a team-based environment are essential for success in this role. Join us to work on cutting-edge layout challenges with the latest process technologies and be a part of a fast-growing semiconductor team working on impactful silicon designs. Competitive compensation and career development opportunities await you in this exciting opportunity.,

As a Physical Design Engineer with 4+ years of experience, you will be responsible for Netlist2GDSII Implementation including Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, and Physical Verification. Your expertise should cover Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes. Proficiency in programming languages like Tcl, Tk, and Perl is essential for this role. You should have hands-on experience with Synopsys and Cadence tools such as Innovus, ICC2, Primetime, PT-PX, and Calibre. Being well-versed in timing constraints, STA, and timing closure will be crucial for successful execution of projects. Your role will require inspirational leadership, effective communication skills, and the ability to collaborate in a global environment. Overall, your responsibilities will revolve around ensuring the successful implementation of physical design tasks, adhering to project timelines, and maintaining high quality standards throughout the process. Your contributions will play a key role in the development of cutting-edge semiconductor products.,

The position involves working at Samsung Semiconductor India Research (SSIR) on cutting-edge semiconductor technologies like Foundation IP Design, Mobile SoCs, 5G/6G solutions, etc. As one of Samsung Electronics" largest R&D centers outside Korea, the team at SSIR works on diverse projects and technologies. Innovation and creativity are highly valued at SSIR to provide high reliability and performance in delivering world-class products. The responsibilities include physical implementation of complex SOC top designs for mobile application processors, modem sub-systems, and connectivity chips. The role requires expertise in Synthesis, Place and Route, STA, timing closure, and physical signoffs. The candidate should have hands-on experience in physical design, floor planning, pin placement, and high-speed signal planning. Understanding timing, power, and area trade-offs, along with optimization of PPA, is essential. Applicants should be proficient in industry-standard tools like ICC, DC, PT, VSLP, Redhawk, etc., and have scripting knowledge in Perl/Tcl. Experience with large SOC designs, synthesis optimization, low power checking, logic equivalence checking, and physical design verification is required. Familiarity with deep sub-micron designs, SOC issues, hierarchical design, and physical convergence is a plus. The ideal candidate should have a minimum of 5 years of experience in semiconductor design and hold a degree in B.Tech/B.E/M.Tech/M.E. Samsung Semiconductor India Research values diversity and provides Equal Employment Opportunity to all individuals, irrespective of their background or characteristics. Skills and Qualifications: - 5+ years of experience in semiconductor design - Proficiency in physical design tools and methodologies - Strong scripting skills in Perl/Tcl - Knowledge of deep sub-micron designs and SOC issues - Degree in B.Tech/B.E/M.Tech/M.E Please note that Samsung Semiconductor India Research (SSIR) is committed to diversity and Equal Employment Opportunity for all candidates.,

You will be joining Quest Global, an organization known for its innovation and rapid growth in engineering services. With expertise in various industries and a commitment to excellence, we are on a journey to become a centenary company. We are seeking individuals who are both humble and brilliant, believing that engineering can turn the impossible into possible. As part of our diverse team of engineers, you will play a crucial role in designing a brighter future through your work. We are looking for innovators who are driven by technology and constantly strive to design, develop, and test solutions for our Fortune 500 clients. Collaboration and continuous learning are at the core of our values, as we believe in collective success and growth. The ideal candidate for this role should possess the following characteristics and skills: - Proficiency in physical design at a block level with a thorough understanding of the PnR cycle - Strong grasp of physical design fundamentals - Hands-on experience with industry-standard PnR tools such as ICC2/Innovus - Familiarity with signoff tools like Prime Time, Redhawk, and Calibre - Ability to mentor junior engineers in resolving technical issues - Proficiency in tools such as ICC/Innovus, Prime Time, StarRC, Redhawk, Calibre DRC/LVS - Experience with scripting languages like TCL and Perl If you are an achiever who thrives on challenges and is passionate about driving innovation, we invite you to be a part of our team. Your contributions will be valued, and your growth will be supported as we work together towards success.,

Qualcomm India Private Limited is a leading technology innovator that drives digital transformation to create a smarter, connected future for all. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. The ideal candidate should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3+ years of experience in Hardware Engineering. Alternatively, a Master's degree with 2+ years of relevant experience or a PhD with 1+ year of experience is also acceptable. The desired experience range for this role is 7 to 10 years. Key responsibilities include the physical design of block levels with a full understanding of the PnR cycle, a good grasp of Physical design fundamentals, and hands-on experience with industry-standard pnr tools like ICC2/Innovus. Additionally, familiarity with signoff tools such as Prime Time, Redhawk, and calibre is necessary. The candidate should possess the ability to guide junior engineers in resolving technical issues. Proficiency in tools like ICC/Innovus, PT, StarRC, Redhawk, Calibre DRC/LVS, and scripting languages like TCL and Perl is required for this role. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information and proprietary data. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities at Qualcomm and is not to be used by staffing or recruiting agencies. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not respond to requests for application updates or resume inquiries through the provided email address. For further information about this role, please reach out to Qualcomm Careers.,

You will be joining a leading service provider specializing in IC Design activities ranging from 350nm to 3nm for various Foundry technologies. As a full-time Analog and Mixed Signal IC Layout Designer with 5-10 years of experience, your primary responsibility will involve the design and verification of IC Layouts. This role requires close collaboration with the design team to ensure the delivery of high-quality layout designs for analog and mixed signal integrated circuits. To excel in this role, you should have proficiency in Analog and Mixed Signal IC Layout Design across various technology nodes such as 28nm, 16nm, 12nm, 7nm, 5nm, 3nm, and 2nm. Your experience in working closely with design teams, coupled with your expertise in layout design and verification tools like Virtuoso MXL, GXL, XL, EXL, Assura, PVS, QRC, and Calibre, will be essential. A strong foundation in analog and mixed signal integrated circuits, as well as a thorough understanding of Electrical and Electronics principles, will be advantageous. Your problem-solving skills will be put to the test in this role, along with your ability to communicate effectively and work collaboratively within a team. Ideally, you hold a Bachelor's or Master's degree in Electrical Engineering to support your qualifications for this position.,

We are looking for an experienced Analog Layout Engineer with 8+ years of hands-on experience in full custom layout of analog and mixed-signal blocks. The ideal candidate should have expertise in advanced CMOS technologies and be capable of delivering high-quality layout from specifications to tape-out. Key Responsibilities: Execute full custom layout for analog/mixed-signal blocks (OpAmps, Bandgaps, LDOs, ADCs, etc.) Floorplanning, device matching, parasitic optimization, and electromigration compliance Perform DRC/LVS/ERC checks and work closely with verification teams Collaborate with circuit designers to optimize performance and area Ensure quality layout delivery in accordance with tape-out schedules Support post-layout simulation and debug efforts Requirements: 8+ years of experience in analog/custom layout Strong understanding of matching, shielding, and analog layout best practices Hands-on experience with layout tools (Virtuoso, IC Compiler, Calibre, etc.) Knowledge of various technology nodes (180nm to FinFET) Good communication, teamwork, and problem-solving skills Apply Now! If you meet the above qualifications and are ready to take on this exciting challenge, we would love to hear from you. Share your resumes at info@silcosys.com

As a Senior Physical Design Engineer, you will be responsible for leading the Netlist-to-GDSII implementation process on advanced submicron technology nodes. Your expertise in utilizing industry-standard EDA tools and your understanding of timing closure and physical verification will be crucial for this role. Your key responsibilities will include driving the entire Netlist-to-GDSII flow, which involves tasks such as floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. You will also be required to conduct Static Timing Analysis (STA) to ensure timing closure across all design corners, as well as execute power integrity and physical verification checks (LVS, DRC). Collaboration with cross-functional teams including RTL, STA, packaging, and DFT will be essential to successfully handle complex designs on 28nm and below technology nodes. To excel in this role, you must possess strong hands-on experience with tools such as Synopsys/Cadence Innovus, ICC2, Primetime, PT-PX, and Calibre, along with a solid understanding of Physical Design Methodologies including Floorplanning, Placement, CTS, Routing, and STA. Proficiency in timing constraints and closure, Tcl/Tk/Perl scripting, and working with submicron nodes (28nm and below) are also essential skills required for this position. While not mandatory, familiarity with Fusion Compiler, a broader understanding of signal and power integrity, as well as experience in workflow automation and tool scripting would be considered advantageous for this role. If you are excited about the prospect of taking on this challenging and rewarding opportunity, we encourage you to submit your resume to hemanth@neualto.com or spoorthy@neualto.com to express your interest.,

As a skilled professional in Standard Cell Library Development, you will leverage your hands-on experience and expertise to contribute effectively to the characterization processes. Your solid understanding of CMOS and FinFET technologies will be key in ensuring the success of the projects at hand. Additionally, exposure to Verilog modeling will be advantageous in this role, although it is not mandatory. Your role will require strong debugging and problem-solving skills specifically related to cell design, SPICE simulation, and characterization. This will enable you to address challenges effectively and ensure the quality of the developed libraries. Proficiency in EDA tools is essential for this position. Experience with tools such as Cadence Virtuoso, Calibre, HSPICE, and other industry-standard simulation and characterization tools will be beneficial in carrying out your responsibilities efficiently. Overall, your role will be crucial in contributing to the development of Standard Cell Libraries, and your expertise will play a vital part in the success of the projects.,

5+y in Physical design verification,Power analysis Tcl,AWK,python scripting Calibre,Innovus,Voltus layout edits in Innovus,power reports(IR, EM) from Voltus DRC report from Calibre fixing in Innovus IR,EM reports from Voltus fixing in Innovus

You will be responsible for executing customer projects independently with minimum supervision, guiding team members technically in various fields of VLSI Frontend Backend or Analog design. As an individual contributor, you will take ownership of tasks/modules such as RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, Signoff, etc., leading the team to achieve results. Your responsibilities will include completing assigned tasks successfully and on-time within the defined domain(s), anticipating, diagnosing, and resolving problems, coordinating with cross-functional teams as necessary, delivering on-time quality work approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost accepted by UST Manager and Client. Additionally, you will be expected to write papers, file patents, and devise new design approaches. Your performance will be measured based on the quality of deliverables, timely delivery, reduction in cycle time and cost, number of papers published, number of patents filed, and number of trainings presented to the team. You will be expected to ensure zero bugs in the design/circuit design, deliver clean design/modules for ease of integration, meet functional specifications/design guidelines without deviation, and document tasks and work performed. Furthermore, you will be responsible for meeting project timelines, facilitating other team members" progress by delivering intermediate tasks on time, and seeking help and support in case of any delays. Your role will also involve active participation in team work, supporting team members as needed, anticipating when support may be required, and being able to explain project tasks and support delivery to junior team members. Your creativity and innovation will be showcased through tasks such as automating processes to save design cycle time, participating in technical discussions, training forums, white paper or patent filings, and contributing to technical discussions. Your skill set should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, Makefile, Spice, and familiarity with EDA Tools like Cadence, Synopsys, Mentor tool sets, and various simulators. You should have strong technical knowledge in IP Spec Architecture Design, Micro Architecture, Bus Protocols, Physical Design, Circuit Design, Analog Layout, Synthesis, DFT, Floorplan, Clocks, P&R, STA, Extraction, Physical Verification, Soft/Hard/Mixed Signal IP Design, and Processor Hardening. Additionally, you should possess communication skills, analytical reasoning, problem-solving skills, and the ability to interact effectively with team members and clients. Your knowledge and experience should reflect leadership and execution of projects in areas such as RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and understanding of design flow and methodologies. Independent ownership of circuit blocks, clear communication, diligent documentation, and being a good team player are essential attributes for this role. Overall, your role will involve circuit design and verification of Analog modules in TSMC FinFet technologies, developing circuit architecture, optimizing designs, verifying functionality, performance, and power, as well as guiding layout engineers. Strong problem-solving skills, results orientation, attention to detail, and effective communication will be key to your success in this position.,