69 Calibre Jobs

Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level) Active participation in post silicon validation, correlation and test activities using in-house test and validation lab Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Quartz, Calibre, internal tools & flow Perform custom RF Physical Design, including block-level and top level layouts...

As a Physical Verification Engineer, you will be responsible for the following: - Hands-on debugging skills in different physical verification checks like LVS, DRC, ERC, PERC, Antenna, ESD, and DFM using tools such as Calibre, ICV, and Pegasus PV. - Knowledge of basic device physics and PV fixing using various PnR tools like Innovus/ICC2 is required. - Working experience in cutting-edge technologies such as 3/4/5nm and 7nm process nodes is desired. Qualifications required for this role: - B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent. Please note that the job location for this role is Bangalore, Hyderabad, or Noida.,

Role Overview: You are required to lead the end-to-end VLSI components and hardware systems, providing customer support and governance of VLSI components and hardware systems, and managing the team effectively. Key Responsibilities: - Design, analyze, develop, modify, and evaluate VLSI components and hardware systems - Determine architecture and logic design verification through software for component and system simulation - Conduct system evaluations, make appropriate recommendations, and review data and project documentation - Identify and recommend system improvements for better technical performance - Inspect VLSI components and hardware systems for compliance with regulations and safety...

We are seeking a highly skilled and collaborative Analog Layout Engineer to join our team. The ideal candidate will have extensive experience in analog layout in advanced CMOS technologies and be proficient with industry-standard tools. This role requires strong problem-solving abilities, excellent communication skills, and the capacity to work closely with circuit designers to meet stringent design specifications. Roles and Responsibilities: Perform layout in advanced CMOS technologies , including floor planning, placement, routing, DRC (Design Rule Checking), LVS (Layout Versus Schematic) , and other related tasks. Demonstrate experience working on various technology nodes such as 22nm, 28...

Role Overview: As a Senior Package Layout Engineer at NVIDIA, you will play a crucial role in collaborating with the Technical Package Lead and various design teams to develop detailed layout of IC substrates for NVIDIA products. Your responsibilities will involve working on high-speed/density ASIC packages, optimizing package pinout, performing package routing and placement, proposing layout design trade-offs, and developing methodologies to enhance layout productivity. Key Responsibilities: - Collaborate with the Layout team to implement high speed/density ASIC packages - Perform substrate breakout patterns for ASIC packages - Optimize package pinout considering system level trade-offs - A...

Key Responsibilities: Include the development and preparation of multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Working on layout design of owned blocks with Cadence Virtuoso XL. Working on block and top-level level layout verification with Calibre. Extensive PAD Ring and Top /Chip leve l layout experience Working with analog/mixed-signal and digital design teams to ensure proper layout design Block level floor planning and layout IC top level floor planning and area estimation Using recommended layout and verification techniques, tools, and flows to produce optimal designs Generate post-layout...

Role Overview: You are expected to execute any sized customer projects independently with minimum supervision and guide team members technically in any field of VLSI Frontend Backend or Analog design. As an Individual contributor, you will take ownership of any one or more tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, Signoff, etc. and lead the team to achieve results. Your responsibilities will include completing assigned tasks successfully and on-time within the defined domain(s), anticipating, diagnosing, and resolving problems, coordinating with cross-functional teams as necessary, ensuring on-time quality...

Experience in Custom Layout design using tools such as Cadence Virtuoso, Synopsys Custom Compiler, or Mentor Pyxis. Knowledge of semiconductor devices, transistor-level design, & layout techniques for high-density memory cells. Calibre, Pegasus, ICV

Physical Verification Engineer Job Description Work with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification Coordinates with internal IP owners on IP related issues. Coordinates with Manufacturing Team on DRC related issues. Provide automation solutions to improve efficiency in tape-out flow. Report on tapeout issues. Custom Layout Requirement Bachelor/Masters Degree in Electrical/Electronics Engineering / Computer Science 6-10 years of physical verif...

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, including circuits, mechanical systems, and digital/analog/RF/optical systems. Your role will involve working on cutting-edge products, collaborating with cross-functional teams, and meeting performance requirements. The Qualcomm Noida CPU team is specifically looking for individuals to handle the hardening of complex HMs from RTL to GDS, including synthesis, PNR, and timing. - Develop high-performance and power-optimized custom CPU cores - Physical verification post BTECH / MTECH with at least 5 years of experience - Exper...

As an RF Mask Layout Designer/ Support Engineer based in San Diego, CA, you will be responsible for the physical design of RF and Analog circuits in a fast-paced environment. Your key responsibilities will include: - Providing accurate schedules - Meeting project milestone deadlines - Demonstrating full self-sufficiency in debugging complex verification failures - Fully understanding and utilizing the Cadence 6.1 and Calibre tools - Delivering high-quality layouts that conform to all design requirements - Demonstrating a full understanding of hierarchical planning (top-down and bottom-up) and integration Minimum qualifications for this role include: - Meeting all tape-out schedules - Ability...

As an Analog Layout Designer, you will be responsible for working independently on block level and chip level Analog layout design while collaborating with the circuit designer and project lead. Your role will require a minimum of 3+ years of hands-on experience in Analog layout, specifically in custom layout of DAC, ADC, Band gap, Regulators, LDOs, etc. Knowledge of finfet technology or exposure to 28nm or below will be considered an added advantage. It is essential to have a full understanding of IC fabrication and reliability issues. Proficiency in tools such as Cadence-Virtuoso, PVS, ASSURA, and Calibre is required. Strong written and verbal communication skills are necessary for effecti...

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be part of a highly experienced CPU physical design team, responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors. Your role will be crucial in a fast-paced environment with cutting-edge technology. Key Responsibilities: - Own critical CPU units and drive to convergence from RTL-to-GDSII, including synthesis, floor-planning, place and route, timing closure, and signoff. - Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoff...

Job Overview We are seeking a talented Analog Layout Engineer with 3- 5 years of experience in advanced semiconductor technologies (5nm and below). The ideal candidate will have hands-on expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre. This is a fantastic opportunity to work on cutting-edge analog and mixed-signal circuit layouts as part of a high-performance team. Key Responsibilities Execute full custom layout design for high-speed analog and mixed-signal blocks. Collaborate closely with circuit design teams to interpret and implement layout specifications. Perform layout verification, including DRC, LVS, and parasitic extraction ...

Position Summary Role and Responsibilities About Samsung Semiconductor India Research (SSIR) With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segmentsin component solutions, featuring industry-leading technologies inSystem LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions,AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPsand much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers...

Location: Hybrid Job Type: Full-Time Posted Date: 6/30/2025 About The Role Job Overview: We are seeking a Senior Physical Design Engineer with strong expertise in Netlist-to-GDSII implementation and experience working on advanced submicron technology nodes. The role demands in-depth knowledge of industry-standard EDA tools and a solid grasp of timing closure and physical verification processes. Key Responsibilities: ? Drive full Netlist-to-GDSII flow: floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. ? Perform Static Timing Analysis (STA) and ensure timing closure across all design corners. ? Execute power integrity and physical verification checks (LVS, DRC). ? Co...

Senior Physical Design Engineer Physical Design >> Senior Physical Design Engineer Post Senior Physical Design Engineer Required Experience 5 to 10 Years Location: Delhi NCR, Bangalore, Hyderabad Openings 8-10 Education BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) Physical Design Engineer knowledge of PD Flow from netlist to GDS (Floorplanning, Synthesis, Power Planning, Placement & Optimization, CTS, Routing, ECO steps, Timing/SI) Good idea about OCV/MMMC and multi power designs (Level shifters, Isolation cells etc) Should have worked extensively on XTalk/SI/EM Knowledge about CTS, Clock tree methodology and clock skewing. Tool specific knowledge: ICC, innovus, primetim...

The Opportunity We are looking for a detail-oriented and innovative Lithography Mask Designer with strong programming skills to support our semiconductor development processes. In this role, you will be responsible for the creation, optimization, and automation of lithography mask layouts, ensuring precision and efficiency in advanced manufacturing environments. How You'll Make An Impact You will design and generate lithography masks for semiconductor devices using industry-standard tools (e.g. Cadence, KLayout, Calibre), big plus would be knowledge of DW2000. You will collaborate with process engineers and product designers to translate device requirements into mask layouts. You will develo...

Skills requried: In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes. Should have experience in Analog and Mixed Signal Design Should have experience in handling >5M instance count , 1.5GHz frequency designs. Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency. Must have hands-on experience on PnR Suite from Cadence & Synopsys (Innovus & ICC2) Strong experience on Static T...

We're Hiring | Physical Verification Engineer Location: Chennai Experience: 4 to 6 Years Availability: Immediate joiners / Candidates serving notice period preferred Preferred Experience: Calibre tool expertise ACL Digital is looking for a skilled Physical Verification Engineer to join our dynamic team. If you have hands-on experience in physical verification and are proficient with tools like Calibre , we'd love to connect with you! Share your updated resume at: [HIDDEN TEXT]

Job Title : Physical Design Engineer Location State : Maharashtra Location City : Pune Experience Required : 5 to 10 Year(s) Shift: Day Shift Work Mode: Hybrid Position Type: Permanent Openings: 1 Company Name: VARITE INDIA PRIVATE LIMITED About The Client: VARITE is a global staffing and IT consulting company providing technical consulting and team augmentation services to Fortune 500 Companies in USA, UK, CANADA and INDIA. VARITE is currently a primary and direct vendor to the leading corporations in the verticals of Networking, Cloud Infrastructure, Hardware and Software, Digital Marketing and Media Solutions, Clinical Diagnostics, Utilities, Gaming and Entertainment, and Financial Servic...

Company Description Thalia is a venture-funded technology business with facilities in Cwmbran, United Kingdom; Hyderabad, India; and Cologne, Germany. The company provides analog and mixed signal design solutions for integrated circuit (IC) manufacturers and IP companies utilizing unique design automation technology and strong value-added services capabilities. With support from investors like Mercia Fund Management and Finance Wales, along with grants from Innovate UK and The Welsh Government, Thalia enables customers to migrate designs, generate portfolios, and develop faster IPs, achieving reduced design cycles, lower costs, and shorter time to market. Thalia has successfully delivered nu...

Hi All, Title : Analog Layout Engineer Exp Level:3+ yrs Location: Bangalore Job Description: Design and development of full custom analog/mixed-signal layout at block and top level. Strong expertise in analog layout techniques for circuits such as ADC, DAC, PLL, LDO, Bandgap, etc. Hands-on experience with layout tools like Cadence Virtuoso, Calibre, and Mentor tools. Ensure layout meets DRC, LVS, ERC, Antenna, and other physical verification requirements. Work closely with circuit design engineers to plan, review, and optimize layout. Experience in advanced process nodes (e.g., 7nm, 5nm, 3nm) preferred. Understanding of EMIR, ESD, and reliability requirements Proficient in hierarchical and f...

Role Overview: You will be responsible for independently executing mid-sized customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will own tasks related to RTL Design/Module and provide support and guidance to engineers in various areas such as Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. Your role will involve anticipating, diagnosing, and resolving problems while coordinating with cross-functional teams to ensure on-time quality delivery approved by the project manager and client. Additionally, you will be expected to automate design tasks flows, write scri...

You have 24 years of experience in ASIC Physical Design and Timing Analysis. Your hands-on expertise includes working with tools such as: - Physical Design: Innovus, ICC2, Fusion Compiler, or similar - STA: PrimeTime, Tempus - Physical Verification: Calibre, Pegasus Open positions available: - PD- 2-4 years (Chennai) - STA - Top level or Fullchip - 4+ years (Bangalore/Pune/Hyderabad) You should have an immediate to 30 days notice period.,