VLSI Lead

 Long Description 
1. ASIC RTL Engineer:RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - MandatoryPCIe/DDR/Ethernet - Any OneI2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any Onescripting languages like Make flow, Perl ,shell, python - Any OneLocationBangalore / Hyderabad / KochiExperience - 7+ - Lead/Architect2. Emulation LeadJD - Emulation Lead (Zebu/ HAPS /Veloce/Palladium and Module Build (End to End)Location - Bangalore / Hyderabad Experience - 7+ - Lead/Architect3. Lead Design Verification Engineer:7+ years of hands-on DV experience in SystemVerilog/UVM.Must be able to own and drive the verification of a block / subsystem or a SOC.Should have a track record of leading a team of engineers.Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM.Experience in Tesplan and Testbench development,Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time.Should be good with debugging and exposed to all aspects of verification flow including GatesimsMust have extensive experience in verification of one or more of the following:PCI Express or UCIe, CXL or NVMeAXI, ACE or CHIEthernet, RoCE or RDMADDR or LPDDR or HBMARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languagesPower Aware Simulations using UPFExperience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper.Experience in using one or more of revision control systems such asGit, Perforce, Clearcase.Experience in SVA and formal verification is desirable (not a must)Script development using Python, Perl or TCL is desirable (not a must)Location - Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, PuneExperience - 7+ YoE Long Description 
4. Analog Circuit Design:Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc.Experience - 7+ Yrs + Lead/ArchitectLocation - Bangalore5. DFT- ATPG, MBISTLocation - Bangalore, Kochi, Pune, HyderabadExperience - 7 years + DFT LeadMandatory Skills:

VLSI HVL Verification.
Experience5-8 Years.