12 Lpddr Jobs

Responsibilities: * Design, develop & verify complex SoCs using SV, UVM & LPDDR * Collaborate with cross-functional teams on RISC processor integration * Lead IP verification Interested professionals share your resume to mansoor@hisoltech.com

Hot Vacancy Design Verification Engineer (5–10 Years) Location: Bangalore Experience: 5 to 10 Years Industry: Semiconductors / VLSI / ASIC Employment Type: Full Time Joining: Immediate to 30 days preferred Job Description: We are actively hiring skilled and passionate Design Verification Engineers with 5–10 years of experience for multiple cutting-edge SoC/ASIC. Roles and Responsibilities: Develop test plans , testbenches , and testcases using System Verilog and UVM . Own block-level and/or SoC-level verification and drive coverage closure . Verify protocols and interfaces such as AXI, AHB, PCIe, LPDDR5, UCIe, I3C, CXL , etc. Perform assertion-based verification (SVA) and support gate-level simulations (GLS) . Collaborate with cross-functional teams including RTL. Desired Candidate Profile: 5–10 years of hands-on experience in ASIC/SoC functional verification . Strong in System Verilog, UVM . B.E./B.Tech or M.E./M.Tech in ECE/EEE/CSE or related fields. Why Join Us? Work on next-gen chip designs with global teams. Opportunity to work on latest protocols and IPs . Interested Candidates share your resumes to priya@maxvytech.com and hr@maxvytech.com

Key Responsibilities: Good understanding of verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. Experience and knowledge in Verification of IPs related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols. Verification for complex IPs and close the Verification to the challenging milestones. Strong knowledge of AXI4/AXI5 protocol Strong understanding of Coherency rules in ACE and ACE5 Experience with architecting BFMs/VIPs Should be able to handle a team of 3-4 engineers (for senior position). IP Verification: VR creation as per the chip requirements and UVM/OVM Test benches creation Support in building verification infrastructure at the chip level as per the requirements Capable of handling multiple areas of IP Verification: RTL, Power Aware and Gate Level Verification Strong in SV and UVM. PCIe Gen5 Tetsbench development experience is required. CXL2.0/3.0 protocol working experience will be added advantage Skills and Qualifications: Education: B.Tech/B.E. or M.Tech/M.S. in Electronics, Electrical Engineering, or a related field. Experience: 3-14 years of hands-on experience in ASIC design verification. Tools & Technologies: Proficiency in hardware description languages (Verilog, VHDL, System Verilog). Familiarity with UVM (Universal Verification Methodology) and other verification methodologies. Experience with simulation and debugging tools (ModelSim, VCS, Questa). Knowledge of scripting languages (Python, Tcl, Perl) for test automation. Experience with version control tools such as Git or SVN. Familiarity with formal verification tools and techniques is a plus. Desired Skills: Strong understanding of digital logic design, state machines, and timing analysis. Ability to work independently and collaboratively within a team environment. Strong problem-solving and analytical skills. Good communication skills to effectively report verification results and progress. Preferred Qualifications: Experience with high-level synthesis tools. Knowledge of low-power design techniques. Familiarity with performance verification and hardware-software co-verification.

We are seeking a highly skilled and motivated Firmware Software Development Engineer (Memory Management) to join the offshore development teams of our group companies You will work with the rapidly expanding team which focuses on the research and development of embedded products You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Bangalore, Belgrade, Penang, New York Desired Profile Engineers with expertise in firmware development related to memory recognition and configuration code Expertise in embedded C programming Expertise in using hardware debug tools Good problem solving, analysis and debugging skills Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM / SODIMM / RDIMM / LRDIMM / LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Understanding of different vendor implementations and memory timing difference is a big plus Knowledge of platform BIOS and UEFI / Coreboot is a big plus Scripting knowledge is a plus Rewards And Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process. NOTE : Preferred resources holding valid regional work permits only

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the Digital Low Power IPs for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle (including Functional, Low Power Verification, Gate Simulation, Formal Verification) from system-level concept to tape out and post-silicon support.Responsibilities:Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team.Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Low power verification, Formal verification and Gate level simulation to ensure high design quality.Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful IP level verification, integration into subsystem and SoC, and post-silicon validation.Minimum Qualifications:Master's/Bachelors degree in Electrical Engineering, Computer Engineering, or related field.8+ years ASIC design verification, or related work experience.Knowledge of a HVL methodology like SystemVerilog/UVM.Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others.Preferred Qualifications:Experience with Low power design verification, Formal verification and Gate level simulation.Knowledge of standard protocols such as Power Management Flows, PCIe, USB, MIPI, LPDDR, etc. will be a value addExperience in scripting languages (Python, or Perl). Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Applications Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Application Engineer, you will provide technical expertise of hardware through trainings, product demonstrations, and the design, debug, test, and quality support of customer products. Qualcomm Hardware Application Engineers collaborate with cross-functional teams to assess the potential application of company products that meet and exceed customer needs. Minimum Qualifications: "¢ Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, or related field and 2+ years of Hardware Applications Engineering or Hardware Design experience or related work experience. OR Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related field and 1+ year of Hardware Applications Engineering or Hardware Design experience or related work experience. OR PhD in Electrical/Electronics Engineering, Computer Engineering, or related field. IOT JD Title IOT Applications Engineering "“ Senior Engineer Job Function Qualcomm is seeking candidates to assist its customers in designing IoT solutions utilizing Qualcomm hardware and software. The individual will contribute to the dynamic Customer Engineering team for product designs and will be responsible for supporting Qualcomm's expanding portfolio of platforms and applications. This role involves collaborating closely Qualcomm customers to support hardware design sign-offs, system/PCB/chip-level debugging, and ownership of design collaterals that helps customers to bring out products faster. Preferred Qualifications A strong understanding of Digital/baseband HW design and PCB design is required. Good troubleshooting skills with the ability to analyze and debug during board bring up (boot-up) are essential. An understanding of LDO/SMPS is essential, along with experience in power management for portable devices being advantageous. Solid knowledge in High-Speed digital interfaces, such as memory Bus I/F (UFS, eMMC, LPDDR, NAND), Display interfaces (parallel and serial, preferably MIPI DSI), Camera interfaces (parallel and serial, preferably MIPI CSI), High Speed peripherals (USB, SDC, PCIe, Ethernet), and Standard Peripheral interfaces (UART, SPI, I2C, JTAG, HDMI) are necessary. Experience with Digital HW/baseband systems and board-level design, as well as familiarity with Digital ASICs and system design, is important. Understanding of system-level clocking schemes, interface-level handshakes are necessary A strong understanding of mobile and consumer electronics products is needed. Hands-on experience with oscilloscopes, logic analyzers, test and measurement tools are required. Basic knowledge of ARM processors and experience with JTAG emulators, display drivers, and memory is preferable. Knowledge of multi-core system/inter-chip system design is advantageous. A strong understanding of PCB signal/power integrity is necessary Must be comfortable in reviewing schematics and suggesting improvements is required. Experience with schematic entry is a plus. Must have knowledge to review PCB layout in various CAD tools like Cadence Allegro, Siemens Mentor Graphics suite. Knowledge of multi-layer PCB designs, vias, and stack-up configuration is essential. The ability to interact with multi-geography customers and stakeholders is desired. Knowledge of prototyping platforms like Arduino and Raspberry Pi is beneficial. About The Role As a member of Qualcomm's Customer Engineering team, responsibilities include creating chip and chipset documentation, reference schematics, and training materials for global customer support. Candidate will assist with hardware design reviews, respond to technical queries, and troubleshoot designs at the system, SoC, and PCB levels. A minimum of 3 years' relevant experience is required, along with skills in hardware, digital/high speed/power management, and Silicon validation. Keywords Board Design, Board bring up, UFS, LPDDR, NAND, eMMC, MIPI, USB, UART, SPI, I2C, Logic Analyzer, PADS, Allegro, LDO, SMPS, Clocks, Crystal, ARM processor, JTAG Educational Requirements RequiredBachelor's, Electronics and/or Electrical Engineering PreferredMaster's, Electronics and/or Electrical Engineering

Alternate Job Titles: Senior Staff Applications Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a highly skilled Applications Engineering, Sr Staff Engineer with a passion for high-speed protocols and a strong background in DDR solutions With over 8 years of experience in the field, you excel at providing technical support and guidance to global customers, ensuring the seamless integration and optimal performance of DDR Interface IP solutions Your expertise in DDR5, LPDDR5, and LPDDR5X protocols, combined with your proficiency in AMBA bus interfaces and ASIC design flow, makes you an invaluable asset to any team Your excellent communication skills and ability to work effectively with a diverse team of engineers worldwide set you apart as a leader in your field You thrive in dynamic environments, where your problem-solving abilities and technical acumen can make a significant impact on customer success and product innovation, What Youll Be Doing: Providing post-sales support for configuration, integration, simulation, and post-silicon bring-up of DDR PHY and Controller, as well as HBM IPs, Working with the latest DDR protocols, including DDR5, LPDDR5, and LPDDR5X, Collaborating with a global team of engineers to deliver expert product knowledge to Synopsys customers, Conducting detailed technical presentations on the configuration and integration of Synopsys DDR IPs, Creating collateral and authoring documentation to improve user experience, Making presentations to customers on Synopsys DDR offerings, The Impact You Will Have: Enhancing customer satisfaction by providing expert technical support and guidance, Ensuring the successful integration and deployment of Synopsys DDR solutions in customer projects, Contributing to the continuous improvement of Synopsys DDR IPs through customer feedback and collaboration, Driving innovation by working with the latest high-speed protocols and technologies, Strengthening Synopsys' reputation as a leader in DDR solutions and high-performance silicon IPs, Supporting the development of cutting-edge technology that powers the future of computing and connectivity, What Youll Need: Prior experience in high-speed protocols such as DDR, PCIe, or Ethernet, Experience with AMBA bus interfaces, including AXI, Knowledge of floor-planning, SI/PI, and backend engineering, Proficiency with UNIX and HDL (Verilog/VHDL), Strong understanding of ASIC design flow, Bachelor's or Master's degree in Electronics Engineering or a related field, with a focus on VLSI design, 8+ years of relevant experience, Who You Are: Excellent communicator with strong English skills, Detail-oriented and highly organized, Collaborative team player with a global mindset, Adaptable and able to thrive in dynamic environments, Proactive problem solver with a customer-focused approach, The Team Youll Be A Part Of: You will be part of a diverse and dynamic global team of engineers dedicated to providing technical support and expertise to Synopsys customers worldwide This team is focused on delivering high-quality DDR solutions and ensuring customer success through collaboration, innovation, and continuous improvement, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

The Opportunity Were looking for the Wavemakers of tomorrow. About the job The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrows future by accelerating the critical data communication at the heart of our digital world - from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. What Youll Do Will be responsible for verification of IP, Block, or Subsystem at Soc Level Generate appropriate documentation for verification Responsible for analyzing/debugging given blocks/tasks in verification Should be able to develop and own the verification environment, verification components developed You will report to Lead Engineer What Youll Need: 6+ years of experience with a Bachelors/ masters degree in the field of Electrical, Electronics, or computer engineering Should have a good understanding of verification flow, challenges, and requirements of functional verification Have worked on IP level or Block level or SoC level functional verification Experience with digital verification aspects such as constrained random verification, functional coverage, code coverage, assertions, methodology & philosophy Expert in System Verilog, Verilog, and OVM/UVM verification methodology Have working experience on AMBA interface protocols (AXI, AHB, APB) Knowledge of Verilog/System Verilog, digital simulation, and debugging is a must Hands-on experience on working one or more of the following protocols is a must - UART, I2C, SPI, QSPI, I3C, eMMC, CAN, Hands-on experience working with one or more of the following protocols is desired - PCIe, USB, DDR, LPDDR, GBE, SATA Experience with Perl, Python or similar scripting languages will be helpful Ability to adapt & learn, quickly and willingness to proactively take on responsibilities beyond the job description to accomplish team goals. We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Lead the bring-up and debugging of high-speed memory interfaces(LPDDR) on advanced SoCs Optimize memory interface timings and configurations across multiple DRAM types and vendors to achieve performance and reliability Conduct comprehensive validation, IO tuning, and PVT(Process, Voltage, Temperature) testing of memory subsystems to ensure compliance with design specifications and performance targets Work closely with pre-silicon design teams to understand new features, develop validation test plans, and ensure seamless integration. Interface with Design/Software and other teams for the debugs. Work with Customers & Application Engineers & RDs to understand emerging needs requirements and create product specifications Develop and validate low-level firmware for memory subsystems using C/C++ and participate in post-silicon testing to ensure functionality Validate new product features & ensure it meets the requirements and quality Compliance with design specifications and performance targets Identify, analyze, and resolve complex issues related to memory subsystems. Job Requirement: Bachelor's/Master's degree in Electrical/Electronics/Computer science Engineering. 2-5 years of experience in related domain Good communication, English speaking/writing and team work skills Bachelor's degree in Engineering, Computer Science, Electronics/Electrical Engineering or related field Logical thinking and problem-solving ability Very Good C/C++ Skills, Python or Perl skills good to have. In-depth understanding and hands-on experience with memory protocols such as DDR Understand the IP architecture , work with IP Design/Verification teams to understand the validation requirements, develop/port/enhance the validation software content and bring up. Familiarity with lab equipment(e.g., oscilloscopes, multimeters, logic analyzers) and understanding of PCB layout, high-speed board design, and signal integrity principles Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

About The Role : This role is within Intel's Client Computing Group. We are seeking an experienced Memory Validation and Debug Lead to join our post silicon validation team. In this role, you will lead memory subsystem ( DDR5 / LPDDR5) validation and debug efforts and ensure high-quality, reliable memory systems within our advanced silicon products. You will work closely with cross-functional teams, including design, MRC , EV (analog) verification, and validation teams, to enable higher memory speeds , validate new feature and identify , analyze and resolve memory issues. Your expertise will be essential in enhancing product quality, optimizing memory performance, and driving innovation. Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met. Reviews proposed design changes to assess impact on validation plans, tasks, and timelines. Develops SoC validation methodologies, validation test plans, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis. Performs silicon debug to identify root causes and resolves all functional and triage failures for SoC issues. Develops content to create or increase specific IP interactions using a variety of tools and techniques (including patching techniques using microcode, firmware, or custom OS builds). Engages in all phases of the product life cycle and develops and validates content, infrastructure, and bug hunts in multiple environments (e.g., simulation, emulation, FPGAs) to ensure silicon readiness. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: M.tech/ME with 7+ years of relevant industry experience hands on with pre or post silicon SOC validation. Key Skills:Memory sub-system validation, DDR5/LPDDR5, IP, debugging, architecture. Preferred Qualifications: Understanding of Intel system architecture and hands-on experience validating and debugging SoC issues.Requirements listed would be obtained through a industry relevant job experience Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Develop testbenches, testcases, and verification components using SystemVerilog and UVM. PCIe, Ethernet, AMBA protocols must. Create and execute detailed verification plans based on design specifications Drive coverage closure, and debug failures.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. The Power & Signal Integrity Group (PSIG) resides in the CHS (Central Hardware Systems) unit of Qualcomm Technologies, Inc., a leader in wireless communication technology. Engineers in the Power & Signal Integrity Group work with the various business units across Qualcomm to help bring leading edge mobile, AR\VR, IoT, Automotive and various others products to market. The candidate will work in a team-oriented environment with cross functional leads to provide electrical design expertise in the areas of signal integrity and power integrity for the design of wireless products and development systems. The engineer will be located in Bangalore, India and will be closely working with the Product architects, Platform HW teams, IO\PHY, IC Packaging, and other teams. The candidate is expected to perform SI / PI analyses and provide guidance on signal and power integrity challenges. Working effectively across organizational boundaries is essential as is the effective documentation and presentation of results. The candidate is expected to work closely with an experienced SI engineer while applying established PSIG methodologies. The engineer will have the opportunity to influence the evolution of analysis methodologies. Responsibilities Perform various IO analyses using established methodologies, potentially from model extraction through simulation and reporting of conclusions. IO types include DDR memory interfaces and variety of serial interfaces. Analyze and provide design guidance for DIE floor plans, IC packages, PCB power distribution networks using established methodologies. Document, distribute, and present results at appropriate meetings. 2+ years of work experience in the following areas: Electromagnetic theory and transmission lines Basic signal and power integrity concepts Commercial 3D electromagnetic field solver Commercial SI or RF simulation and analysis tools SPICE transient simulation including use of IBIS models The following experience is a plus: DDR and LPDDR design and analysis High speed serial IO design and analysis, PCIE, USB, UFS, CSI/DSI/MIPI Power Integrity analysis SI/PI tools :Ansys HFSS/SIwave, Cadence/Sigrity, Keysight ADS, HSPICE Spreadsheets and similar productivity tools Mentor or Cadence board design tools Education Requirements: Minimum Bachelor degree in Electrical Engineering or related discipline, Master degree preferred