32 Lpddr Jobs

As a Senior Engineer, Analog Design at Micron Technology, your primary responsibilities will involve designing, implementing, and enhancing Complex Analog Circuits in advanced semiconductor process nodes for cutting-edge DRAM products. This includes the development of CMOS Amplifiers, Comparators, IO circuits (DDR/LPDDR) - Tx & Rx, DFE, CTLE, along with integrating modules with Power delivery network and proposing design solutions for optimal performance. You will be tasked with validating and optimizing designs for reliability, conducting Clock & Datapath design, performing EM/IR simulation, optimizing layout for enhanced circuit performance, as well as engaging in custom digital circuit design & validation. Additionally, you will be involved in parasitic modeling, assisting in design validation, reticle experiments, and necessary tape-out revisions. As part of your role, you will oversee and manage the layout process, including floor-planning, placement, and routing, while also conducting verification processes using industry-standard simulators. Collaboration will be key, as you will work across various groups such as Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering to ensure accurate manufacturability of products. Furthermore, you will play a crucial role in driving innovation for future Memory generations within a dynamic work environment. Your contributions will be vital in advancing technology and pushing boundaries to meet the evolving needs of the industry. Micron Technology, Inc. is a global leader in innovative memory and storage solutions, committed to transforming the way information is utilized to enhance life for all. With a strong focus on technology leadership, operational excellence, and customer satisfaction, Micron delivers a diverse range of high-performance DRAM, NAND, and NOR memory and storage products under the Micron and Crucial brands. If you are passionate about being part of a team that drives the data economy forward, enabling advancements in artificial intelligence and 5G applications from data centers to the intelligent edge and beyond, Micron is the place for you. Join us in shaping the future of technology and exploring new opportunities in the ever-evolving tech landscape. For more information about career opportunities at Micron, please visit micron.com/careers. For any assistance with the application process or to request reasonable accommodations, please reach out to hrsupport_in@micron.com. Micron upholds a strict policy against the use of child labor and adheres to all relevant laws, regulations, and international labor standards.,

As a Staff Engineer - Design Verification at Micron Technology, you will be part of a highly innovative and motivated design team working on cutting-edge memory technologies to develop advanced DRAM and Emerging memory products. Your role will involve verifying high density memory chips with complex circuit capabilities, ultra-high-speed designs, and next-generation DDR/LPDDR technologies. You will collaborate with various design and verification teams globally to ensure the successful completion of design projects. Your responsibilities will include: - Taking ownership of verification and conducting end-to-end analysis of complex block-level custom designs for DDR4, LPDDR4, DDR5, and LPDDR5 memory architectures operating at high speeds. - Guiding and directing the verification effort for all projects undertaken by the team. - Providing verification support by simulating, analyzing, and debugging pre-silicon block level/full chip designs. - Developing test cases and stimulus to enhance functional coverage for DRAM and emerging memory products. - Creating and maintaining test benches and test vectors using simulation tools, running regressions for coverage analysis, and collaborating with international colleagues to develop new verification flows. - Contributing to the development of verification methodologies and environments for advanced DRAM and emerging memory products. - Demonstrating a good understanding of digital/mixed-signal circuits and experience in digital/mixed-signal verification. - Utilizing tools like Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, and Hspice. - Writing Verilog and Real Number Models, as well as building SV testbenches at block and full-chip levels. - Implementing SV and UVM-based verification, with proficiency in scripting using Perl and Python. - Having previous experience in DRAM memory-related fields is advantageous, along with possessing strong communication, debugging skills, and the ability to work effectively in a team. To qualify for this role, you must hold a Bachelor's or Post Graduate Degree in Electronics Engineering or a related field, with 5-15 years of relevant experience. Micron Technology, Inc. is a global leader in memory and storage solutions, driving innovations that enhance the way information is used to enrich life for all. With a focus on customer satisfaction, technology leadership, and operational excellence, Micron offers a range of high-performance DRAM, NAND, and NOR memory and storage products through its Micron and Crucial brands. The advancements made by Micron's team members contribute to the data economy, enabling progress in artificial intelligence and 5G applications across various platforms. For more information, please visit micron.com/careers. If you require assistance during the application process or need accommodations, please contact hrsupport_in@micron.com. Micron Technology strictly prohibits the use of child labor and complies with all relevant laws, regulations, and international labor standards.,

As an FPGA Design and Verification/Validation Engineer at Dexcel Electronics in Bengaluru or Hyderabad, you will be responsible for independently overseeing FPGA Design Blocks. You should have a minimum of 2 years of experience in RTL Design, 2 years in IP Verification, 4 years in IP Design/SOC Design, and 6 years in FPGA Design. Your primary task will involve working with various Interfaces such as PCIe 2.0, SATA, Fiber Channel, 1G/10G BASE, MII/RMII/GMII/RGMII/SGMII/XAUI, RXAUI, SDI- SD/HD/3G, Display Port, USB, JESD204B, SRIO, MIPI, DDR/LPDDR/DDR2/DDR3, and QDR memories. Additionally, hands-on experience in Design and Debugging is preferred. You should have prior experience working on projects based on FPGAs and SOC, with a solid understanding of SOC and Hi-Speed Interfaces domain knowledge. At Dexcel Electronics, we are seeking highly motivated individuals who are eager to learn and develop in a dynamic environment. If you are passionate about technology and seeking exciting career opportunities, we invite you to join our team. For more information on current job openings, please visit our website or email your updated resume to careers@dexceldesigns.com.,

You will be responsible for designing and leading the development of high-speed IP such as GDDR7, DDR5, and LPDDR6. As a strong individual contributor in the analog domain, you will actively participate in all aspects of development including analog design, layout, digital design, documentation, and silicon validation. Your role will also involve engaging in customer-facing discussions to address their requirements and concerns. To qualify for this position, you should hold a B.Tech / BE / ME / Mtech degree with at least 5 to 15+ years of experience. It is essential to have hands-on design experience and leadership skills in GDDR/DDR/LPDDR IPs. A successful candidate must have been involved in the entire cycle of analog IP creation, from specification to silicon debugging and characterization. Good communication skills and the ability to work effectively in a team are crucial for this role. Moreover, expertise in areas such as PLL, high-speed circuits like TX, RX, clocking circuits, etc., is mandatory. Experience with other common IP blocks like BGR, LDO, POC, temperature sensor, etc., would be considered advantageous.,

We are seeking a highly skilled and experienced Lead Verification Engineer with expertise in USB/LPDDR and a strong knowledge of Cadence VIP. The ideal candidate will have a deep understanding of low-power design and verification techniques. Responsibilities: Develop and execute comprehensive verification strategies for USB/LPDDR subsystem designs, considering low-power design requirements. Collaborate with cross-functional teams to define verification goals and ensure alignment with project objectives. Design and implement reusable, scalable, and efficient verification testbenches using SystemVerilog/UVM or C based . Leverage Cadence VIP and other verification IPs to accelerate the verification process. Low-Power Design VerificationApply expertise in low-power design and verification techniques to ensure accurate and reliable verification of power management features, including power states, power domains, and power-aware verification methodologies. : Extensive experience (8+ years) in verification. Strong knowledge of Cadence VIP and verification methodologies (SystemVerilog/UVM). Proficiency in low-power design techniques and power-aware verification methodologies. Hands-on experience with industry-standard simulation and verification tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Questa). Solid understanding of verification languages (SystemVerilog, VHDL) and scripting languages (Perl, Python, TCL). Familiarity with industry standards and protocols related to USB (USB 2.0, USB 3.x) and LPDDR (LPDDR4, LPDDR5). Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

DDR and LPDDR design and analysis High speed serial IO design and analysis, PCIE, USB, UFS, CSI/DSI/MIPI Power Integrity analysis SI/PI tools: Ansys HFSS/SIwave, Cadence/Sigrity, Keysight ADS, HSPICE Spreadsheets and similar productivity tools Mentor or Cadence board design tools

At Cadence, we are looking for individuals who are passionate about technology and aspire to lead and innovate in the industry. Your responsibilities will include understanding and reviewing design specifications, developing verification strategies, test plans, and coverage plans. Additionally, you will be tasked with creating constrained random verification environments, verification components, writing tests, sequences, functional coverage, and assertions to achieve verification goals. Furthermore, you will be developing C-based test cases for SOC verification. To excel in this role, you should have a strong background in functional verification fundamentals, environment planning, test plan generation, and environment development. Proficiency in System Verilog and experience with UVM based functional verification environment development are required. Knowledge of verilog, vhdl, C, C++, Perl, and Python is essential. Expertise in AMBA protocols such as AXI, AHB, and APB is a must, along with familiarity with USB, PCIE, Ethernet, DDR, LPDDR, or similar protocols. Proficiency in version control and load sharing software is also necessary. Desirable skills and experience include prior experience with Cadence tools and flows, familiarity with ARM/CPU architectures, experience in developing C-based test cases for SOC verification, some exposure to assembly language programming, and knowledge of protocols like UART, I2C, SPI, and JTAG. Embedded C code development and debug, as well as formal verification experience, would be advantageous. Strong communication, organizational, planning, and presentation skills are crucial for success in this role. You should be able to work independently, deliver high-quality results in a fast-paced environment, and be open to learning new methodologies, languages, and protocols. Personal development and growth are essential to meet the evolving demands of the semiconductor industry. A self-motivated mindset and willingness to take on additional responsibilities to contribute to the team's success are highly valued. Join us at Cadence, where we tackle challenges that others cannot. Let's make a difference together.,

As a Senior Engineer, Signal Integrity at Micron Technology, you will be part of the inclusive culture that drives the innovation of memory and storage solutions. Your role within the Signal Integrity Research and Development (SI R&D) group will involve supporting various product developments, including DRAM, LPDRAM, NAND, CXL, LPCAMM, DIMM modules, and SSDs across different business sectors. Your responsibilities will include analysis of end-to-end systems solutions, circuit level IO and Power Distribution, integrated circuit packages, printed circuit boards, and measurements to ensure optimal Signal Integrity (SI) and power integrity (PI) performance for Micron's memory solutions. Working within the Signal Integrity team, you will be tasked with various aspects of SI and PI for high-speed interfaces, including modeling at silicon, package, and board levels, time and frequency domain analysis, electrical performance evaluation, and correlation to measurements for different products. You will collaborate with global teams for the development and optimization of methodologies, represent the SI R&D team in cross-functional groups, and integrate with various departments to ensure overall product performance. Successful candidates for this position will possess a Bachelor's or Master's degree in Electrical/Electronics Engineering with 4-8 years of experience. You should have a strong background in SI/PI/EMI theory and application, modeling, analysis, simulation, and a deep understanding of electromagnetic and transmission line theory. Experience with E.M. field solvers, simulation tools, and lab equipment is required. Additionally, familiarity with statistical analysis tools and experience in high-speed interface design and analysis are beneficial. The ideal candidate will be proactive in identifying gaps and opportunities, collaborate effectively with global teams and customers, and communicate complex issues and solutions clearly in both written and verbal formats. If you are ambitious, possess strong problem-solving skills, and enjoy taking ownership of projects, this role at Micron Technology may be the perfect fit for you. Micron Technology, Inc. is a leading industry player in memory and storage solutions, committed to transforming how information enriches life for all. With a focus on technology leadership and operational excellence, Micron delivers high-performance DRAM, NAND, and NOR memory and storage products that power innovations in artificial intelligence and 5G applications. For more information about Micron Technology and potential career opportunities, please visit micron.com/careers. If you require assistance during the application process or need reasonable accommodations, please contact hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and adheres to all applicable labor laws and standards.,

Qualcomm India Private Limited is seeking talented Software developers to join the team, lead, and contribute towards the development of software tools. In this role, you will collaborate with cross-functional teams to ensure that the tools meet the highest standards of quality and performance. Your responsibilities will include designing, developing, and maintaining software tools and frameworks that enable customers to efficiently integrate and test chipsets across various design stages, from early development to factory testing. This is an excellent opportunity to work with cutting-edge technology and collaborate with cross-functional teams to drive customer success. The minimum qualifications for this role include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 6+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 5+ years of experience or a PhD with 4+ years of experience is also acceptable. As a System HW Applications Engineering Engineer, Sr Staff/Manager at Qualcomm, you will be responsible for supporting customers in designing solutions using Qualcomm hardware and software. You will contribute to the dynamic Applications engineering team for end product designs in Consumer, Industrial, and IoT applications. Your role will involve successfully integrating Qualcomm solutions into customer end products across various markets such as Mobile, Compute, 5G Broadband, Automotive, IoT, and consumer electronics. Key responsibilities include gathering, integrating, and interpreting information from cross-functional teams to troubleshoot issues and find solutions. You will apply your deep and broad knowledge to anticipate and identify gaps/risks in processes, technical aspects, and close these gaps by working with a wide range of eco-system partners within Qualcomm. Additionally, you will act as a tech lead on projects, collaborate with internal partners, define product requirements, support customers on HW design signoffs, system/SoC debug, and manage a cross-functional team of engineers. Preferred qualifications for this role include expertise in embedded systems HW/SW design, board bring up, Silicon bench tests, measurements of AC/DC parameters, SOC interface parametric measurements, and basic SW integrated functional tests. Proficiency in programming languages such as C, PERL, and PYTHON is preferred. Experience with High-Speed Digital interfaces, Power management areas, ARM processors, and JTAG emulators is highly desirable. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com or call Qualcomm's toll-free number. Please note that Qualcomm expects its employees to abide by all applicable policies and procedures, including those related to the protection of confidential information. If you are an individual seeking a job at Qualcomm, please refrain from using the Careers Site for staffing and recruiting purposes. Qualcomm does not accept unsolicited resumes or applications from agencies. For more information about this role, please contact Qualcomm Careers.,

We are seeking experienced Senior/Lead ASIC Verification Engineers to join our Noida-VIP team. With 5 to 15 years of experience in Verification, particularly using industry-standard protocols and methodologies, this role offers a challenging opportunity for individuals well-versed in System Verilog, Verilog, and Object-Oriented Programming. As a successful candidate, you will have demonstrated your ability to lead the development of reusable Verification environments on at least 2 projects using VMM, OVM, or UVM methodologies. Your expertise should extend to protocols such as UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory. Your responsibilities will include contributing to the development of the VIP, reviewing and signing off on VIP development and updates, and collaborating with Architects and methodology experts to address issues and drive architectural and methodological perspectives. If you are a proactive and reliable professional with a passion for Verification, we invite you to share your updated CV with us at taufiq@synopsys.com. Feel free to refer anyone who may be interested in this exciting opportunity as well. At Synopsys, we value Inclusion and Diversity, considering all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability. Join us in shaping the future of technology.,

Project description This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. Responsibilities Drive the development of cutting-edge memory-related firmware projects, contributing to the creation of innovative solutions Collaborate with a highly regarded team to bring innovation to memory-related firmware, ensuring solutions are at the forefront of industry advancements Tackle complex challenges by employing strong problem-solving skills, enhancing firmware to meet evolving performance and reliability standards Skills Must have 5-12 years' experience. Strong with C language programming Working knowledge of git/gerrit Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Nice to have Understanding different vendor implementations and memory timing differences is a big plus

3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / subsystem or a SOC. Should have a track record of leading a team of engineers. Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Experience in Tesplan and Testbench development, Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. Should be good with debugging and exposed to all aspects of verification flow including Gatesims Must have extensive experience in verification of one or more of the following: PCI Express or UCIe, CXL or NVMe AXI, ACE or CHI Ethernet, RoCE or RDMA DDR or LPDDR or HBM ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages Power Aware Simulations using UPF Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper. Experience in using one or more of revision control systems such asGit, Perforce, Clearcase. Experience in SVA and formal verification is desirable (not a must) Script development using Python, Perl or TCL is desirable (not a must) Location - Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, Pune Experience - 7+ YoE Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from design, selection of materials, low level system software development and verification. Needs by displaying complete understanding of product vision and business requirements Develop architectural designs for the new and existing products Part Implementation of derived solution Debug and Solve critical problems during implementation Evangelize Architecture to the Project and Customer teams to achieve the final solution. Constant analysis and monitoring of the product solution Continuously improve and simplify the design, optimize cost and performance Understand market- driven business needs and objectives; technology trends and requirements to define architecture requirements and strategy Create a product-wide architectural design that ensures systems are scalable, reliable, and compatible with different deployment options Develop theme-based Proof of Concepts (POCs) in order to demonstrate the feasibility of the product idea and realise it as a viable one Analyse, propose and implement the core technology strategy for product development Conduct impact analyses of changes and new requirements on the product development effort Provide solutioning of RFPs received from clients and ensure overall product design assurance as per business needs Collaborate with sales, development, consulting teams to reconcile solutions to architecture Analyse technology environment, enterprise specifics, client requirements to set a product solution design framework/ architecture Provide technical leadership to the design, development and implementation of custom solutions through thoughtful use of modern technology Define and understand current state product features and identify improvements, options & tradeoffs to define target state solutions Clearly articulate, document and sell architectural targets, recommendations and reusable patterns and accordingly propose investment roadmaps Validate the solution/ prototype from technology, cost structure and customer differentiation point of view Identify problem areas and perform root cause analysis of architectural design and solutions and provide relevant solutions to the problem Tracks industry and application trends and relates these to planning current and future IT needs Provides technical and strategic input during the product deployment and deployment Support Delivery team during the product deployment process and resolve complex issues Collaborate with delivery team to develop a product validation and performance testing plan as per the business requirements and specifications. Identifies implementation risks and potential impacts. Maintain product roadmap and provide timely inputs for product upgrades as per the market needs Competency Building and Branding Ensure completion of necessary trainings and certifications Develop Proof of Concepts (POCs), case studies, demos etc. for new growth areas based on market and customer research Develop and present a point of view of Wipro on product design and architect by writing white papers, blogs etc. Attain market referencsability and recognition through highest analyst rankings, client testimonials and partner credits Be the voice of Wipros Thought Leadership by speaking in forums (internal and external) Mentor developers, designers and Junior architects for their further career development and enhancement Contribute to the architecture practice by conducting selection interviews etc Deliver No.Performance ParameterMeasure1.Product design, engineering and implementationCSAT, quality of design/ architecture, FTR, delivery as per cost, quality and timeline, POC review and standards2.Capability development% trainings and certifications completed, mentor technical teams, Thought leadership content developed (white papers, Wipro PoVs) Applications from people with disabilities are explicitly welcome.

Project description This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. Responsibilities Drive the development of cutting-edge memory-related firmware projects, contributing to the creation of innovative solutions Collaborate with a highly regarded team to bring innovation to memory-related firmware, ensuring solutions are at the forefront of industry advancements Tackle complex challenges by employing strong problem-solving skills, enhancing firmware to meet evolving performance and reliability standards SkillsMust have 7-10 years' experience. Strong with C language programming Working knowledge of git/gerrit Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Nice to have Understanding different vendor implementations and memory timing differences is a big plus

About the Role This leadership position is pivotal within a global digital data business, contributing to the development of next-generation connectors, cable assemblies, and radio system components. Youll steer a specialized engineering team focused on Signal Integrity, guiding end-to-end product lifecycle activitiesfrom concept to high-volume manufacturing qualificationthrough rigorous design, simulation, and testing. This is more than managementit's strategic direction in a fast-evolving tech space where innovation and precision meet performance. Click to Apply - (https://forms.gle/fqb29wUvjNuV82C57) Responsibilities Strategic Leadership: Lead a globally distributed team of experienced SI engineers. Align design activities with organizational goals, customer expectations, and technical standards. Create and manage work plans, project schedules, budgets, and resource allocation. Technical Oversight: Define signal integrity performance parameters for innovative products. Guide complex simulations for multiple protocols: PCIe, USB, Ethernet, etc. Oversee connector design reviews using electromagnetic simulation tools and test validation data. Ensure adherence to qualification processes for high-speed connector interfaces and cable assemblies. Innovation & Execution: Integrate market trends and customer needs into technical roadmaps. Advocate a data-driven design culture through structured simulation reviews and continuous improvement. Lead advanced packaging and PCB layout exploration to support emerging high-speed protocols. Team Development: Build a cohesive, skilled team through talent assessments, structured onboarding, and continuous upskilling. Foster collaboration across geographies and functional disciplines (mechanical, process, materials, product). Provide clear coaching, feedback, and career development plans. Balance workloads and promote wellbeing through flexible, effective leadership. Key Technologies & Tools Signal Integrity Tools: Agilent ADS, Ansys HFSS, CST CAD Platforms: SpaceClaim, AutoCAD, Creo PCB Design: Altium, layout/fabrication validation Test Equipment: VNA, TDR, BERT Data Analysis: Statistical interpretation, tolerance modeling Simulation Interpretation: Channel modeling, S-parameter validation Ideal Candidate Profile 10+ years in electrical or RF design with progressive experience 3+ years of people management and cross-functional leadership Strong grasp of physical layer system architecture and packaging interfaces Skilled communicator able to present to technical and executive audiences Experienced in high-volume manufacturing qualification and risk analysis Proven success building high-performance teams with global collaboration

Role & responsibilities Test bench development and debug UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based testing. Coverage analysis (code, functional, assertion) Verification plan reviews, Verification reviews Back-annotated netlist simulation execution and debug Debug failing cases & Coverage improvements.

Looking for PCB layout design Engineers with the following requirements: Hands-on experience in complex, high-density, high-speed PCBs, Analog, Digital, RF, mixed-signal PCB layout design. Hands-on experience with High-speed interfaces like DDR3,DDR4, LPDDR, , PROCESSORS, FPGA, PCIE, USB, SATA, MIL-1553, ADC, DAC, ETHERNET, NAND & NOR FLASH, SD, RS-422, BLUETOOTH 4.0, WIFI, GPS, GSM etc. Hands on Complex layout HDI designs with multiple BGAs and Multiple Fine pitch BGA (0.8mm and 0.5mm) of high pin count (2084 pins). Library creation as per IPC 7351 standard. Electrical Constrains setup for high-speed modules to match its requirement (Length match, impedance, delay tuning requirements) Experience in Power supply layout design types: AC to DC, DC to DC converters and SMPS. Creation of file type conversions from PCB to DXF, IDF, Step file Power supply layout designs & its critical requirements to meet stringent isolations. Gerber validation and generations of final deliverables for DFM. Working experience on Gerber viewers using Cam350, ODB++ viewer. Collaborating with multiple functional teams like design, SI/PI, mechanical, DFM, DFA etc. in a product development environment knowledge on Power dc, Thermal design, simulation and analysis knowledge of OrCAD schematic Design Tool Collaboration with cross functional teams: Software, Electrical, Mechanical and PCB CAD teams Hands-on experience with Cadence Allegro/Altium EDA/PADS tools is essential. Educational Qualification: B Tech/M. tech/BE/ME, Diploma Location: Hyderabad Shift: General Exp.: 4-6 Years Work Week: Monday to Friday

Looking for PCB layout design Engineer with the following requirements: Hands-on experience in complex, high-density, high-speed PCBs, Analog, Digital, RF, mixed-signal PCB layout design. Exposure with complex 2U, 3U server form factor-based PCB designs. Hands-on experience with High-speed interfaces like DDR3,DDR4/5, LPDDR, , PROCESSORS, FPGA, PCIE, USB, SATA, MIL-1553, ADC, DAC, ETHERNET, NAND & NOR FLASH, SD, RS-422, BLUETOOTH 4.0, WIFI, GPS, GSM etc. Hands on Complex layout HDI designs with multiple BGAs and Multiple Fine pitch BGA (0.8mm and 0.5mm) of high pin count (2084 pins). Library creation as per IPC 7351 standard. Electrical Constraints setup for high-speed modules to match its requirement (Length match, impedance, delay tuning requirements) Experience in Power supply layout design types: AC to DC, DC to DC converters and SMPS. Creation of file type conversions from PCB to DXF, IDF, Step file collaboration with Mechanical Engineer. Power supply layout designs & its critical requirements to meet stringent isolations. Gerber validation and generations of final deliverables for DFM. Working experience on Gerber viewers using Cam350, ODB++ viewer. Collaborating with multiple functional teams like design, SI/PI, mechanical, DFM, DFA etc. in a product development environment knowledge on Power dc, Thermal design, simulation and analysis knowledge of OrCAD schematic Design Tool Collaboration with cross functional teams: Software, Electrical, Mechanical and PCB CAD teams Hands-on experience with Cadence Allegro/Altium EDA/PADS tools is essential. Education Requirements: B. Tech/B.E./M. Tech./M.E. Shift: 9:30 AM to 6:30 PM Work Mode: Office (Monday to Friday)

Job Role Overview: The ideal candidate for this role will be an innovative self-starter. You will be a DDR/LPDDR expert with experience in making architectural trade-offs to optimize DDR/LPDDR performance & power for a variety of use cases. You will collaborate with internal and external development engineers (architecture, hardware, validation, software services). You will be a member of a team analysing the product-level system power & performance for DDR/LPDDR. You will contribute to development, support device characterization, and benchmarking efforts. Job Description : Extensive experience in DDR/LPDDR systems Experience in development, preferably for DDR/LPDDR memory controller. In-depth knowledge and extensive experience with JEDEC specifications for DDR/LPDDR. In-depth knowledge and extensive experience in embedded domain. Requirements: B. Tech in Computer Science, Electrical Engineering. 8+ years of experience in a relevant domain. Strong analytical & abstract thinking ability, along with technical communication skills. Able to work independently and perform in a fast-paced environment. Ability to troubleshoot and debug complex issues. Prior experience in working with Agile/Scrum.

"We're Hiring For Lead Hardware Engineer role at Chennai Location" Position: Lead Hardware Engineer Experience: 15+ Years Location: Chennai Key Responsibilities: Independently lead electrical hardware design tasks for automotive systems. Review and analyze customer specifications and translate them into design requirements. Design and develop automotive electronics including: Microcontrollers, SoCs, high-speed memory interfaces LVDS and FPD-Link III circuitry High-speed digital and analog circuits Audio, camera, and video signal processing Linear and switching power supplies Perform worst-case analysis and circuit simulations to ensure compliance with specifications. Conduct and support formal design reviews and customer presentations. Create and maintain schematics, BOMs, and assembly drawings under change control processes. Develop and maintain DFMEA documentation for electrical systems. Collaborate with ECAD engineers for PCB layout and provide design support. Support prototype hardware builds and validate product performance. Develop test plans and perform electrical verification testing. Support EMC compliance and validation testing processes. Use structured problem-solving techniques to resolve design and testing issues. Operate lab instruments such as oscilloscopes, power supplies, function generators, and multimeters for design verification and debugging. More information +91 73597 10155 | rushit@tekpillar.com

"We're Hiring For Lead Hardware Engineer role at Chennai Location" Position: Lead Hardware Engineer Experience: 5+ Years Location: Chennai Key Responsibilities: Independently lead electrical hardware design tasks for automotive systems. Review and analyze customer specifications and translate them into design requirements. Design and develop automotive electronics including: Microcontrollers, SoCs, high-speed memory interfaces LVDS and FPD-Link III circuitry High-speed digital and analog circuits Audio, camera, and video signal processing Linear and switching power supplies Perform worst-case analysis and circuit simulations to ensure compliance with specifications. Conduct and support formal design reviews and customer presentations. Create and maintain schematics, BOMs, and assembly drawings under change control processes. Develop and maintain DFMEA documentation for electrical systems. Collaborate with ECAD engineers for PCB layout and provide design support. Support prototype hardware builds and validate product performance. Develop test plans and perform electrical verification testing. Support EMC compliance and validation testing processes. Use structured problem-solving techniques to resolve design and testing issues. Operate lab instruments such as oscilloscopes, power supplies, function generators, and multimeters for design verification and debugging. More information +91 73597 10155 | rushit@tekpillar.com

Long Description 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 2. Emulation Lead JD - Emulation Lead (Zebu/ HAPS /Veloce/Palladium and Module Build (End to End) Location - Bangalore / Hyderabad Experience - 7+ - Lead/Architect 3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / subsystem or a SOC. Should have a track record of leading a team of engineers. Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Experience in Tesplan and Testbench development, Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. Should be good with debugging and exposed to all aspects of verification flow including Gatesims Must have extensive experience in verification of one or more of the following: PCI Express or UCIe, CXL or NVMe AXI, ACE or CHI Ethernet, RoCE or RDMA DDR or LPDDR or HBM ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages Power Aware Simulations using UPF Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper. Experience in using one or more of revision control systems such asGit, Perforce, Clearcase. Experience in SVA and formal verification is desirable (not a must) Script development using Python, Perl or TCL is desirable (not a must) Location - Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, Pune Experience - 7+ YoE Long Description 4. Analog Circuit Design : Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc. Experience - 7+ Yrs + Lead/Architect Location - Bangalore 5. DFT - ATPG, MBIST Location - Bangalore, Kochi, Pune, Hyderabad Experience - 7 years + DFT Lead Mandatory Skills: VLSI HVL Verification. Experience5-8 Years.

Skillset: DV | System Verilog | UVM | Protocol Expertise Must-Have Skills: Strong expertise in System Verilog (SV) and UVM Proven experience in Test Bench Development Deep protocol knowledge in at least one of the following: PCIe / UCIe / CXL / NVM AXI / ACE / CHI Ethernet / RoCE / RDMA DDR / LPDDR / HBM Key Responsibilities : Lead and drive verification for block, subsystem, or SoC level designs Strong experience in IP/subsystem/SoC verification using SV/UVM Verification experience with ARM or RISC-V CPU based subsystems Work with C/Assembly for low-level testing Perform Power Aware Simulations using UPF Location : Bangalore | Hyderabad | Cochin | Pune

Responsibilities: * Design, develop & verify complex SoCs using SV, UVM & LPDDR * Collaborate with cross-functional teams on RISC processor integration * Lead IP verification Interested professionals share your resume to mansoor@hisoltech.com

Hot Vacancy Design Verification Engineer (5–10 Years) Location: Bangalore Experience: 5 to 10 Years Industry: Semiconductors / VLSI / ASIC Employment Type: Full Time Joining: Immediate to 30 days preferred Job Description: We are actively hiring skilled and passionate Design Verification Engineers with 5–10 years of experience for multiple cutting-edge SoC/ASIC. Roles and Responsibilities: Develop test plans , testbenches , and testcases using System Verilog and UVM . Own block-level and/or SoC-level verification and drive coverage closure . Verify protocols and interfaces such as AXI, AHB, PCIe, LPDDR5, UCIe, I3C, CXL , etc. Perform assertion-based verification (SVA) and support gate-level simulations (GLS) . Collaborate with cross-functional teams including RTL. Desired Candidate Profile: 5–10 years of hands-on experience in ASIC/SoC functional verification . Strong in System Verilog, UVM . B.E./B.Tech or M.E./M.Tech in ECE/EEE/CSE or related fields. Why Join Us? Work on next-gen chip designs with global teams. Opportunity to work on latest protocols and IPs . Interested Candidates share your resumes to priya@maxvytech.com and hr@maxvytech.com

Key Responsibilities: Good understanding of verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. Experience and knowledge in Verification of IPs related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols. Verification for complex IPs and close the Verification to the challenging milestones. Strong knowledge of AXI4/AXI5 protocol Strong understanding of Coherency rules in ACE and ACE5 Experience with architecting BFMs/VIPs Should be able to handle a team of 3-4 engineers (for senior position). IP Verification: VR creation as per the chip requirements and UVM/OVM Test benches creation Support in building verification infrastructure at the chip level as per the requirements Capable of handling multiple areas of IP Verification: RTL, Power Aware and Gate Level Verification Strong in SV and UVM. PCIe Gen5 Tetsbench development experience is required. CXL2.0/3.0 protocol working experience will be added advantage Skills and Qualifications: Education: B.Tech/B.E. or M.Tech/M.S. in Electronics, Electrical Engineering, or a related field. Experience: 3-14 years of hands-on experience in ASIC design verification. Tools & Technologies: Proficiency in hardware description languages (Verilog, VHDL, System Verilog). Familiarity with UVM (Universal Verification Methodology) and other verification methodologies. Experience with simulation and debugging tools (ModelSim, VCS, Questa). Knowledge of scripting languages (Python, Tcl, Perl) for test automation. Experience with version control tools such as Git or SVN. Familiarity with formal verification tools and techniques is a plus. Desired Skills: Strong understanding of digital logic design, state machines, and timing analysis. Ability to work independently and collaboratively within a team environment. Strong problem-solving and analytical skills. Good communication skills to effectively report verification results and progress. Preferred Qualifications: Experience with high-level synthesis tools. Knowledge of low-power design techniques. Familiarity with performance verification and hardware-software co-verification.