Verification Engineer || VLSI

Acesoft Labs

4 - 9 years

15 - 30 Lacs

hyderabad

Posted:23 hours ago| Platform:

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Skills Required

memory verification static timing analysis verification engineer dram memory circuit sta .lib nvm post silicon validation memory design cadence siliconsmart ddr pre silicon mram spef functional verification def primelib sram tsmc arc chip level synopsys parasitic ram

Work Mode

Work from Office

Job Type

Full Time

Job Description

Job Title:

Job Location:

Experience:

Verification Engineer

Responsibilities:

Perform
Static Timing Analysis
at block, cell, and full-chip levels for DRAM/memory designs.
Characterize standard cells (up to 40% effort) using
PrimeLib, SiliconSmart
Create and validate .lib files, write ARC for cell characterization, and run QA checks.
Develop timing constraints, analyze STA reports, and ensure violation closure.
Collaborate with design teams on parasitic modeling, validation experiments, and tape-out revisions.
Drive standardization across verification flows and contribute to innovation in next-gen memory products.

Mandatory Skills:

STA tools (Synopsys PrimeTime / Cadence Tempus)
Standard Cell Characterization (.lib, ARC, QA)
Strong circuit understanding (digital/analog mix, block to full-chip)
Timing constraints and violation debug

Good to Have:

TSMC process certification
Low-power timing closure experience
Scripting (TCL, Python, Perl)
Parasitic modeling exposure
Hands-on with reticle experiments or silicon validation

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