7 Post-Silicon Validation Jobs

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in High Bandwidth Memory/Double Data Rate (HBM/DDR). Experience in silicon bringup, functional validation, characterizing, and qualification. Experience with board schematics, layout, and debug methodologies with using lab equipment. Preferred qualifications: Experience in hardware emulation with hardware/software integration. Experience in coding (e.g., Python) for automation development. Experience in Register-Transfer Level (RTL) design, verification or emulation. Knowledge of SoC architecture including boot flows. Knowledge of HBM/DDR standards. Responsibilities Develop and execute tests for memory controller High Bandwidth Memory (HBM) post-silicon validation and on hardware emulators and assist in bring-up processes from prototyping through post-silicon validation. Drive debugging and investigation efforts to root-cause, cross-functional issues. This includes pre-silicon prototyping platforms as well as post-silicon bringup and production. Ensure validation provides necessary functional coverage for skilled design. Help operate and maintain our hardware emulation platform for pre-silicon integration and validation.

Responsibilities: Develop power management architecture for ASICs, ensuring optimal performance under power and thermal constraints. Prototype and validate SoC power management systems across various design phases. Track and analyze power-mode specifications, measurements, and optimizations through different stages of design. Collaborate with software and architecture teams to build comprehensive system-level designs and methods. Job Requirements: Bachelor's degree in Electrical Engineering or equivalent practical experience. Experience in power management or post-silicon measurements and validation. Knowledge of Dynamic Voltage Frequency Scaling (DVFS), idle power management, and system mitigation techniques. Familiarity with the impact of software and architectural decisions on power and thermal behavior, including thermal mitigation and scheduling.

Experience in working on validation of ASIC/SoC products. Knowledge of post-silicon features & functional validation for BSPs and Linux Device Drivers. Knowledge of Test case development & implementation for IP's features. Expertise in protocols/interfaces such as USB, PCIe, I2C, SPI, UART, and Ethernet. Knowledge of Software Development & Testing Life Cycles. Strong knowledge of C, Python, Shell, and Bash Scripting. Strong knowledge of Linux Kernel, Boot-Up Process, Linux-Internals, and System Calls. Understanding of Schematics and PCB board design. Experience with version control software such as GIT. Excellent Communication and learning skills.

Developing and testing software for validation and automation purposes. Performing device-level and system-level validation and debug in post-silicon environments. Executing software tests in verification environments to ensure product quality. Working with FPGA-based setups to run validation tests and update FPGA RTL modules as needed. Creating detailed test and validation reports with statistical analysis. Interfacing with customers to capture requirements and provide post-release support. The Impact You Will Have: Contributing to the development of cutting-edge technology that drives innovation in various industries. Ensuring the reliability and performance of high-speed serial interface PHYs like USB, PCIe, and Ethernet. Enhancing the validation and debug processes through meticulous testing and analysis. Improving the overall quality and functionality of Synopsys products through rigorous validation. Supporting the continuous improvement of product development cycles. Providing valuable insights and feedback to enhance future product iterations. What You'll Need: B.Tech in ECE/CS or equivalent with 3-7 years of previous experience in a similar role/industry. Experience in programming and testing using C/C++. Board-level test and debug experience using lab equipment. Experience with embedded or resource-constrained environments. Development experience on Unix, Linux, and Windows platforms. Ability to quickly learn new workflows and adapt to new technologies. Exposure to MATLAB/Python programming is a plus. Exposure to verification and basic RTL is a plus. Excellent verbal and written communication skills.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: DV Engineers DDR (either IP or SoC level experience) Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Define and implement verification strategies and test plans for DDR memory interface designs. Develop UVM/SystemVerilog-based testbenches and reusable verification components. Perform protocol-level verification for DDR memory interfaces and validate compliance. Collaborate with architecture, RTL, and system teams to understand design intent and corner cases. Own functional coverage, regression setup, and closure. Integrate DDR models, controllers, PHYs, and validate their interactions. Debug and resolve simulation failures and functional issues. Drive code and functional coverage improvements to ensure thorough verification. Lead or participate in technical reviews and mentor junior engineers. Required Skills & Experience: 10+ years of hands-on experience in ASIC/IP/SoC verification. Strong expertise in SystemVerilog, UVM, and functional coverage methodology. In-depth understanding and working experience with DDR3/DDR4/DDR5/LPDDR protocols. Experience with DDR controllers, PHY integration, and JEDEC standards. Proficient in simulation and debug tools such as Synopsys VCS, Cadence Xcelium, QuestaSim, etc. Good scripting skills in Python, Perl, or Shell for automation and regression management. Excellent debugging and problem-solving skills. Familiarity with AXI/AHB protocols and interconnects is a plus. Experience working with memory models and timing analysis. Preferred Qualifications: Experience with post-silicon validation or DDR hardware bring-up. Knowledge of formal verification tools and techniques. Experience with low power verification and timing closure tools. TekWissen Group is an equal opportunity employer supporting workforce diversity.

Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. Bachelors/ Masters with 10+ years Systems Engineering or related work experience Educational Requirements Bachelor's/Masters/ Doctorate degree in Engineering, Electronics & Communication Micro Electronics Information Systems, Computer Science, or related field. Individuals who possess skills/experience in one or more of the following are requested to apply: Preferred Qualifications: Areas of Expertise (the more the better): Working experience with Complex Embedded Systems, Mobile/ IOT/Auto domains preferred. Expertise in fields such as power performance use cases , system modeling, SOC Profiling, PPA tradeoffs, post silicon bring up, and product qual. Firm grasp of computer architecture and OS fundamentals Post Silicon System Validation of SOC Performance, Architecture Analysis and Feedback to future products. Analyzing the power-performance data for various CPU, GPU, AI workloads benchmarks Conducting detailed workload characterization and sensitivity analysis Develop and enhance analysis tools and instrumentation to assist in analysis, identifying performance gaps and optimization options CPU microarchitecture including cache, Latency, BW analysis, etc. Linux/Android kernel development, device driver development and Android architecture experience Collaborate with the architecture team on power-performance trade-off analysis as part of product definition. Power and/or performance optimization, CPU, SOC SW DCVS/DVFS Governors exposure Working experience at System level, Linux kernel internals system programming Collaborate with internal teams and external partners for analysis and optimizations Lab Hands-on: with Power Data Acquisition/DAQs, Oscilloscope, JTAGs, ARM Developer Studio exposure Exposure to ADB shell, shell scripts, Python scripts, Understanding of Linux/android systems , automation scripts/environment Exposure to Git, Jira, Android and QTI tools Good communication skills, presentation skills and should manage his/her tasks independently Acts as a tech lead on projects and owns the outcome of the project.

Responsibilities & Achievements: Reduced post-silicon bug escapes through early software-driven validation in emulation environments. (Accelerated Verification) Cut SoC bring-up time by 50% by architecting a unified simulation-to-emulation testbench with reusable transactors. Spearheaded the Accelerated verification plan for a next-gen ADAS SoC including use cases like Start Up, BOOTROM, Complex data path, Negative tests Enabled 80% reuse of verification components across simulation, emulation, and prototype platforms through modular UVM design. Successfully led a AV verification team of engineers across DV, emulation Key Skills Accelerated Verification: Synopsys ZeBu, Siemens Veloce Verification Methodologies: UVM, System Verilog, Acceleratable UVM, C based V&V Reuse & Bridging: Simulation-to-Emulation Flow, Coverage Continuity, Transactor Development is desirable.