9 Mram Jobs

Role Overview: Tata Semiconductor Manufacturing Pvt. Ltd. (TSMPL) is seeking an experienced BEOL Process Integration Lead to drive the development and optimization of embedded non-volatile memory (eNVM) technologies, including eFlash, RRAM, MRAM, and FeRAM across CMOS nodes from 130nm to 28nm, including BCD and FinFET platforms. As a BEOL Process Integration Lead, you will be responsible for leading integration setup, process development, and stabilization to meet performance, reliability, and manufacturability goals. Your role will involve guiding cross-functional teams, collaborating with tool and module owners, designing and executing experiments, analyzing data, defining process flows, a...

As the Non-Volatile Memory Design Manager at NXP in Bangalore, India, you will oversee the deployment of embedded Non-Volatile Memory solutions, including Logic NVM, Flash, and advanced memory technologies like RRAM and MRAM. Leading a team of engineers to deliver innovative NVM IP for creating differentiating products effectively, you will gain a competitive edge in the market. - Build and lead a team of 10 to 20 engineers specializing in NVM Analog Design, Digital Design, and Verification. - Define and oversee the deployment of Logic NVM, Flash, and Disruptive Memory Solutions (RRAM, MRAM). - Manage resource allocation and planning in collaboration with design management and project leads....

Job Title: Verification Engineer Job Location: Hyderabad Experience: 5 to 8 years Education: B.E./B.Tech/M.E./M.Tech in ECE, Electrical, or VLSI Design or equivalent Job Description: we are seeking a Verification Engineer specializing in Static Timing Analysis (STA) and Standard Cell Characterization for advanced memory product development (HBM, DRAM). The role involves working closely with cross-functional design and verification teams to ensure robust, high-performance memory solutions. Responsibilities: Perform Static Timing Analysis at block, cell, and full-chip levels for DRAM/memory designs. Characterize standard cells (up to 40% effort) using PrimeLib, SiliconSmart Create and validate...

As a candidate for the position, you should have a Bachelor's or Master's Degree with 3-10 years of Analog Layout experience. It is essential to possess a good understanding of advanced semiconductor technology process and device physics. Your role will involve full-custom circuit layout/verification and RC extraction experience. Experience in one or more of the following areas is preferable: Mixed signal/analog/high-speed layout, e.g., PLL, IO, RF, PMIC, OSC, DC-DC converter, Temperature sensor, SRAM, TCAM, ROM, MRAM, ESD. You should be familiar with the Cadence Virtuoso environment and various industry physical verification tools (DRC, LVS, DFM, etc.). Experience in advanced technology nod...

Memory Architect (e.g., DRAM, NAND, SRAM) Job Title: Memory Architect Location: [Bangalore / Hyderabad / Noida / Chennai] Experience: 5-12 years Education: B.Tech/M.Tech/Ph.D. in ECE, CS, or VLSI Responsibilities: Define and optimize memory architectures (DRAM, NAND, NOR, MRAM, SRAM) for performance, power, and density Develop memory access protocols, ECC strategies, and redundancy schemes Collaborate with RTL, verification, and silicon validation teams Drive design for reliability and yield Requirements: In-depth knowledge of memory design and fabrication Familiarity with JEDEC standards, timing, and signal integrity issues Experience in memory controller design is a plus Proficient in RTL ...

You should have an M.S or PhD in Electrical Engineering, Materials Science or equivalent field. You must possess a strong understanding of CMOS and eNVM device physics, process modules, yield improvement, failure mechanisms, and analytical techniques (physical and electrical). A deep understanding of key eNVM technologies such as charge trap, floating gate, RRAM, MRAM, etc is essential. Experience in technology parameters and figures of merit like bit cell size, macro size, endurance, retention, power, latency, mask count, etc is required. You should have a proven track record in delivering these technologies into volume manufacturing and achieving competitive performance. The ability to lea...

Job Description: As an Analog Layout Engineer at SILCOSYS Solutions Pvt. Ltd., you will be responsible for custom circuit layout, physical verification, and RC extraction. We are looking for a talented individual with 3 to 7 years of experience in the field. Proficiency in Cadence Virtuoso and a solid understanding of DRC, LVS, and DFM methodologies are essential for this role. Key Requirements: - Demonstrated expertise in AMS and high-speed layout design - Exposure to components such as Temperature Sensors, SRAM, TCAM, ROM, MRAM, ESD - Track record in advanced technology nodes, with experience in 5nm/3nm considered a plus - Familiarity with Totem EMIR tools and methodologies This position o...

You are a skilled embedded non-volatile memory (eNVM) Bitcell Layout Design Engineer / Lead interested in joining the eNVM team at Tata Electronics Private Limited (TEPL) to lead the development and optimization of eNVM bitcells. In this role, you will be responsible for designing layout and implementing eNVM bitcells across a wide range of Foundry CMOS technologies, from 130nm to 28nm, including BCD and advanced FinFET technology nodes. Your work will contribute to building high-yield, high-performance memory IP for various applications in automotive, IoT, and mobile markets. To excel in this position, you should ideally have 5-10 years of experience in the semiconductor industry with exper...

The Non-Volatile Memory Design Manager role within the CTO/Frontend Innovation/NVM Design Department at NXP involves overseeing the deployment of embedded Non-Volatile Memory solutions across the organization's business and product lines. This includes integrating Logic NVM, Flash, and advanced memory technologies like RRAM and MRAM. By implementing innovative NVM technologies, the team gains a competitive edge in the market. As the Design Manager for NXP's NVM design group in Bangalore, India, you will lead the expansion of the team and drive alignment among a group of talented engineers. Your primary responsibility is to ensure that the team delivers innovative NVM IP to create differentia...