Verification Engineer(standard cell characterization) Acesoft Labs

3.0 - 8.0 years

3 - 8 Lacs

Hyderabad

Work from Office

Job Title: Verification Engineer Key Responsibilities: Perform standard cell characterization (up to 40% of the time). Conduct static timing analysis (STA) (approximately 60% of the time). Characterize basic standard (STD) cells. Write ARC (Analysis and Results Capture) for STD cell characterization using PrimeLib and Silicon Smart . Conduct .lib QA checks to ensure model quality and accuracy. Understand circuits at both block-level and full-chip level . Execute STA for DRAM at block level, top level, and cell level. Write constraints and analyze STA reports for setup, hold, and timing violations. Report violations to the design team and take ownership of closure . Support parasitic modeling and assist in design validation , reticle experiments , and tape-out revisions . Perform verification using industry-standard simulators , involving modeling and simulation. Collaborate across teams to contribute to standardization and cross-functional success . Drive innovation for future memory generations within a dynamic and challenging work environment. Required Experience: 3 to 5 years of relevant experience in digital/analog verification and STA.

Posted 1 month ago

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