8 Sram Jobs

In this role you will work on SoC/Sub-system level Emulation model development and design bring up on Zebu/Veloce HW platforms. Additionally, you will work closely with design, verification, validation, and SW teams to implement emulation testbench (XTORs, Speed Adaptors) and features required to develop content on emulation models. You would develop tests to qualify models. Key Skills 815 years of experience on SoC/Sub-system Emulation of multi-million gate and complex design with multiple clocks and power domains Experience in microcontroller architecture, Cores ARM A/M series, Interconnect (NIC, FlexNoC), Protocols like AHB, AXI, Memory (Flash, SRAM, DDR4/5), and memory controllers Experience in automotive protocols like LIN, CAN, high-speed protocols like PCIe, Ethernet, USB etc. would be an advantage Emulation model creation from RTL/Netlist Experienced in Zebu/Veloce emulation platforms Create and execute test plans targeting emulation model qualification Experience with Speed Bridge Integration and perform real-time testing would be a plus Experience in integrating Acceleration VIPs/XTORs and perform co-emulation Scripting and Automation to continuously improve operational efficiency

In this role you will work on SoC/Sub-system level Emulation model development and design bring up on Zebu/Veloce HW platforms. Additionally, you will work closely with design, verification, validation, and SW teams to implement emulation testbench (XTORs, Speed Adaptors) and features required to develop content on emulation models. You would develop tests to qualify models. Key Skills 8-15 years of experience on SoC/Sub-system Emulation of multi-million gate and complex design with multiple clocks and power domains Experience in microcontroller architecture, Cores ARM A/M series, Interconnect (NIC, FlexNoC), Protocols like AHB, AXI, Memory (Flash, SRAM, DDR4/5), and memory controllers Experience in automotive protocols like LIN, CAN, high-speed protocols like PCIe, Ethernet, USB etc. would be an advantage Emulation model creation from RTL/Netlist Experienced in Zebu/Veloce emulation platforms Create and execute test plans targeting emulation model qualification Experience with Speed Bridge Integration and perform real-time testing would be a plus Experience in integrating Acceleration VIPs/XTORs and perform co-emulation Scripting and Automation to continuously improve operational efficiency.

We are seeking a skilled Senior Embedded Firmware Engineer to join our dynamic team. The ideal candidate will have 3-5 years of experience in firmware development, focusing on microcontrollers and embedded systems. Key Responsibilities Firmware Development: Design, develop, test, and maintain firmware for microcontrollers like STM32, NXP, ESP. Ensure seamless hardware-software integration using electronic fundamentals. Work with BareMetal systems and Real-Time Operating Systems (RTOS) for efficient multitasking, scheduling, and resource management, optimized firmware solutions. Strong understanding of microcontroller architecture, including the core processor, memory (Flash, SRAM, EEPROM), and peripheral modules (Timers, UART, SPI, I2C, ADC, DAC, GPIO). Designing firmware to handle fault tolerance, including watchdog timers, error detection, and recovery mechanisms for reliable operation in embedded systems. Communication Protocols: Implement and validate protocols such as SPI, I2C, MODBUS, CAN, Ethernet, and WebSocket. Apply networking basics to support communication standards. Documentation & Collaboration: Maintain clear and concise documentation for firmware and processes. Collaborate effectively with cross-functional teams and adapt to priority changes. Security & Standards: Incorporate embedded security principles into firmware design. Understand and implement industry standards related to EVSE (Electric Vehicle Supply Equipment). Debugging & Problem-Solving: Analyze and resolve firmware issues, ensuring robust and efficient solutions. Required Skills Solid understanding of hardware/electronics basics. Proficiency in C/C++ programming languages. Experience with BareMetal and Real-Time Operating Systems (RTOS). In-depth knowledge of microcontroller basics (uC Basics). Familiarity with embedded security principles. Strong documenting, analytical, and problem-solving skills. Knowledge of version control tools (e.g., Git) and defect tracking systems (e.g., Jira). Good-to-Have Skills Understanding of power electronics fundamentals. Familiarity with EVSE standards and communication protocols. Qualifications Bachelor's or master's degree in electrical engineering, Electronics and Communication Engineering (ECE), or a related field. 35 years of relevant experience in microcontroller firmware development.

Job Description: Details: Memory Design Engineer Job Requirement: We are looking to hire engineers with 2 to 10 years of experience in Memory design. Candidate needs to have comprehensive knowledge of circuit design with experience in developing CMOS memories such as SP SRAM, DP SRAM, Register File, and ROM. Should have understanding of process technologies and device behaviour and reliability issues Experience in o ptimizing performance, power, and area, reduce leakage of circuits, and drive characterization of individual memory instances and memory compilers. Understanding of SRAM PPA trade-offs is required Strong documentation skills and collaborative attitude are must haves Preferred Qualifications: Education - BE/ME/B.Tech/M.Tech Work location: Bangalore

Position 1: Memory Layout Role: Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology. Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Compiler level integration, verification of Compiler/Custom memories. Skills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required Experience : 4 to 7Years 1. Understanding of memory architecture 2. Experience in creating basic memory layouts from scratch 3. Knowledge of memory peripheral blocks, including control blocks, I/O blocks, and row drivers The candidate should have over 4 years of experience with all of the above and more than 6 years of relevant industry experience overall. Additionally, they are seeking expertise in: 4. Knowledge of compiler issues 5. Understanding of reliability issues 6. Simulation effects 7. EMI (Electromagnetic Interference) considerations Position 2: I/O Layout Design Engineer: Roles & Responsibilities: Custom layout development on block level to Top level I/O layout for GPIO, HSTL, HCSL, VTMON, LVCMOS, DDR, LVDS etc., Need knowledge on Latchup, ESD and EM. Exposure to lower nodes N3E3nm, , 5nm etc., SKILL: LVS/DRC/ERC/Litho Checks/Antenna/ESD-LU/Density etc. Should possess good knowledge on CMOS functionality, CMOS fabrication process, foundries and challenges in latest technology nodes. Skills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required. Exp: Above 4 to 6 years Location: Electronic City, Bangalore Joining date: 2 - 4 Weeks Position 3: Memory Design Validation (Verification): We are looking for energetic and passionate memory design validation engineers for the development of memory compilers and custom macros of all types on the leading edge of process technology. Typically requires a minimum of 5+ years of relevant experience. Job Description Summary Contribute towards Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers as well as custom macros in 3nm and other cutting edge process technologies Job Description Contribute towards Memory Design Validation of all types of custom memory macros and memory compilers Perform functional verification, root cause design discrepancies, and help resolve them Perform signal integrity analysis, identify design weaknesses, and propose possible solutions to address them Perform transistor level simulations to check for any Power Up or Lock up issues and help resolve them Perform EM/IR analysis/simulations and evaluate impact on timing and internal margins Perform transistor level simulations to validate timing and internal margins, identify timing characterization holes, and help resolve them Perform various QA and validation checks to ensure accurate timing and power models Develop scripts to automate verification flow and data analysis Support silicon debugs and correlation to spice models Coordinate with memory design leads, modelling leads, and managers to define and execute on the memory validation plan

Role & osition: Sr vefication engg 1 position exp - 7-10 yrs SV & UVM method, verilog simulation, exp in memory (Not theoretical, BUT practical)- really great SRAM DRAM - v good prf - Masters degree, graduate also ok. gate level simulation, AMS skills good to have Cadence, VCS - normal verification Mentor experience required, not team lead TMSC not required preference will be given to SPICE simulation No protocols required– should be a able to write a test plan, test bench Knowledge on Pearl can be alternative to PLI coding responsibilities Preferred candidate profile Perks and benefits

Position: Staff Engineer - System C Modeling Experience: 6 to 10 yrs Job Location: Bangalore Job Type: Permanent & Day Shift Qualification: B.Tech / B.E / M.Tech / M.E Responsibilities: Hands-on contributions coding C++ & System C models & test creation Debug issues in Firmware environment Validating the developed model using SV/UVM testbench Debug failures and root-cause it by interacting with other teams/groups Etc. Experience: 5 to 8 Years of experience in the following areas: - Functional Modeling & Verification: Hands-on experience in C++ & System C based Model development/test creation Prior Experience with C based Tests/Test bench development Python coding would be a plus Knowledge on NAND concepts will be an advantage - Knowledge on Memory and Digital Design Concepts would be preferable (SRAM/DRAM/ROM/Flash) Circuits/Logic - Languages Expertise: C, C++, Python, System C, System Verilog/UVM will be a plus - Tool Expertise: Visual Studio , Git, Bitbucket Education & Soft Skills: Bachelors/Masters from a reputed College/University with Electronics and communication/Embedded Systems background Strong Problem Solving Efficient Communication Team Leading & Mentoring skills Kindly Note: Candidates who cannot relocate to Bangalore, are not preferred to apply. We are looking for candidates who can join 15 to 30 days notice. Interested candidates please feel free to reach out Ravindra @ 8340937197 or Please email your profile to: ravindra.m@creenosolutions.com

Job Description: Memory design engineer. Responsibilities: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA. Required Skills and Experience : We Prefer graduate or postgraduate from a University or Engineering School, in Electronic Engineering or equivalent Engineering Degree. You have some understanding of computer architecture and concepts. We expect you to have basic understanding of CMOS Transistors, their behaviors. We expect some basic understanding of high speed/low power CMOS circuit design, clocking scheme, Static and complex logic circuits. Understanding of Power versus Performance versus Area trade-offs in typical CMOS design. You have an engineering demeanor and Passion for Circuit design. Expected to have good interpersonal skills. Minimum 5Yrs of experience in SRAM / memory design Margin, Char and its related quality checks. Nice To Have Skills and Experience : You know basic scripting languages, e.g. Perl/TCL/Python. Some Experience of working on Cadence or Synopsys flows. Experience with Circuit Simulation and Optimization of standard cells.