13 Sram Jobs

As a Senior Circuit Design Verification Engineer at Micron Technology, you will be part of a highly innovative and dynamic team working with cutting-edge memory technologies. Your primary responsibility will be to lead the verification effort to ensure the accurate and timely delivery of sophisticated memory designs. You will have the opportunity to work on full chip gate level custom designs with advanced low power and power management technologies, covering categories such as DDR4, LPDDR4, DDR5, and LPDDR5, operating at high speeds of up to 6400MT/s. In this role, you will collaborate closely with global design and verification team members, leveraging their extensive experience in memory design. Your responsibilities will include guiding the verification effort, providing support to design projects by simulating and analyzing designs, developing test cases to increase functional coverage, and participating in the development of verification methodology and environments for complex products. Additionally, you will work on developing new verification flows and maintaining test benches using simulation tools. To succeed in this role, you should possess strong communication skills, the ability to work well in a team, and analytical capabilities for complex CMOS and gate level circuit designs. Proficiency in SPICE and/or Verilog simulations, as well as experience in SystemVerilog, PLI coding, UVM Test Bench, DRAM, SRAM, and AMS verification, are essential qualifications for this position. A Bachelor's or Post Graduate Degree in Electronics Engineering or a related field is required. Micron Technology is a global leader in memory and storage solutions, driving innovations that transform how information enriches lives worldwide. With a focus on customer satisfaction, technology leadership, and operational excellence, Micron offers high-performance DRAM, NAND, and NOR memory and storage products through its Micron and Crucial brands. By joining Micron, you will be part of a team that fuels the data economy, enabling advancements in artificial intelligence and 5G applications across various platforms. To learn more about Micron Technology and explore career opportunities, please visit micron.com/careers. For assistance with the application process or to request accommodations, please contact hrsupport_in@micron.com. Micron Technology complies with labor laws and standards, prohibiting the use of child labor and ensuring adherence to applicable regulations.,

As a Lead Memory Design Engineer, you will be responsible for driving the architecture, design, and development of advanced memory IPs including SRAMs, ROMs, CAMs, and Register Files. Your role will involve leading a team of designers, collaborating with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Your key responsibilities will include defining architecture and design specifications for custom memory IPs, optimizing circuits such as memory cell arrays, sense amplifiers, and decoders, leading schematic-level design and simulation, collaborating with layout and verification teams, guiding post-layout activities, ensuring designs meet requirements for DFM and reliability, contributing to methodology development, supporting silicon bring-up, and providing technical leadership to junior engineers. To be successful in this role, you should have a B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering, along with 8+ years of experience in full-custom memory design. You should possess a solid understanding of CMOS analog/digital circuit design principles, expertise in circuit simulation tools, experience with advanced nodes, and hands-on experience with variation analysis, IR drop, and EM checks. Strong analytical, communication, and leadership skills are essential for this position. Preferred qualifications include experience in memory compiler design, knowledge of low-power memory design techniques, experience with ECC and redundancy strategies, familiarity with ISO 26262/Safety compliance, and scripting knowledge for automation of design and simulation flows. If you are interested in this opportunity, please share your CV with Sharmila.b@acldigital.com.,

Job Description • M emory layout engineer. • Experience Level 3 to 8 Years ( Mid-Level Role) Responsibilities: As Memory Layout Engineer, we will work on developing memory compilers layouts and memory Fast Cache instances layouts for our next generation Cores achieving outstanding PPA. Required Skills and Experience : We Prefer graduate or postgraduate from a University or Engineering School, in Electronic Engineering or equivalent Engineering Degree. We expect you to have basic understanding of CMOS Transistors, their behaviors. We expect some basic understanding of CMOS logic design and layout. Understanding of Power versus Performance versus Area trade-offs in typical CMOS design. You have an engineering demeanor and Passion for Circuit layouts. Expected to have good interpersonal skills. Capable of creating high quality design rule driven layout Able to review schematics with engineering and propose changes based on layout implications. Exploring possible floor planning options and proposing improvements Minimum 5Yrs of experience in SRAM / memory layouts creation and backend verifications including EMIR analysis. Nice To Have Skills and Experience : You know basic scripting languages, e.g. Perl/skill. Some Experience of working on Cadence or Synopsys flows.

Role & responsibilities : Design knowledge of memory architectures & their interfaces SRAM, SDRAM, DPRAM, EEPROM, DDR2/3 Hands-on experience with EMI/EMC. Hands-on experience with a high-speed digital design like FPGA, Processors, and Controllers interfaces Analysis: AC, DC, Loading, Power, Current, Derating, Lighting, Obsolescence. Preparation of schematic design, netlist, and BOM using various ECAD tools Verification of the Designed PCB Files using Allegro and Cadstar Design viewer Testing and troubleshooting of the designed boards. Develop & Deploy hardware products as per requirement. Sound knowledge of peripheral interfaces (Serial, I2C, SPI, ADC, CAN, etc.) Understanding of Interface Control Documents (ICD) and Electrical interfaces like RS232/422/485, I2C, SPI, Ethernet, and USB Preferred candidate profile : Experience in Designing with 8/16/32 Microprocessor / Microcontroller Experience with protocols & interfaces like RS-232, 485, SPI, I2C, IrDA, ARINC429, and AFDX. Working experience in the validation testing of DC-DC converters and SMPS. Experience with ARM, AVR, and PIC-based microcontrollers. Experience in design and development, including testing and debugging. Perks and benefits

The role requires 3 to 8 years of experience in SRAM Memories layout design. You should be well-versed in various levels of memory layouts including custom memory bits, leaf cells, control blocks, Read-Write, Sense Amplifiers, and decoders. Proficiency in floor planning, power planning, block area estimation of memory designs or compliers is essential. You must have expertise in leaf cell layout development and physical verification. Additionally, a good understanding of schematics, interface with circuit designer and CAD, and process development team is required. Strong knowledge of layout fundamentals such as Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc. is necessary. Understanding layout effects on the circuit like speed, capacitance, power, and area is crucial. Excellent problem-solving skills in solving area, power, performance, and physical verification of custom layout are expected. Experience with Cadence tools including Virtuoso schematic editor, Virtuoso layout L, XL & Verification tools like Mentor Calibre is preferred. Leadership qualities and the ability to multitask are important. Working in a team environment, guiding, and providing technical support to team members are key responsibilities. Self-motivation, hard work, goal orientation, and excellent verbal and written communication skills are essential. Knowledge of Skill coding and layout automation is a plus. Responsibilities include Memory Compiler layout development and verification, Layout design and development of Memory blocks such as Array, Row/Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. Performing layout verification like LVS/DRC/Latchup, quality check, and documentation. Ensuring on-time delivery of block-level layouts with acceptable quality. Demonstrating leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedule/milestones in a multiple project environment. Guiding junior team-members in their execution of Sub block-level layouts & reviewing their work. Contributing to effective project management and effectively communicating with engineering teams to assure project success. UST is a global digital transformation solutions provider that has been operating for over 20 years. UST partners with clients from design to operation, embedding innovation and agility into their organizations. With over 30,000 employees in 30 countries, UST aims to make a boundless impact touching billions of lives in the process.,

Job Description : We are looking for a VLSI MBIST Engineer with strong expertise in Memory Built-In Self-Test (MBIST) methodologies for ASIC/SoC designs. The ideal candidate should have hands-on experience using Synopsys SMS tool and a solid understanding of MBIST test development, pattern generation, and fault simulation. Key Responsibilities : Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) Use Synopsys SMS tool for MBIST pattern generation and validation Perform fault modeling, fault simulation, and fault coverage analysis Integrate MBIST macros into SoC designs in collaboration with RTL and physical design teams Debug MBIST issues in pre- and post-silicon stages Document MBIST flows, generate test reports, and provide support for DFT reviews Stay updated on industry trends and best practices in MBIST and memory testing Required Skills : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related fields 4+ years of experience in MBIST implementation and validation Strong experience with Synopsys SMS tool Proficiency in scripting languages like TCL, Perl, or Python Good knowledge of Verilog/SystemVerilog and digital design fundamentals Familiarity with simulation tools like VCS, ModelSim Preferred Skills : Experience with DFT tools such as Tessent Knowledge of ATPG, JTAG (IEEE 1149.1), and IEEE 1500 standards Exposure to silicon bring-up and failure analysis

Job description: Circuit design, simulation, and characterization of full custom circuits Functional simulations and statistical analysis Sign off and release the memory IPs on dedicated IP validation test chips Support Silicon bring-up and characterization Participate in implementation & design/layout reviews Contribute with innovative ideas for addressing design problems Work closely and collaborate with IP design and layout teams Required Qualifications: Requires MTech in Electrical (VLSI, Microelectronics and related fields) from a reputed university with 10-12 years of relevant experience Applicant should have a proficient knowledge of and experience with EDA (Cadence, Mentor Graphics, Synopsys) tools for schematic design & simulations (Virtuoso, Spectre, HSPICE, etc.) Experience in NVM Memory(eFlash/SRAM/eNVM design)) designs Experience in analog circuits Charge pumps, regulators, low voltage analog circuits, sense amplifier Good understanding and analysis of READ/PROGRAM/ERASE simulations and analysis General analog mixed-signal design concepts is desirable Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Preferred Qualifications: Knowledge in various technologies (Bulk, CMOS & SOI) process is desirable Hands on knowledge of state-of-the-art memory or analog design flows Programming experience applicable to design flow automation tasks Dedication and the capability to work within a very dynamic interdisciplinary environment Knowledge of 45/32/28nm and below technology nodes is an advantage. Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional Spoken and Written Proficiency in English Strong analytical and problem-solving skills. Role & responsibilities Preferred candidate profile

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com call me :7995220108. Client Name: Proxelera Position Name VLSI MBIST Engineer Position type: Permanent Total Exp: 4-8 years HBTS Budget: Open Notice Period: Immediate to 15days Work Location: Bangalore South Job Description Must have: We are seeking a skilled VLSI MBIST Engineer with approximately 4 years of experience, specialized in Memory Built-In Self-Test (MBIST) methodologies. The ideal candidate will have hands-on experience with Synopsys SMS tool and be proficient in MBIST pattern generation, fault simulation, and test development for various embedded memories in ASIC/SoC designs. Requirements Key Responsibilities: Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) using Synopsys SMS tool. Create MBIST test infrastructure and collaborate with design teams to integrate MBIST macros into SoC designs. Perform fault modeling, fault simulation, and analysis to ensure high fault coverage and test quality. Validate MBIST patterns through simulation and silicon validation. Debug MBIST failures at both pre-silicon and post-silicon stages and provide root cause analysis. Work closely with RTL designers, physical design, and test teams to optimize MBIST architecture and test flows. Generate MBIST test reports, documentation, and provide design-for-test (DFT) reviews. Stay updated with latest MBIST methodologies and industry trends. Required Skills & Qualifications: Bachelors/Master’s degree in Electronics, Electrical Engineering, VLSI, or related field. Minimum 4 years of experience in MBIST engineering for ASIC/SoC designs. Strong knowledge of MBIST architectures, memory testing algorithms, and fault models. Hands-on experience with Synopsys SMS tool for MBIST pattern generation and validation. Familiarity with other DFT tools and methodologies is a plus. Proficient in scripting languages such as TCL, Perl, or Python for automation of MBIST flows. Good understanding of digital design and RTL coding (Verilog/SystemVerilog). Experience with simulation tools (ModelSim, VCS, etc.) and testbench development. Strong analytical and problem-solving skills with attention to detail. Good communication skills and ability to work in a team environment. Preferred Skills: Experience with other memory test tools or DFT tools like Tessent. Knowledge of ATPG and other DFT methodologies. Exposure to silicon bring-up and failure analysis. Familiarity with industry standards such as IEEE 1149.1 (JTAG), IEEE 1500. AMD (Don’t Share AMD Profiles) Preferred candidate profile

Your Job: ? Developing CMOS memories such as SP SRAM, DP SRAM, Register File, and ROM. Circuit design, simulation, Margining and characterization of full custom circuits Functional simulations and statistical analysis Verifying bit cells, physical layout design and verification. Sign off and release the memory IP's on dedicated IP validation test chips Support Silicon bring-up and characterization Participate in implementation & design/layout reviews Contribute with innovative ideas for addressing design problems Work closely and collaborate with IP design and layout teams Required Qualifications: Requires Bachelors/Master in Electrical (VLSI, Microelectronics and related fields) from a reputed university with Minimum 4-12 years Work/Industry experience Bachelor's degree with 10+ years or master's degree with 8+ years experience in semiconductors/Microelectronics/VLSI engineering Applicant should have a proficient knowledge of and experience with EDA (Cadence, Mentor Graphics, Synopsys) tools for schematic design & simulations (Virtuoso, Spectre, HSPICE, etc.) Experience in SRAM Memory designs Experience in timing characterization, Verilog is desirable General analog mixed-signal design concepts is desirable Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Be able to collaborate with technical design leads on multiple concurrent projects. Preferred Qualifications:? Knowledge in various technologies (Bulk, CMOS & SOI) process is desirable Hands on knowledge of state-of-the-art memory or analog design flows Programming experience applicable to design flow automation tasks Dedication and the capability to work within a very dynamic interdisciplinary environment Knowledge of 45/32/28/14nm and below technology nodes is an advantage. Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional Spoken and Written Proficiency in English? Strong analytical and problem-solving skills.?

In this role you will work on SoC/Sub-system level Emulation model development and design bring up on Zebu/Veloce HW platforms. Additionally, you will work closely with design, verification, validation, and SW teams to implement emulation testbench (XTORs, Speed Adaptors) and features required to develop content on emulation models. You would develop tests to qualify models. Key Skills 815 years of experience on SoC/Sub-system Emulation of multi-million gate and complex design with multiple clocks and power domains Experience in microcontroller architecture, Cores ARM A/M series, Interconnect (NIC, FlexNoC), Protocols like AHB, AXI, Memory (Flash, SRAM, DDR4/5), and memory controllers Experience in automotive protocols like LIN, CAN, high-speed protocols like PCIe, Ethernet, USB etc. would be an advantage Emulation model creation from RTL/Netlist Experienced in Zebu/Veloce emulation platforms Create and execute test plans targeting emulation model qualification Experience with Speed Bridge Integration and perform real-time testing would be a plus Experience in integrating Acceleration VIPs/XTORs and perform co-emulation Scripting and Automation to continuously improve operational efficiency

In this role you will work on SoC/Sub-system level Emulation model development and design bring up on Zebu/Veloce HW platforms. Additionally, you will work closely with design, verification, validation, and SW teams to implement emulation testbench (XTORs, Speed Adaptors) and features required to develop content on emulation models. You would develop tests to qualify models. Key Skills 8-15 years of experience on SoC/Sub-system Emulation of multi-million gate and complex design with multiple clocks and power domains Experience in microcontroller architecture, Cores ARM A/M series, Interconnect (NIC, FlexNoC), Protocols like AHB, AXI, Memory (Flash, SRAM, DDR4/5), and memory controllers Experience in automotive protocols like LIN, CAN, high-speed protocols like PCIe, Ethernet, USB etc. would be an advantage Emulation model creation from RTL/Netlist Experienced in Zebu/Veloce emulation platforms Create and execute test plans targeting emulation model qualification Experience with Speed Bridge Integration and perform real-time testing would be a plus Experience in integrating Acceleration VIPs/XTORs and perform co-emulation Scripting and Automation to continuously improve operational efficiency.

We are seeking a skilled Senior Embedded Firmware Engineer to join our dynamic team. The ideal candidate will have 3-5 years of experience in firmware development, focusing on microcontrollers and embedded systems. Key Responsibilities Firmware Development: Design, develop, test, and maintain firmware for microcontrollers like STM32, NXP, ESP. Ensure seamless hardware-software integration using electronic fundamentals. Work with BareMetal systems and Real-Time Operating Systems (RTOS) for efficient multitasking, scheduling, and resource management, optimized firmware solutions. Strong understanding of microcontroller architecture, including the core processor, memory (Flash, SRAM, EEPROM), and peripheral modules (Timers, UART, SPI, I2C, ADC, DAC, GPIO). Designing firmware to handle fault tolerance, including watchdog timers, error detection, and recovery mechanisms for reliable operation in embedded systems. Communication Protocols: Implement and validate protocols such as SPI, I2C, MODBUS, CAN, Ethernet, and WebSocket. Apply networking basics to support communication standards. Documentation & Collaboration: Maintain clear and concise documentation for firmware and processes. Collaborate effectively with cross-functional teams and adapt to priority changes. Security & Standards: Incorporate embedded security principles into firmware design. Understand and implement industry standards related to EVSE (Electric Vehicle Supply Equipment). Debugging & Problem-Solving: Analyze and resolve firmware issues, ensuring robust and efficient solutions. Required Skills Solid understanding of hardware/electronics basics. Proficiency in C/C++ programming languages. Experience with BareMetal and Real-Time Operating Systems (RTOS). In-depth knowledge of microcontroller basics (uC Basics). Familiarity with embedded security principles. Strong documenting, analytical, and problem-solving skills. Knowledge of version control tools (e.g., Git) and defect tracking systems (e.g., Jira). Good-to-Have Skills Understanding of power electronics fundamentals. Familiarity with EVSE standards and communication protocols. Qualifications Bachelor's or master's degree in electrical engineering, Electronics and Communication Engineering (ECE), or a related field. 35 years of relevant experience in microcontroller firmware development.

Job Description: Details: Memory Design Engineer Job Requirement: We are looking to hire engineers with 2 to 10 years of experience in Memory design. Candidate needs to have comprehensive knowledge of circuit design with experience in developing CMOS memories such as SP SRAM, DP SRAM, Register File, and ROM. Should have understanding of process technologies and device behaviour and reliability issues Experience in o ptimizing performance, power, and area, reduce leakage of circuits, and drive characterization of individual memory instances and memory compilers. Understanding of SRAM PPA trade-offs is required Strong documentation skills and collaborative attitude are must haves Preferred Qualifications: Education - BE/ME/B.Tech/M.Tech Work location: Bangalore