Senior Layout Engineer

Job Description

Job Title: Senior Custom Layout Engineer Experience: 5+ Years Location: Hyderabad Education: BE or MTech in Electronics / VLSI Engineering Process Node Experience: TSMC 3nm / 5nm / 7nm (TSMC Certification preferred) Job Description: We are seeking a Senior Custom Layout Engineer responsible for the design and development of critical analog, mixed-signal, custom digital blocks, along with full-chip level integration support. The role demands hands-on expertise in layout development, physical verification, and delivery in advanced technology nodes. Key Responsibilities: Design and develop analog, mixed-signal, and custom digital layout blocks Provide support for full-chip level layout integration Perform layout verification including LVS, DRC, Antenna checks, and quality assurance Ensure on-time delivery of high-quality block-level layouts Maintain accurate execution across multiple parallel projects to meet tight schedules Guide and review layout work of junior team members Collaborate closely with local engineering teams to ensure project success Contribute to effective project management and documentation Required Skills: Minimum 5 years of hands-on experience in analog/custom layout in advanced CMOS processes Proficiency in Cadence VLE/VXL Expertise with Mentor Graphics Calibre for DRC/LVS verification Strong understanding of layout effects such as matching, IR-drop, coupling, parasitics Excellent debugging and problem-solving skills in physical verification Experience working with TSMC 3nm/5nm/7nm process nodes Strong communication and teamwork skills Preferred: TSMC Layout Certification Experience with complex block and sub-block level layout reviews Familiarity with quality check procedures and support documentation