22 Memory Design Jobs

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory

Candidate should have worked in memory domain and preferably candidate should have worked on Memory characterization, design and validation. Candidate should be familiar with layout parasitic extraction and challenges in deep submicron technologies. Candidates should be familiar with Spice decks and should be able to write spice decks, stimulus and test vectors and validate them. Candidates should have good knowledge and should have hands on experience with fast simulator tools. Candidate should have good memory design knowledge and should have debugging skills and should be familiar with waveform viewers etc . Candidate should be familiar with NMDL + CCST. libs and should have hands on experience on generating libs and sign off QA checks etc . Candidate should be familiar with validating libs with tight stimulus (sanity) runs. Candidates with scripting knowledge will be preferred Interested can contact me at shubhanshi@incise.in

Role & responsibilities Description: Performs semiconductor design engineering assignments including engineering and designing chip layout circuits, circuit checking, documenting specifications, modifying and evaluating semiconductor devices and components. Reviews product requirements and logic diagrams for device definition. Typically responsible for projects, or portions of projects, to design, fabricate, modify, and evaluate semiconductor devices and components. 3-5 years of experience Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Experience with Gate Level Simulations and timing debugs. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Additional Details TSMC Certification:- Added Advantage

Job description About The Role Designs, develops, and builds digital circuits for custom blocks including SRAM, register files, memory compilers, and caches. Designs floorplans, performs circuit design, schematic entry, simulation for major blocks, and verifies functionality to optimize custom circuit for power, performance, area, timing, and yield goals. Creates block level DFT models, develops memory test tools, and improves and automates flows and methodologies to ensure streamlining of design. Collaborates cross functionally to report design progress and to collect, track, and resolve any performance and memory circuit design issues. Optimizes performance, power, and area, reduce leakage of circuits, and drive characterization of individual memory instances and memory compilers. Works with architecture and layout teams to design circuit for best functionality, robustness, and electrical capabilities. Qualifications The candidate must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum qualifications Must have a Bachelors (B.Tech) in Electronics or Masters (M.Tech) in Electrical, Microelectronics or VLSI Engineering. B.Tech with 8+ years and M. Tech with 6+ years experience required. 6+ years experience with scripting (Perl, tcl etc. 6+ years experience in memory design convergence tools including formal equivalence verification, static timing methodology, electrical reliability and robustness analysis. 6+ years experience with transistor level operation, memory bitcell design, design challenges under process variations and low power circuit techniques, Innovative architectural proposals, driving layouts and its driven decisions. Preferred Qualifications Some experience in scripting, compiler understanding and hands on experience in coding tilers.

As part of Synopsys, you will be at the forefront of innovations that are reshaping the way we live and work. From self-driving cars to Artificial Intelligence, 5G to the Internet of Things, we are driving the Era of Smart Everything with cutting-edge technologies in chip design and software security. If you are driven by a passion for innovation, we invite you to join our team. The Silicon Design & Verification business focuses on accelerating the development of high-performance silicon chips. As the world's leading provider of solutions for designing and verifying advanced silicon chips, we are committed to designing the next-generation processes and models essential for chip manufacturing. By enabling our customers to optimize chips for power, cost, and performance, we significantly reduce project timelines. As a member of the Custom Design Solutions Team within Synopsys's EDA Group, you will collaborate with top-tier customers to implement high-quality Custom/Analog Design Solutions on the latest process nodes. Working across various design stages, including front-end, simulation, back-end, and verification flows, the team emphasizes diversity in design experiences. You will have the opportunity to leverage your design expertise to architect and develop innovative Custom Design solutions. In the role of Solutions Engineering, Principal Engineer, your responsibilities will include: - Promoting the adoption of Synopsys Custom Design Platform to new Customers through presentations and demos - Understanding Customer flow requirements and aligning them with features in Synopsys Custom Design Platform - Collaborating with R&D and Product Marketing to drive the development of new flows and functionalities - Defining Analog Design flows and methodologies to enhance customer productivity - Creating Custom scripts tailored to specific customer needs or for rapid problem-solving - Managing customer relationships by ensuring clear communication of requirements to R&D and tracking feature development To qualify for this role, you should have: - A BE/MTech degree in Electrical/Electronics/Computer Engineering - Over 15 years of experience in creating and supporting custom design flows using tools like Custom Compiler - Hands-on experience in Analog design and coding medium-sized software solutions for custom design challenges - Expertise in areas such as advanced custom layout flows, simulation environments, parasitic extraction techniques, mixed-signal design, memory design, and custom placement and routing If you are a seasoned professional with a strong background in custom design flows and a desire to drive innovation in the semiconductor industry, we encourage you to apply for this position.,

Role & responsibilities Core Requirements Basic understanding of CMOS and gate level circuit designs Familiarity with SPICE Familiarity with Verilog simulations Good communication skills and ability to work well in a team Preferred Qualities Analytical capability for complex gate level circuit designs Experience in SystemVerilog, PLI coding Experience in UVM Test Bench Experience in DRAM, SRAM or other memory related fields Experience Level 5+ years Preferred candidate profile

Role Responsibilities: Map the IP ecosystem and anticipate future Foundation IP product requirements for Google's custom silicon solutions. Collaborate with Architecture, Product Management, Design, SOC IP Integration, and IP QA teams to ensure product excellence. Work with IP vendors to influence new features, schedules, and IP portfolios to maximize product differentiation. Drive SOW, ECOs, change/version controls, and develop IP QA checklists and guidelines to ensure quality and performance. Job Requirements: Master's degree in Electrical Engineering or equivalent practical experience. 6 years of experience in memory, standard cell, GPIO, and other custom designs. Experience with RTL to GDS flow and integration. Experience working with or managing silicon IP vendors and foundries.

As a Lead Memory Design Engineer, you will be responsible for driving the architecture, design, and development of advanced memory IPs including SRAMs, ROMs, CAMs, and Register Files. Your role will involve leading a team of designers, collaborating with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Your key responsibilities will include defining architecture and design specifications for custom memory IPs, optimizing circuits such as memory cell arrays, sense amplifiers, and decoders, leading schematic-level design and simulation, collaborating with layout and verification teams, guiding post-layout activities, ensuring designs meet requirements for DFM and reliability, contributing to methodology development, supporting silicon bring-up, and providing technical leadership to junior engineers. To be successful in this role, you should have a B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering, along with 8+ years of experience in full-custom memory design. You should possess a solid understanding of CMOS analog/digital circuit design principles, expertise in circuit simulation tools, experience with advanced nodes, and hands-on experience with variation analysis, IR drop, and EM checks. Strong analytical, communication, and leadership skills are essential for this position. Preferred qualifications include experience in memory compiler design, knowledge of low-power memory design techniques, experience with ECC and redundancy strategies, familiarity with ISO 26262/Safety compliance, and scripting knowledge for automation of design and simulation flows. If you are interested in this opportunity, please share your CV with Sharmila.b@acldigital.com.,

As a member of the SRAM design group in Bangalore, you will be involved in the development of various types of SRAMs, Register files, and ROMs in advanced technology nodes such as 4nm, 2nm, and beyond. Your primary responsibility will be to deliver highly competitive memories for SAMSUNG Foundry customers. This position offers a unique opportunity for individuals who are passionate about innovation and enjoy solving complex circuit design challenges. Working at Samsung Foundry, a pioneer in new device technology, will provide you with ample opportunities to innovate and design cutting-edge IPs. Your role and responsibilities will include designing highly competitive circuits to meet performance/power specifications requested by customers. You will guide and lead a group of engineers to ensure timely delivery of the SRAM IP. It will be crucial for you to analyze circuits, identify potential robustness gaps, and develop solutions to enhance the robustness of the design. You will take ownership of the entire process from SPEC to GDS and DK delivery, review circuits and robustness reports, and address any potential issues. Additionally, you will review layouts and provide suggestions for improvement to achieve competitive PPA. Understanding SRAM PPA trade-offs and selecting the right techniques to meet specifications will be a key aspect of your role. Effective communication across different teams is essential for successful collaboration. To excel in this position, you should hold a Master's or Bachelor's degree in electronics and have at least 10 years of working experience, preferably in Memory design. A strong understanding of RC network and finfet fundamentals is necessary. Experience in Custom or Compiler SRAM/ROM development, as well as knowledge of process variability and its impact on memory design, will be beneficial. You should have a thorough understanding of SRAM bit cell characteristics such as Read current, Standby current, data retention, and SNM. Proficiency in circuit design fundamentals, critical path modeling concepts, and various types of models (RC, C, Pai, ladder) is required. Additionally, a good grasp of semiconductor physics, including finfet function and parasitics, is essential. Analyzing layouts and understanding LLE effects will also be part of your responsibilities. If you are a detail-oriented individual with a passion for innovation and a strong background in circuit design, we encourage you to apply for this challenging yet rewarding opportunity. Your expertise and dedication will play a crucial role in delivering cutting-edge memory solutions to Samsung Foundry customers.,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Roles and Responsibilities Work closely with CAD and custom macro/memory design leads to understand the design methodology and high level requirements and develop flows. Develop efficient analysis and model generation methodologies for timing and noise to achieve tight correlation. Determine key areas where automation and leading methodologies can help improve PPA. Define, innovate and implement new infrastructure capabilities that can be used to accelerate design and development, and improve user experience. Preferred qualifications MS degree in Computer Engineering; 5+ years of practical experience Strong skills in transistor level signoff tools for timing, emir, simulations, extraction and IPQA. Experience in flow development at high scale (multithreading, ml capabilities, hyperscaling, schedulers, filer hot-spot management etc.). Direct experience with efficient visualization tools to analyze results, log parsers, web views, error/warning scanners etc. Strong fundamentals in scripting languages (python, tcl, sh. others), automation, general purpose CAD infrastructure and flows. Good understanding of stdcell or memory design fundamentals. Excellent partner collaborating with design team in flow debug and support. Experience with signing off accuracy and correlation of analysis flows (compare to spice, foundry models, etc.) Tool knowledge in any of these is a plus – nanotime, xa/spectre, liberate, primelib, totem

Job description: Circuit design, simulation, and characterization of full custom circuits Functional simulations and statistical analysis Sign off and release the memory IPs on dedicated IP validation test chips Support Silicon bring-up and characterization Participate in implementation & design/layout reviews Contribute with innovative ideas for addressing design problems Work closely and collaborate with IP design and layout teams Required Qualifications: Requires MTech in Electrical (VLSI, Microelectronics and related fields) from a reputed university with 10-12 years of relevant experience Applicant should have a proficient knowledge of and experience with EDA (Cadence, Mentor Graphics, Synopsys) tools for schematic design & simulations (Virtuoso, Spectre, HSPICE, etc.) Experience in NVM Memory(eFlash/SRAM/eNVM design)) designs Experience in analog circuits Charge pumps, regulators, low voltage analog circuits, sense amplifier Good understanding and analysis of READ/PROGRAM/ERASE simulations and analysis General analog mixed-signal design concepts is desirable Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Preferred Qualifications: Knowledge in various technologies (Bulk, CMOS & SOI) process is desirable Hands on knowledge of state-of-the-art memory or analog design flows Programming experience applicable to design flow automation tasks Dedication and the capability to work within a very dynamic interdisciplinary environment Knowledge of 45/32/28nm and below technology nodes is an advantage. Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional Spoken and Written Proficiency in English Strong analytical and problem-solving skills. Role & responsibilities Preferred candidate profile

Memory development and behavior modeling. Developing advanced models/views for leading-edge EDA design/layout/analysis tools/flows. Memory QA methodology development and execution. Maintain and support released memories. Programming for flow and procedure automation. Specific Tasks to Complete: Support internal and external memory compilers. Memory instance view generation and characterization. Develop memory verification methodology Post silicon memory analysis Minimum Requirements: MSEE or MSCE with 2+ years of industrial experience in memory development. Solid industrial experience with memory design and verification. Experienced with both transistor-level and gate-level simulations. Familiar with design and layout of logic circuits. Good knowledge of analog and digital design flows. Good UNIX background and Perl/Shell/SKILL scripting skills. Strong problem-solving, written, and verbal communication skills.

Responsibilities: Collaborate with cross-functional teams on product development. Ensure compliance with industry standards and customer requirements. Design memories, characterize performance.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory

Research and analyze emerging memory technologies, to understand their characteristics, advantages, and limitations. Collaborate with system architects and product teams to define memory requirements Health insurance Provident fund Annual bonus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Roles and Responsibilities Work closely with CAD and custom macro/memory design leads to understand the design methodology and high level requirements and develop flows. Develop efficient analysis and model generation methodologies for timing and noise to achieve tight correlation. Determine key areas where automation and leading methodologies can help improve PPA. Define, innovate and implement new infrastructure capabilities that can be used to accelerate design and development, and improve user experience. Preferred qualifications MS degree in Computer Engineering; 5+ years of practical experience Strong skills in transistor level signoff tools for timing, emir, simulations, extraction and IPQA. Experience in flow development at high scale (multithreading, ml capabilities, hyperscaling, schedulers, filer hot-spot management etc.). Direct experience with efficient visualization tools to analyze results, log parsers, web views, error/warning scanners etc. Strong fundamentals in scripting languages (python, tcl, sh. others), automation, general purpose CAD infrastructure and flows. Good understanding of stdcell or memory design fundamentals. Excellent partner collaborating with design team in flow debug and support. Experience with signing off accuracy and correlation of analysis flows (compare to spice, foundry models, etc.) Tool knowledge in any of these is a plus- nanotime, xa/spectre, liberate, primelib, totem Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Basics nand , nor , latches , flops , building blocks , tools - finesim , spectre; DRAM/ SRAM is Mandatory Simulation tools: Cadence/Spectre/ primesim - Must Have Experience: 3-5 Yrs Onsite: Hyderabad

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). 2-5 years of experience in Custom layout and Memory Layout design. Memory Leafcell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures and compilers Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, DRC limitations and work closely with CAD engineers for better customization of DRC and tiling layout. Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions. Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow Proficient in SKILL and PERL for custom tiling and automations

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). 2-5 years of experience in Custom layout and Memory Layout design. Memory Leafcell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures and compilers Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, DRC limitations and work closely with CAD engineers for better customization of DRC and tiling layout. Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions. Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow Proficient in SKILL and PERL for custom tiling and automations

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Memory Design Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :About The Role (Memory Design Engineer) :Job Overview:Memory Design & Characterization Engineer with 3-5 years of expQualification:Good understanding of Memory Design & Characterization using Silicon Smart or equivalent Good if candidate Hands-on experience on AOCV/LVF working experience/understanding is required Hands-on experience characterizing physical IPs Strong experience with simulation tools like Monte Carlo, Hspice, Finesim, Nanosim, Hsim etc. and Synopsys liberty format description is required. Automation skills (Proficient in PERL/SHELL scripting) Good understanding of CMOS circuit design fundamentals Excellent communication skills Good if candidate Hands-on experience on APL model generation for RH IR drop analysis. Good if candidate Hands-on experience on IP modeling (Verilog)Job Overview:Good understanding of digital circuits Hands-on experience characterizing physical Ips Automation skills (Proficient in PERL/SHELL scripting) Good understanding of CMOS circuit design fundamentals Excellent communication skills and ability to work across multiple projects is criticalAs a Software Development Engineer, you will engage in a dynamic work environment where you will analyze, design, code, and test various components of application code across multiple clients. Your typical day will involve collaborating with team members to ensure the successful implementation of software solutions, performing maintenance and enhancements, and contributing to the overall development process. You will be responsible for delivering high-quality code while adhering to project timelines and standards, ensuring that the applications meet the needs of the clients effectively. Roles & Responsibilities:- Expected to be an SME.- Collaborate and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Mentor junior team members to enhance their skills and knowledge.- Continuously evaluate and improve development processes to increase efficiency. Professional & Technical Skills: - Must To Have Skills: Proficiency in Memory Design.- Strong understanding of digital design principles and methodologies.- Experience with simulation and verification tools.- Familiarity with hardware description languages such as VHDL or Verilog.- Ability to troubleshoot and resolve design issues effectively. Additional Information:- The candidate should have minimum 5 years of experience in Memory Design.- This position is based at our Bengaluru office.- A 15 years full time education is required. Qualification 15 years full time education