15 Memory Design Jobs

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory

Research and analyze emerging memory technologies, to understand their characteristics, advantages, and limitations. Collaborate with system architects and product teams to define memory requirements Health insurance Provident fund Annual bonus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Roles and Responsibilities Work closely with CAD and custom macro/memory design leads to understand the design methodology and high level requirements and develop flows. Develop efficient analysis and model generation methodologies for timing and noise to achieve tight correlation. Determine key areas where automation and leading methodologies can help improve PPA. Define, innovate and implement new infrastructure capabilities that can be used to accelerate design and development, and improve user experience. Preferred qualifications MS degree in Computer Engineering; 5+ years of practical experience Strong skills in transistor level signoff tools for timing, emir, simulations, extraction and IPQA. Experience in flow development at high scale (multithreading, ml capabilities, hyperscaling, schedulers, filer hot-spot management etc.). Direct experience with efficient visualization tools to analyze results, log parsers, web views, error/warning scanners etc. Strong fundamentals in scripting languages (python, tcl, sh. others), automation, general purpose CAD infrastructure and flows. Good understanding of stdcell or memory design fundamentals. Excellent partner collaborating with design team in flow debug and support. Experience with signing off accuracy and correlation of analysis flows (compare to spice, foundry models, etc.) Tool knowledge in any of these is a plus- nanotime, xa/spectre, liberate, primelib, totem Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Basics nand , nor , latches , flops , building blocks , tools - finesim , spectre; DRAM/ SRAM is Mandatory Simulation tools: Cadence/Spectre/ primesim - Must Have Experience: 3-5 Yrs Onsite: Hyderabad

Description: Job Title: Memory Circuit Design Verification Engineer Memory Circuit Design Verification Engineer Description As a Memory Circuit Design Verification Engineer, you will work in a highly innovative, motivated, young and dynamic design team capable of verifying complete products using state of the art memory technologies. You will need to have the ability to evaluate full chip and/or block level functionality and provide solutions to help the timely delivery of a functionally correct design. Unique Opportunities Complete ownership of verification and end to end analysis of complex full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR4,LPDDR4,DDR5 and LPDDR5 that are capable of operating at high speeds of up to 6400MT/s. Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Work on cross functional tasks that can widen your skill set. Responsibilities Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Core Requirements Basic understanding of CMOS and gate level circuit designs Familiarity with SPICE Familiarity with Verilog simulations Good communication skills and ability to work well in a team Preferred Qualities Analytical capability for complex gate level circuit designs Experience in SystemVerilog, PLI coding Experience in UVM Test Bench Experience in DRAM, SRAM or other memory related fields Experience in AMS verification and co-sim Experience Level 3-7+ years Education Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required

About The Role Designs, develops, and builds digital circuits for custom blocks including SRAM, register files, memory compilers, and caches. Designs floorplans, performs circuit design, schematic entry, simulation for major blocks, and verifies functionality to optimize custom circuit for power, performance, area, timing, and yield goals. Creates block level DFT models, develops memory test tools, and improves and automates flows and methodologies to ensure streamlining of design. Collaborates cross functionally to report design progress and to collect, track, and resolve any performance and memory circuit design issues. Optimizes performance, power, and area, reduce leakage of circuits, and drive characterization of individual memory instances and memory compilers. Works with architecture and layout teams to design circuit for best functionality, robustness, and electrical capabilities. Qualifications The candidate must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum qualifications Must have a Bachelors (B.Tech) in Electronics or Masters (M.Tech) in Electrical, Microelectronics or VLSI Engineering. B.Tech with 8+ years and M. Tech with 6+ years' experience required. 6+ years' experience with scripting (Perl, tcl etc. 6+ years' experience in memory design convergence tools including formal equivalence verification, static timing methodology, electrical reliability and robustness analysis. 6+ years' experience with transistor level operation, memory bitcell design, design challenges under process variations and low power circuit techniques, Innovative architectural proposals, driving layouts and its driven decisions. Preferred Qualifications Some experience in scripting, compiler understanding and hands on experience in coding tilers. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

Position 1: Memory Layout Role: Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology. Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Compiler level integration, verification of Compiler/Custom memories. Skills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required Experience : 4 to 7Years 1. Understanding of memory architecture 2. Experience in creating basic memory layouts from scratch 3. Knowledge of memory peripheral blocks, including control blocks, I/O blocks, and row drivers The candidate should have over 4 years of experience with all of the above and more than 6 years of relevant industry experience overall. Additionally, they are seeking expertise in: 4. Knowledge of compiler issues 5. Understanding of reliability issues 6. Simulation effects 7. EMI (Electromagnetic Interference) considerations Position 2: I/O Layout Design Engineer: Roles & Responsibilities: Custom layout development on block level to Top level I/O layout for GPIO, HSTL, HCSL, VTMON, LVCMOS, DDR, LVDS etc., Need knowledge on Latchup, ESD and EM. Exposure to lower nodes N3E3nm, , 5nm etc., SKILL: LVS/DRC/ERC/Litho Checks/Antenna/ESD-LU/Density etc. Should possess good knowledge on CMOS functionality, CMOS fabrication process, foundries and challenges in latest technology nodes. Skills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required. Exp: Above 4 to 6 years Location: Electronic City, Bangalore Joining date: 2 - 4 Weeks Position 3: Memory Design Validation (Verification): We are looking for energetic and passionate memory design validation engineers for the development of memory compilers and custom macros of all types on the leading edge of process technology. Typically requires a minimum of 5+ years of relevant experience. Job Description Summary Contribute towards Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers as well as custom macros in 3nm and other cutting edge process technologies Job Description Contribute towards Memory Design Validation of all types of custom memory macros and memory compilers Perform functional verification, root cause design discrepancies, and help resolve them Perform signal integrity analysis, identify design weaknesses, and propose possible solutions to address them Perform transistor level simulations to check for any Power Up or Lock up issues and help resolve them Perform EM/IR analysis/simulations and evaluate impact on timing and internal margins Perform transistor level simulations to validate timing and internal margins, identify timing characterization holes, and help resolve them Perform various QA and validation checks to ensure accurate timing and power models Develop scripts to automate verification flow and data analysis Support silicon debugs and correlation to spice models Coordinate with memory design leads, modelling leads, and managers to define and execute on the memory validation plan

Role: Semiconductor Design Engineer Experience: 7yrs. Location: Hyderabad Interview Mode: Face to Face interview Notice: immediate to 15 days max. Package: 18LPA max Skillset: Semiconductor Designing, UVM, Verilog and System Verilog, Memory Circuit Designing Responsibilities for fast spice(Prime sim/Fine sim/spectre) based verification. Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Circuit understanding Block level circuit simulation , Analysis capability Analysis of the test modes , Basic DFT understanding Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all Emerging memory architectures and features. Participate in developing verification methodology and verification environments for advanced emerging memory products. Co-work with international colleagues on developing new verification flows to take on the challenges in emerging memory design. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.

Role & responsibilities : * Pre-Silicon Support: Simulate, analyze, and debug pre-silicon full-chip designs to ensure functional accuracy. * Test Case Development: Develop stimulus and test cases to increase the functional coverage for DRAM, SRAM, and other emerging memory technologies. Core Requirements: * Strong Communication Skills: Ability to collaborate effectively within a team. * Leadership: Guide new team members and engineers, sharing your knowledge and experience. * Analytical Expertise: Deep understanding of complex CMOS and/or gate-level circuit designs. * Proficiency in SPICE and/or Verilog simulations. Preferred candidate profile : Required Skills: * Experience with SystemVerilog, PLI coding, and UVM Test Benches. * Expertise in DRAM, SRAM, or other memory-related fields. * Familiarity with AMS verification and co-simulation is a plus. * Experience with Ethernet, SATA, Perl Scripts, and Debugging is helpful. * Knowledge of full-chip DDR, gate-level simulation, and SPICE simulation is optional but advantageous. Perks and benefits : Flexible Working Hours , Transport facility, Competitive Salary

As a Scribe CAD Staff Engineer at Micron Technology, Inc., you will be enabling and deploying layout automation concepts to enhance memory design teams productivity. You will be collaborating with multiple global teams like CAD, Memory design, and Technology development teams. Responsibilities and Tasks include, but not limited to: Work closely with memory design and technology development teams and resolve their daily challenges and develop comprehensive solutions for future. Proactively identify problem areas for improvement, propose, and develop innovative solutions. Continuously evaluate and implement new tools and technologies to improve the current automation flows. Demonstrate growth mindset and work towards submitting patent disclosures and research papers. Provide guidance and mentorship to junior members of the team. Qualifications: Advanced understanding of PDK development/validation, EDA tools and CAD flows. Develop and enable programmatically defined P-cell (Parameterized layout generator) devices for memory layout modules. Implement advanced methodologies for layout automation which can be scalable between technologies and enhance design workflow. Good understanding of programming fundamentals, as well as exposure to various programming languages including: Skill/Skill++ (Cadence), Perl, Python, Tcl. Experience of developing physical verification collaterals using SVRF. Working experience of Physical Verification flow and analyzing/debugging DRC, ERC, LVS, DFM, Antenna and rule deck issues. Good understanding of basic CMOS process manufacturing and layout design rules. Working knowledge of Linux is a must. Excellent problem-solving skills with attention to detail. Ability to work in a dynamic environment. Proficiency in working effectively with global teams and stakeholders. 8+ years of relevant experience. Education: A Bachelors or Masters degree in Computer Science, Computer Engineering, Electrical Engineering or Electronics Engineering.

About The Role : As a DFT engineer in the DFT and Manufacturing (DMT) organization, you will work to develop test automation solutions Design-for-Test (DFT) insertion and verification, test development, logic test content generation e.g. Automatic Test Pattern Generation (ATPG) and modular test content reuse. You will architect, develop and deploy CAD capabilities to address problems in this space and adapt off-the-shelf capabilities where available to build solutions. You will collaborate with an interdisciplinary team spanning chip design, product development and process technology development. The ideal candidate should exhibit the following behavioral traits: Analytical skills for problem abstraction Ability to apply scientific methods to investigate problems and to reduce ambiguity in making technical decisions. You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences. Currently, the work model is hybrid Qualifications Minimum Qualifications:The candidate must possess a BS, MS in Electronics/VLSI Design/Computer Engineering or Computer Science, with a thesis in the area of DFT, test CAD with 5+ years of experience.Candidate must have experience in following area: Logic and memory design principles, VLSI design flow and VLSI CAD algorithms. Tool, flows and methodology development for DFT insertion and test generation needs. Strong understanding of VLSI design principles and digital logic design Expertise in DFT methodologies including scan chain design, ATPG, BIST, and boundary scan Proficiency with EDA tools like Synopsys, Mentor Graphics Tessent, Cadence. DFT scan architecture and execution experience. Programming skills with one or more of the high level languages e.g. C++/C/TCL/Perl/Python etc. Ability to work independently and collaborate effectively with cross-functional teams Theoretical knowledge in computer science, including algorithms and data structures. Standard software engineering practices for version control, configuration management, debugging and validation. Preferred Qualifications: Detailed understanding of design-for-test (DFT) principles and knowledge of software design patterns and programming paradigms Linux OS features and scripting languages Inside this Business Group Product Enablement Solutions Group (PESG) is one of the key pillars, enabling Intel product design teams get to market faster with winning leadership products. Other Locations IN, Hyderabad Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel'™s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

Responsibilities As a Performance Analyst for storage and networking I/O subsystems, you’ll be running workloads that simulate real client operations, with the goal of stressing these subsystems. Across different operating systems, machine types, adapters and fabrics, you’ll develop experimental plans to ensure that our I/O performance meets clients’ requirements, and, when it doesn’t, you’ll dive in to the stack to find a solution. You can expect to partner with hardware engineers and software developers at every level of the stack from the chip and the bus through adapter vendors to the operating system kernel right through to the hypervisor and Kubernetes-based technologies that power the hybrid cloud. You’ll also get great insights in to the workloads that enterprises run, from databases through AI applications. This is a great role for anyone who loves solving problems and is fascinated by how bits move within and between computers. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Professional Expertise o Demonstrated experience with modern IO technologies such as TCP/IP, SSL, NVMe, Fiberchannel o Demonstrated understanding of micro-architecture design, memory layout, multi-threading, I/O buses o Solid understanding of operating system implementation, memory management and process scheduling o Experience with C/C++ programming o Experience with deploying, tuning and profiling applications running in Kubernetes environments o Experience deploying applications on at least one public cloud o Extensive experience with automation frameworks such as Ansible or Python o Ability to work in a team and network with people outside of the team and effectively communicate in written and verbal presentations is essential. Technical Expertise o 5+ years of experience with enterprise-class I/O technologies spanning both storage and networking o Demonstrated experience in microarchitecture design and implementation o 3+ years with C/C++ or other systems-level programming o 5+ years with a modern automation framework, Ansible preferred o 3+ years deploying, tuning and managing complex workloads in a public cloud o Passion for continuous improvement in building knowledge base both technically and professionally Minimum BS OR MS degree in Computer Engineering, electrical engineering, computer science or a related technical discipline or equivalent experience. Preferred technical and professional experience o Experience deploying hybrid cloud applications (that is, an application with an on-premise and a public cloud component) o Demonstrated application of machine-learning or AI technologies to data analysis o Agile/ Scrum methodology experience

About The Role : ou will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for leading the design analysis and methodologies of the different types of memory blocks. Your responsibilities will include but not limited to: 1. Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area.2. In depth understanding of different memory design concepts ((SRAM/RF/ROM).3. Expertise in Static timing analysis concepts.4. Close work with Layout and Floor planning teams.5. Back end design implementation of new features.6. Expertise in Memory post silicon analysis. 7. Good understanding of statistical variation. 8. Planning, implementing and analyzing clock distribution from Full Chip level to leaf level for CPU cores. Qualifications You must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with atleast 10 years of experience. Technical Expertise in synthesis, P and R tools preferred. Preferred Qualifications: 1. Digital Design Experience, with High Speed, Low Power.2. Familiarity with Verilog/VHDL.3. Tcl, Perl, Python scripting. 4. Good understanding of spice simulations and analysis 5.Custom circuit design, IO design, full chip clocking6. Strong verbal and written communication skills. Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core „¢, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.

Job Description: Memory design engineer. Responsibilities: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA. Required Skills and Experience : We Prefer graduate or postgraduate from a University or Engineering School, in Electronic Engineering or equivalent Engineering Degree. You have some understanding of computer architecture and concepts. We expect you to have basic understanding of CMOS Transistors, their behaviors. We expect some basic understanding of high speed/low power CMOS circuit design, clocking scheme, Static and complex logic circuits. Understanding of Power versus Performance versus Area trade-offs in typical CMOS design. You have an engineering demeanor and Passion for Circuit design. Expected to have good interpersonal skills. Minimum 5Yrs of experience in SRAM / memory design Margin, Char and its related quality checks. Nice To Have Skills and Experience : You know basic scripting languages, e.g. Perl/TCL/Python. Some Experience of working on Cadence or Synopsys flows. Experience with Circuit Simulation and Optimization of standard cells.