Lead Memory Design Engineer

Role Overview: As a Lead Memory Design Engineer, you will be responsible for driving the architecture, design, and development of advanced memory IPs including SRAMs, ROMs, CAMs, and Register Files. Your role will involve leading a team of designers, collaborating with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Key Responsibilities: - Define architecture and design specifications for custom memory IPs. - Optimize circuits such as memory cell arrays, sense amplifiers, and decoders. - Lead schematic-level design and simulation. - Collaborate with layout and verification teams. - Guide post-layout activities. - Ensure designs meet requirements for DFM and reliability. - Contribute to methodology development. - Support silicon bring-up. - Provide technical leadership to junior engineers. Qualification Required: - B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering. - 8+ years of experience in full-custom memory design. - Solid understanding of CMOS analog/digital circuit design principles. - Expertise in circuit simulation tools. - Experience with advanced nodes. - Hands-on experience with variation analysis, IR drop, and EM checks. - Strong analytical, communication, and leadership skills. Additional Details: Preferred qualifications include experience in memory compiler design, knowledge of low-power memory design techniques, experience with ECC and redundancy strategies, familiarity with ISO 26262/Safety compliance, and scripting knowledge for automation of design and simulation flows. If you are interested in this opportunity, please share your CV with Sharmila.b@acldigital.com.,