11 Register Files Jobs

As a Memory Layout Lead at Best-in-Class Semiconductor Memory IPs, you will be responsible for driving the physical design and delivery of high-performance, low-power, and high-density semiconductor memory IPs including SRAM, ROM, register files, CAMs, and more. Your main focus will be on owning the complete layout strategy, from bitcell integration to periphery circuits, ensuring best-in-class PPA (performance, power, area), and yield while adhering to strict foundry rules. Key Responsibilities: - Lead end-to-end layout design and floorplanning for advanced-node memory IPs. - Deliver DRC/LVS/DFM-clean GDS with robust EM/IR reliability sign-off. - Collaborate with circuit, CAD, and SoC integ...

As an experienced and highly motivated Lead Memory Design Engineer at our company, your role will involve driving the architecture, design, and development of advanced memory IPs such as SRAMs, ROMs, CAMs, and Register Files. You will be leading a team of designers, interacting with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Key Responsibilities: - Define architecture and design specifications for custom memory IPs or memory compilers. - Design and optimize circuits such as: Memory cell arrays, sense amplifiers, precharge, write drivers, decoders, control logic. - Lead the schematic-level design and s...

As an experienced "Memory Layout" Engineer with 10+ years of experience, you will be responsible for designing memory layout for blocks such as Caches, CAMs, Register files, multiport register Files, Compilers, and analog layouts like PLLs, TX, RX, amplifiers. Your role will require hands-on work, leadership abilities, and a growth mindset. Effective communication skills are essential for collaborating with cross-site designers. You should have practical experience with technologies like Finfets, GAA, and working with technology nodes below 7nm. Proficiency in debugging and resolving issues related to LVS, DRC, Antenna, DFM, EM, IR, and Methodology check is required. Additionally, you will b...

You would be responsible for leading the implementation of the architecture and design of memory technologies such as SRAM, Register Files, ROM generators, etc. Your role would involve combining knowledge across various domains including AI, compilers, computer architecture, analog circuits, and memories. Key Responsibilities: - Have a fundamental understanding of bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention, etc.) - Possess expertise in process variability and circuit reliability issues affecting power, speed, area, and yield - Demonstrate a strong understanding of custom circuit design and layout in finFET-based CMOS technologies - Expertise in c...

As the leader in implementing the architecture and design of memory technologies at Ceremorphic AI hardware, your role will involve combining knowledge across various domains such as AI, compilers, computer architecture, analog circuits, and memories. Your responsibilities will include: - Leading the implementation of memory technologies like SRAM, Register Files, ROM generators, etc. - Demonstrating fundamental know-how of bit cell and its characteristics including SNM, WM, Cell current, Standby current, data retention, etc. - Showcasing expertise in process variability and circuit reliability issues affecting power, speed, area, and yield - Having a strong understanding of custom circuit d...

As a Memory Layout Lead at our company, you will play a crucial role in driving the physical design and delivery of high-performance, low-power, and high-density semiconductor memory IPs including SRAM, ROM, register files, CAMs, and more. Your main responsibility will be to lead the end-to-end layout design and floorplanning for advanced-node memory IPs. Additionally, you will collaborate with circuit, CAD, and SoC integration teams to ensure optimal implementation. Your innovative layout techniques will be essential in achieving competitive density and performance targets. You will also be responsible for providing comprehensive IP deliverables such as GDSII, LEF, Liberty (.lib), Verilog m...

Role Overview: As a Lead Memory Design Engineer, you will be responsible for driving the architecture, design, and development of advanced memory IPs including SRAMs, ROMs, CAMs, and Register Files. Your role will involve leading a team of designers, collaborating with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Key Responsibilities: - Define architecture and design specifications for custom memory IPs. - Optimize circuits such as memory cell arrays, sense amplifiers, and decoders. - Lead schematic-level design and simulation. - Collaborate with layout and verification teams. - Guide post-layout activi...

As an experienced candidate with 2-5 years of experience, your role will primarily involve transistor level circuit design tasks such as critical path modeling. You will be responsible for designing and qualifying memory components like bit cells, sense amplifiers, and read/write circuitry. Additionally, you will be involved in the characterization and qualification of various memory components such as SRAM, RAMS, Register Files, and cad view generations. Qualifications Required: - 2-5 years of relevant experience in transistor level circuit design - Proficiency in critical path modeling - Experience in designing and qualifying memory components - Knowledge of characterization and qualificat...

As the Lead for the implementation of Ceremorphic AI hardware architecture and design of memory technologies, you will play a crucial role in integrating knowledge from various fields like AI, compilers, computer architecture, analog circuits, and memories. Your responsibilities will revolve around designing memory technologies including SRAM, Register Files, ROM generators, and other related components. Your key requirements for this position include a fundamental understanding of bit cell characteristics such as SNM, WM, Cell current, Standby current, data retention, among others. You should also possess expertise in dealing with process variability and circuit reliability issues that impa...

Company Description SILCOSYS Solutions collaborates with clients to develop next-generation flagship products, including mobile devices, routers, consumer goods, storage solutions, microprocessors, and graphics processors. We are known for pioneering cutting-edge technologies that are both pivotal and rare in the industry. With expertise in crafting intricate SoCs, SILCOSYS Solutions also boasts one of the industry&aposs most robust analog/mixed signal and software design teams. Position: Senior Memory Layout Engineer Experience: 6 - 15 Years Location: Bangalore Notice Period: 0 - 15 Days Role Description Looking for experts in memory compilers with solid hands-on experience in SRAM, ROM, TC...

As a Lead Memory Design Engineer, you will be responsible for driving the architecture, design, and development of advanced memory IPs including SRAMs, ROMs, CAMs, and Register Files. Your role will involve leading a team of designers, collaborating with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Your key responsibilities will include defining architecture and design specifications for custom memory IPs, optimizing circuits such as memory cell arrays, sense amplifiers, and decoders, leading schematic-level design and simulation, collaborating with layout and verification teams, guiding post-layout act...