Principal Engr-Chip Design Expert – Semiconductor

Principal Engr-Chip Design Expert – Semiconductor

Jobcode-SS-IN-00-380873

Location: Bangalore, India

Experience: 15+ years (Principal/SME level)

About the Role

We are looking for a seasoned Chip Design Expert to lead cutting-edge semiconductor design initiatives. The ideal candidate will have deep expertise in SoC architecture, RTL design, physical implementation, and verification, with proven experience in advanced technology nodes (7nm/5nm/3nm). This role involves strategic leadership of complex chip design programs from concept to tape-out, ensuring optimal Power, Performance, and Area (PPA) targets while driving innovation and best practices across the organization.

Key Responsibilities

Architecture & Design Leadership

• Define chip-level architecture and microarchitecture for complex SoCs and custom ASICs.

• Collaborate with system architects and IP teams for seamless subsystem integration.

• Drive low-power design strategies, clock/power gating, and hierarchical design methodologies.

Physical Design & Implementation

• Lead floorplanning, synthesis, place & route (P&R), CTS, and timing closure for large-scale designs.

• Ensure robust Static Timing Analysis (STA) across multiple corners/modes.

• Optimize for power integrity, signal integrity, thermal constraints, and reliability.

Verification & Sign-off

• Oversee DFT strategies (Scan, MBIST, LBIST) and ensure compliance with DRC, LVS, ESD requirements.

• Drive formal verification, CDC analysis, lint checks, and sign-off processes.

Program & Team Leadership

• Act as a technical authority and mentor for design teams, fostering skill development.

• Manage project schedules, deliverables, and quality metrics for successful tape-outs.

• Collaborate with cross-functional teams including packaging, test, and manufacturing.

Innovation & Methodology Development

• Champion AI/ML-driven design automation, advanced EDA flows, and efficiency improvements.

• Contribute to continuous improvement of design methodologies, IP reuse strategies, and best practices.

Qualifications-Master’s/Bachelor’s in Electrical Engineering, Electronics, or VLSI Design.

Experience:

• 15+ years in semiconductor chip design (SoC, ASIC, or custom ICs).

• Proven track record of multiple successful tape-outs in advanced technology nodes.

• Strong leadership in architecture definition, RTL design, and physical implementation.

Technical Expertise:

• Proficiency in Verilog/SystemVerilog, scripting (TCL, Python, Perl).

• Hands-on experience with EDA tools (Cadence, Synopsys, Mentor Graphics).

• Expertise in timing closure, power optimization, and signal integrity analysis.

Soft Skills:

• Exceptional leadership, communication, and stakeholder management abilities.

• Ability to drive strategic decisions and influence technology roadmaps.

Preferred Skills

• Experience with AMBA protocols, DDR4/LPDDR, PCIe, SerDes.

• Familiarity with Network-on-Chip (NoC) and coherent interconnects.

• Exposure to chiplet architectures, advanced packaging (2.5D/3D).

• Knowledge of functional safety (ISO 26262) and security in hardware design.

Pl share the cv with Job code and position applied for on suryasingh@indusitc.com and call me if any queries on +91-9811107008