Physical Design Engineer – STA & Synthesis , AMD

5 - 10 years

15 - 25 Lacs

Posted:7 hours ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

Key Responsibilities

  • Perform RTL/Netlist synthesis and support Synthesis to GDSII flow
  • Own Static Timing Analysis (STA) across all design stages
  • Create, validate, and maintain SDC constraints
  • Drive timing closure by analyzing setup/hold, clock, and path-related issues
  • Work closely with PnR teams on timing fixes and ECOs
  • Support and analyze Clock Tree Synthesis (CTS) impacts on timing
  • Perform timing sign-off including corner, mode, and scenario analysis
  • Debug complex timing issues and provide actionable solutions
  • Collaborate with RTL, DV, and PD teams for seamless execution
  • Support tape-out activities and last-minute timing changes .

Key Expertise / Skills

  • Strong hands-on experience in STA and Synthesis
  • Expertise in SDC constraints development and validation
  • Deep understanding of timing analysis and timing fixes
  • Experience with CTS and post-CTS timing analysis
  • Knowledge of ECO flows and timing optimization techniques
  • Proficiency with industry-standard EDA tools (Synopsys/Cadence)
  • Experience with advanced technology nodes is a plus .

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