14 Gdsii Jobs

You have been selected for a role as a Lead in SoC Physical Design at a dynamic company, 7Rays Semiconductor Private Ltd. With over 3 years of relevant experience, your expertise in SoC Physical design across multiple technology nodes, including 5nm for TSMC & Other foundries, will be highly valuable. Your responsibilities will include: - Demonstrating excellent hands-on P&R skills with expert knowledge in ICC/Innovus - Utilizing expert knowledge in all aspects of PD from Synthesis to GDSII - Demonstrating a strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure - Experience at taping out multiple chips, especially...

As a Physical Design Engineer/Lead, with 5 to 15 years of hands-on experience, your role will involve the following key responsibilities: - Implementing block-level Physical Design from RTL to GDSII or Netlist to GDSII. - Conducting block-level Physical Signoff. - Ensuring block-level Timing Signoff and ECO generation. - Performing block-level Power Signoff. - Demonstrating proficiency in Automation tools such as Perl, Tcl, Awk, and Python. - Providing technical guidance to junior engineers and leading a team of 4-6 engineers. - Leading small project teams effectively. - Utilizing strong communication skills to be the single point of contact for clients. In this role, remote work is not avai...

As a Physical Design Engineer at UST, you will be responsible for the following: - Expected to be very good in Basic Fundamentals of C-MOS technology - Able to handle RTL/Netlist to GDSII independently at block level and should have done multiple tape outs (Low power implementation is preferred) - Hands-on experience of working on Lower technology nodes like 5nm, 7nm, 10nm, 14nm, 16nm, 28nm etc. - Proficient in floor planning, placement optimizations, clock tree synthesis (CTS), and routing - Experienced in block/top level signoff Static Timing Analysis (STA), physical verification (DRC/LVS/ERC/antenna) checks, and other reliability checks (IR/EM/Xtalk) - Expertise in industry standard EDA t...

As a Memory Layout Lead at our company, you will play a crucial role in driving the physical design and delivery of high-performance, low-power, and high-density semiconductor memory IPs including SRAM, ROM, register files, CAMs, and more. Your main responsibility will be to lead the end-to-end layout design and floorplanning for advanced-node memory IPs. Additionally, you will collaborate with circuit, CAD, and SoC integration teams to ensure optimal implementation. Your innovative layout techniques will be essential in achieving competitive density and performance targets. You will also be responsible for providing comprehensive IP deliverables such as GDSII, LEF, Liberty (.lib), Verilog m...

You have a job opportunity for the Manager / Senior Role Physical Design Engineer position in Hyderabad. Your primary responsibilities will include: - Performing IP/Block level PnR activities from Netlist to GDS-II - Demonstrating good knowledge of all PnR activities such as Floor-planning, Placement, CTS, Routing, Timing closure (STA), and signoff checks like FEV, VCLP, EMIR, and PV - Executing all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file - Handling signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff - Having knowledge of high performance and low power implementation methods (preferred) - Expertise in ICC2/Fusion Compil...

About SiFive SiFive, the pioneers who introduced RISC-V to the world, are revolutionizing the future of computing by harnessing the boundless potential of RISC-V for the most high-performance and data-intensive applications globally. SiFive's unparalleled computing platforms continue to empower leading technology firms worldwide to innovate, optimize, and deliver cutting-edge solutions across various chip design segments, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer electronics. With SiFive, the future of RISC-V knows no bounds. At SiFive, we are eager to engage with talented individuals who share our fervor for driving innovation and mak...

As a Senior ASIC Physical Design Engineer at Synopsys, you will play a crucial role in shaping the future of the semiconductor industry by driving innovations in IC design and physical implementation. Your expertise in high-performance digital design, low-power design, and high-speed clock design will be instrumental in developing cutting-edge solutions for creating high-performance silicon chips. You will collaborate with cross-functional teams to streamline the physical design process, enhance product offerings, and exceed customer expectations. Your responsibilities will include floor planning, developing timing constraints, physical synthesis, clock tree optimization, routing and extract...

As a Physical Design Engineer/Lead based in Noida, Ahmedabad, Bangalore, or Hyderabad, you will be responsible for leveraging your 5 to 15 years of hands-on experience in various aspects of physical design implementation. Your key responsibilities will include executing block-level physical design implementation from RTL to GDSII or Netlist to GDSII, ensuring block-level physical signoff, conducting block-level timing signoff and ECO generation, and overseeing block-level power signoff. Your role will also entail demonstrating proficiency in automation using tools such as Perl, Tcl, Awk, or Python. Additionally, you will be expected to offer technical guidance to a team of 4-6 junior enginee...

You should have at least 3+ years of relevant experience leading SoC Physical design projects across multiple technology nodes, including 5nm for TSMC and other foundries. Your expertise should include hands-on Place and Route (P&R) skills with in-depth knowledge of ICC/Innovus. You must possess expert knowledge in all phases of Physical Design (PD) from Synthesis to GDSII, with a solid background in Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Experience in taping out multiple chips and strong familiarity with the top level at the latest technology nodes will be beneficial. Collaboration with CAD, Met...

The Sr. Staff Physical Design Engineer position at Lattice Semiconductor in Pune, India offers a dynamic opportunity to join the HW design team focused on IP design and full chip integration. As part of a worldwide community of engineers and specialists, you will have the chance to contribute, learn, innovate, and grow within this fast-paced and ambitious organization. Key responsibilities for this role include implementing and leading the RTL to GDSII flow for complex designs, working on various aspects of physical design such as place & route, CTS, routing, floorplanning, powerplanning, timing, and physical signoff. The ideal candidate will have experience in physical design signoff checks...

We dont need superheroes, just super minds! We bring together a dynamic team of individuals with a B.Tech/M.tech or equivalent experience in Computer Science or Electronics Engineering with shown experience Strong programming knowledge in C/C++ and strong object oriented design skills. Good algorithm and data-structure design skills with theoretical background in analysis of algorithms. Prior experience in geometric data processing and knowledge of computational geometry algorithms. Should have working knowledge of distributed computing environment. Adept at using one or more software development methodologies such as Agile. Technical Skills required (Desirable) Experience in developing EDA ...

Job Requirements: Technical Skills required (Must have): Strong programming knowledge in C/C++ and strong object oriented design skills. Good algorithm and data-structure design skills with theoretical background in analysis of algorithms. Prior experience in geometric data processing and knowledge of computational geometry algorithms. Should have working knowledge of distributed computing environment. Adept at using one or more software development methodologies such as Agile. Technical Skills required (Desirable): Experience in developing EDA applications in the post layout domain such as Mask Data Preparation and Modelling. Experience in using model calibration tools or aware of model cal...

Job description This is your role Design and implement algorithmic solutions within the mask data preparation and lithography systems modeling domains. Chip in to the continuous enhancement of Siemens EDAs product lines through design reviews and technical innovations. Collaborate effectively with multi-functional teams across different geographies and cultures. Engage with co-workers and collaborators to improve product quality and drive technical excellence. Provide technical consultation and drive improvements in product functionality. We dont need superheroes, just super minds! We bring together a dynamic team of individuals with a B.E./B.Tech./M.Tech. in Computer Science, Electrical Eng...

You should have at least 3+ years of relevant experience in SoC Physical design, with a focus on multiple technology nodes including 5nm for TSMC and other foundries. Your expertise should include hands-on P&R skills, particularly in ICC/Innovus. You must possess expert knowledge in all aspects of Physical Design (PD) from Synthesis to GDSII, with a strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Experience in taping out multiple chips and working at the top level in the latest technology nodes will be highly beneficial. Collaboration with CAD, Methodology & IP teams for PD implementation is critical, requi...