9 Gdsii Jobs

About SiFive SiFive, the pioneers who introduced RISC-V to the world, are revolutionizing the future of computing by harnessing the boundless potential of RISC-V for the most high-performance and data-intensive applications globally. SiFive's unparalleled computing platforms continue to empower leading technology firms worldwide to innovate, optimize, and deliver cutting-edge solutions across various chip design segments, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer electronics. With SiFive, the future of RISC-V knows no bounds. At SiFive, we are eager to engage with talented individuals who share our fervor for driving innovation and making a difference in the world. Our culture of constant innovation and enduring success is attributed to our remarkable teams of immensely talented individuals who collaborate and support one another to generate truly revolutionary ideas and solutions. These solutions are poised to significantly impact people's lives, gradually making the world a better place, one processor at a time. Are you prepared to join us on this journey To delve deeper into SiFive's remarkable achievements and discover why we have been honored with the GSAs prestigious Most Respected Private Company Award (for the fourth time!), explore our website and Glassdoor pages. Responsibilities - Lead the implementation and drive uARCH optimization of SiFive's high-performance Out of Order RISC-V CPUs from RTL to GDSII. - Achieve ambitious performance, power, and area (PPA) goals at the block and/or CPU subsystem level. - Work closely with the microarchitecture and RTL teams to identify and optimize PPA trade-offs, including pathfinding for the next generation of CPUs. - Develop timing and area models for configurability to ensure predictable execution. - Contribute to the development of physical implementation flow and enhance Foundation IP (standard cell, SRAM) to achieve best-in-class automation and PPA. Requirements - Possess 12+ years of physical implementation experience with multiple tape-outs across various technologies; Strong preference for experience in CPU implementation and advanced process nodes (3nm and below). - Proficient in Synopsys/Cadence Silicon Implementation tools. - Expertise in aggressive PPA optimization through physical design techniques. - Familiarity with out-of-order core uArch and logic design is highly preferred. - Prior experience in leading/managing teams is advantageous. - Detail-oriented with a focus on high-quality design. - Ability to collaborate effectively with others and a belief in the collaborative nature of engineering. - Hold a Bachelor's or Master's degree in Electrical Engineering or Computer Engineering. Additional Information This role necessitates successful background and reference checks, along with satisfactory proof of your eligibility to work in India. Any employment offer for this position is subject to the Company verifying your authorization for access to export-controlled technology under relevant export control laws or, if not already authorized, our ability to obtain any necessary export license(s) or approvals successfully. SiFive upholds equal employment opportunities. We value diversity and are dedicated to fostering an inclusive environment for all employees.,

As a Senior ASIC Physical Design Engineer at Synopsys, you will play a crucial role in shaping the future of the semiconductor industry by driving innovations in IC design and physical implementation. Your expertise in high-performance digital design, low-power design, and high-speed clock design will be instrumental in developing cutting-edge solutions for creating high-performance silicon chips. You will collaborate with cross-functional teams to streamline the physical design process, enhance product offerings, and exceed customer expectations. Your responsibilities will include floor planning, developing timing constraints, physical synthesis, clock tree optimization, routing and extraction management, timing closure, signal integrity analysis, physical verification, and design for manufacturability (DFM) checks. By contributing to the development and enhancement of physical design flows for advanced technology nodes, you will drive innovation and improve efficiency in the physical design process. To excel in this role, you should have a solid understanding of IC design principles and physical implementation, experience with the full design cycle from RTL to GDSII, proficiency in deep sub-micron design flows, and hands-on experience with complex design projects and successful tape-outs. You should be a detail-oriented professional with strong analytical and problem-solving skills, an effective communicator, a proactive learner, a dedicated team player, and a creative thinker who can contribute to innovative solutions and improvements. You will be part of a dynamic and innovative team at Synopsys, dedicated to pushing the boundaries of IC design and physical implementation. Together, you will work collaboratively to address complex challenges and deliver exceptional results, driving the technological advancements that shape the future of the semiconductor industry. Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process. Join us at Synopsys to transform the future through continuous technological innovation and contribute to the growth of our innovative group.,

As a Physical Design Engineer/Lead based in Noida, Ahmedabad, Bangalore, or Hyderabad, you will be responsible for leveraging your 5 to 15 years of hands-on experience in various aspects of physical design implementation. Your key responsibilities will include executing block-level physical design implementation from RTL to GDSII or Netlist to GDSII, ensuring block-level physical signoff, conducting block-level timing signoff and ECO generation, and overseeing block-level power signoff. Your role will also entail demonstrating proficiency in automation using tools such as Perl, Tcl, Awk, or Python. Additionally, you will be expected to offer technical guidance to a team of 4-6 junior engineers and have experience leading small project teams. Strong communication skills are essential as you will serve as the primary point of contact for clients. Please note that this role does not support work from home or remote work arrangements.,

You should have at least 3+ years of relevant experience leading SoC Physical design projects across multiple technology nodes, including 5nm for TSMC and other foundries. Your expertise should include hands-on Place and Route (P&R) skills with in-depth knowledge of ICC/Innovus. You must possess expert knowledge in all phases of Physical Design (PD) from Synthesis to GDSII, with a solid background in Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Experience in taping out multiple chips and strong familiarity with the top level at the latest technology nodes will be beneficial. Collaboration with CAD, Methodology & IP teams is a crucial aspect of PD implementation, necessitating regular sync-ups for deliveries. You should have significant knowledge and preferably hands-on experience in SoC Static Timing Analysis (STA), Power analysis, Physical Verification, and other sign-off processes. Strong problem-solving abilities, a proactive approach, hard work ethic, and excellent interpersonal skills are essential for this role. A Bachelor's Degree in Electrical, Electronics, or Computer Engineering is required. About Company: 7Rays Semiconductor Private Ltd. provides end-to-end custom SoC design solutions, encompassing SoC Architecture, RTL design, Design verification, DFT, Physical Design, and Analog design. Our focus is on serving top semiconductor and system companies to facilitate the design of their complex SoCs. We prioritize building effective partnerships with our clients to deliver high-quality, tailored solutions. With a dedicated engineering team and a proven history of successful project execution, we are dedicated to excellence and innovation in SoC Design, Development, and deployment of customer products.,

The Sr. Staff Physical Design Engineer position at Lattice Semiconductor in Pune, India offers a dynamic opportunity to join the HW design team focused on IP design and full chip integration. As part of a worldwide community of engineers and specialists, you will have the chance to contribute, learn, innovate, and grow within this fast-paced and ambitious organization. Key responsibilities for this role include implementing and leading the RTL to GDSII flow for complex designs, working on various aspects of physical design such as place & route, CTS, routing, floorplanning, powerplanning, timing, and physical signoff. The ideal candidate will have experience in physical design signoff checks, drive efficiency and quality in physical design flow and methodology, collaborate with internal and external teams, and possess scripting knowledge to enhance design efficiency. Additionally, the successful candidate will play a vital role in FPGA design efforts, drive physical design closure of key ASIC blocks & full chip, maintain design quality through quality checks and signoff, develop strong relationships with global teams, mentor colleagues, and may require occasional travel. Requirements for this role include a BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science or equivalent, along with 12+ years of experience in driving physical design activities for ASIC blocks and full chips. Candidates must have multiple tapeout experience and proficiency in industry-standard physical design tools. The ideal candidate should be an independent problem solver, capable of collaborating with diverse groups across different sites and time zones. Lattice Semiconductor values its employees as the cornerstone of its success and offers a comprehensive compensation and benefits program to attract and retain top talent in the industry. As an international developer of low-cost, low-power programmable design solutions, Lattice is committed to customer success and a culture of innovation and achievement. If you thrive in a results-oriented environment, seek individual success within a team-first organization, and are ready to contribute to a collaborative and innovative atmosphere, Lattice Semiconductor may be the perfect fit for you. Feel the energy at Lattice.,

We dont need superheroes, just super minds! We bring together a dynamic team of individuals with a B.Tech/M.tech or equivalent experience in Computer Science or Electronics Engineering with shown experience Strong programming knowledge in C/C++ and strong object oriented design skills. Good algorithm and data-structure design skills with theoretical background in analysis of algorithms. Prior experience in geometric data processing and knowledge of computational geometry algorithms. Should have working knowledge of distributed computing environment. Adept at using one or more software development methodologies such as Agile. Technical Skills required (Desirable) Experience in developing EDA applications in the post layout domain such as Mask Data Preparation and Modelling. Experience in using model calibration tools or aware of model calibration process in semiconductor manufacturing industry. Knowledge of computational mathematics concepts like numerical methods including non-linear optimization etc. Experience in processing large layout/mask data in formats such as OASIS, GDSII, MEBES, VSB etc. Experience in parallel and distributed computing, with working knowledge of tools such as Sun Grid Engine, LSF, etc. Good understanding of configuration management tools such as CVS. Working knowledge of Scrum, experience with defect tracking tools such as JIRA.

Job Requirements: Technical Skills required (Must have): Strong programming knowledge in C/C++ and strong object oriented design skills. Good algorithm and data-structure design skills with theoretical background in analysis of algorithms. Prior experience in geometric data processing and knowledge of computational geometry algorithms. Should have working knowledge of distributed computing environment. Adept at using one or more software development methodologies such as Agile. Technical Skills required (Desirable): Experience in developing EDA applications in the post layout domain such as Mask Data Preparation and Modelling. Experience in using model calibration tools or aware of model calibration process in semiconductor manufacturing industry. Knowledge of computational mathematics concepts like numerical methods including non-linear optimization etc Experience in processing large layout/mask data in formats such as OASIS, GDSII, MEBES, VSB etc Experience in parallel and distributed computing, with working knowledge of tools such as Sun Grid Engine, LSF, etc Good understanding of configuration management tools such as CVS. Working knowledge of Scrum, experience with defect tracking tools such as JIRA. General Skills: Positive attitude, Good presentation and communication skills, Self-driven and self-motivating, Able to provide consultation on technical issues, Relationship building capabilities, Team player. Academic Qualifications: BE/MTech in Computer Science or Electronics from reputed institutes like IITs.

Job description This is your role Design and implement algorithmic solutions within the mask data preparation and lithography systems modeling domains. Chip in to the continuous enhancement of Siemens EDAs product lines through design reviews and technical innovations. Collaborate effectively with multi-functional teams across different geographies and cultures. Engage with co-workers and collaborators to improve product quality and drive technical excellence. Provide technical consultation and drive improvements in product functionality. We dont need superheroes, just super minds! We bring together a dynamic team of individuals with a B.E./B.Tech./M.Tech. in Computer Science, Electrical Engineering, Electronics & Communication, Instrumentation & Control, or related fields with shown ability Strong programming skills in C/C++ with deep expertise in object-oriented design. Solid understanding of algorithms and data structures , with a strong theoretical background in algorithm analysis. Experience with geometric data processing and computational geometry algorithms . Proficiency in distributed computing environments . Familiarity with modern software development methodologies such as Agile . Desirable Technical Skills: Experience in developing EDA applications in the post-layout domain (e.g., Mask Data Preparation, Modeling).Knowledge of model calibration tools or an understanding of the model calibration process in semiconductor manufacturing. A solid base in computational mathematics and numerical methods (including non-linear optimization). Experience in handling large layout/mask data in formats like OASIS, GDSII, MEBES, VSB .Familiarity with parallel and distributed computing tools (e.g., Sun Grid Engine, LSF ). Experience with configuration management tools such as CVS .Knowledge of Scrum methodologies and defect tracking tools like JIRA . We value individuals with a positive attitude, strong communication and presentation skills, and a dedicated, motivated approach. We seek someone who can provide technical consultation on complex issues, form relationships, and collaborate effectively as a great teammate across teams with varied strengths and cultures! We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status

You should have at least 3+ years of relevant experience in SoC Physical design, with a focus on multiple technology nodes including 5nm for TSMC and other foundries. Your expertise should include hands-on P&R skills, particularly in ICC/Innovus. You must possess expert knowledge in all aspects of Physical Design (PD) from Synthesis to GDSII, with a strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Experience in taping out multiple chips and working at the top level in the latest technology nodes will be highly beneficial. Collaboration with CAD, Methodology & IP teams for PD implementation is critical, requiring regular sync-ups for deliveries. You should have significant knowledge, and preferably hands-on experience, in SoC STA, Power, Physical Verification, and other sign-off processes. Problem-solving capabilities, proactive attitude, hardworking nature, and strong interpersonal skills are essential for this role. A Bachelor's Degree in Electrical, Electronics, or Computer Engineering is required for this position. About Company: 7Rays Semiconductor Private Ltd. provides end-to-end custom SoC design solutions, including SoC Architecture, RTL design, Design verification, DFT, Physical Design & Analog design. The company focuses on offering services to top semiconductor and system companies to assist them in designing complex SoCs. The company believes in building effective partnerships with clients to deliver high-quality solutions tailored to their needs. With a dedicated engineering team and a successful track record in project execution, the company is committed to excellence and innovation in SoC Design, Development, and deployment of customers" products.,