1109 Dft Jobs - Page 19

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Contribute/Lead towards Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers as well as custom macros in 2nm and other cutting edge process technologies Job Description Contribute/Lead towards Memory Design Validation of all types of custom memory macros and memory compilers Perform functional verification, root cause design discrepancies, and help resolve them Perform signal integrity analysis, identify design weaknesses, and propose possible solutions to address them Perform transistor level simulations to check for any Power Up or Lock up issues and help resolve them Perform EM/IR analysis/simulations and evaluate impact on timing and internal margins Perform transistor level simulations to validate timing and internal margins, identify timing characterization holes, and help resolve them Perform various QA and validation checks to ensure accurate timing and power models Develop scripts to automate verification flow and data analysis Support silicon debugs and correlation to spice models Coordinate with memory design leads, modelling leads, and managers to define and execute on the memory validation plan Skill Sets Strong expertise in development of memory macros of all types and architectures Strong understanding of transistor level circuit behavior and analysis Good understanding of the layout and their related challenges in sub nanometer process technologies Good understanding of signal integrity, EM/IR, and reliability analysis Good understanding of memory behavioral and physical models Good understanding of DFT Schemes and chip level integration Proficient in running transistor level simulators, writing automation scripts, and are tools savvy Complete hands on experience in using Cadence schematic/layout editor tools Complete hands on experience with transistor level simulators, Monte Carlo variation analysis, waveform viewer tools such as; HSPICE, HSIM, XA, FineSim, XARA, nWave, waveform viewer, etc.. Experience in Skill/Perl/Python Scripting is a strong plus Good communication, interpersonal, and leadership skills Good debugging skills, problem solving and logical reasoning skills Motivated, self-driven and good at multi-tasking .

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Contribute/Lead towards Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers as well as custom macros in 2nm and other cutting edge process technologies Job Description Contribute/Lead towards Memory Design Validation of all types of custom memory macros and memory compilers Perform functional verification, root cause design discrepancies, and help resolve them Perform signal integrity analysis, identify design weaknesses, and propose possible solutions to address them Perform transistor level simulations to check for any Power Up or Lock up issues and help resolve them Perform EM/IR analysis/simulations and evaluate impact on timing and internal margins Perform transistor level simulations to validate timing and internal margins, identify timing characterization holes, and help resolve them Perform various QA and validation checks to ensure accurate timing and power models Develop scripts to automate verification flow and data analysis Support silicon debugs and correlation to spice models Coordinate with memory design leads, modelling leads, and managers to define and execute on the memory validation plan Skill Sets Strong expertise in development of memory macros of all types and architectures Strong understanding of transistor level circuit behavior and analysis Good understanding of the layout and their related challenges in sub nanometer process technologies Good understanding of signal integrity, EM/IR, and reliability analysis Good understanding of memory behavioral and physical models Good understanding of DFT Schemes and chip level integration Proficient in running transistor level simulators, writing automation scripts, and are tools savvy Complete hands on experience in using Cadence schematic/layout editor tools Complete hands on experience with transistor level simulators, Monte Carlo variation analysis, waveform viewer tools such as; HSPICE, HSIM, XA, FineSim, XARA, nWave, waveform viewer, etc.. Experience in Skill/Perl/Python Scripting is a strong plus Good communication, interpersonal, and leadership skills Good debugging skills, problem solving and logical reasoning skills Motivated, self-driven and good at multi-tasking

MTS SILICON DESIGN ENGINEER (Timing Constraints/STA Signoff ) THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. T HE ROLE : As a member of the AECG ASIC Group, you will help bring to life cutting-edge designs. As a member of the Back-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA Well versed with timing signoff methodology and corner definitions Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring full chip level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure P REFERRED EXPERIENCE : 8+ years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Proficient in analyzing SoC architecture to derive appropriate timing constraints and define STA methodology. Skilled in translating architectural and design specifications into accurate timing constraints (SDC), including clock definitions, generated clocks, exceptions (false paths, multi-cycle paths), and hierarchical timing. Owned timing budgets, constraint development, and timing ECOs, achieving first-pass silicon success. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc. Excellent communication and interpersonal skills and always enthusiastic to collaborate with diverse teams. Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Experience in working full-chip STA closure, defining mode requirements and corners for timing closure. Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering # LI-SR4 Benefits offered are described: AMD benefits at a glance .

We are seeking a highly skilled and experienced Design-for-Test (DFT) Engineer with 6-12 years of industry experience in architecting and implementing DFT solutions for complex SoCs and mixed-signal ICs. The ideal candidate should have a deep understanding of scan, at-speed test techniques, and compression methodologies, with hands-on experience in leading EDA tools such as Cadence Modus . Experience in handling DFT for analog and mixed-signal (AMS) blocks is a strong plus. Key Responsibilities: Own and drive DFT architecture and implementation for analog mixed signal chips from concept to production. Develop scan insertion, scan compression, and at-speed test strategies to meet high fault coverage and test cost targets. Work with cross-functional teams including design, verification, and physical design to ensure DFT integration and tapeout readiness. Define and implement test strategies for analog and mixed-signal IPs , including DFT hooks, wrappers, and test mode integration. Create test patterns and perform ATPG analysis to ensure test coverage goals are met. Debug DFT-related issues during silicon bring-up and collaborate with product/test engineering teams. Automate and optimize DFT flows and scripting for scalability and efficiency. Qualifications Required Qualifications: B. E. /B. Tech or M. E. /M. Tech in Electrical/Electronics Engineering or related discipline. Minimum 6 years of hands-on experience in DFT with successful tapeouts. Strong knowledge of scan insertion , scan compression , transition fault (at-speed) testing , and boundary scan (IEEE 1149. 1/1500). Proficiency in industry-standard DFT tools, with Cadence Modus experience highly desired. Experience with ATPG tools , test coverage analysis, and test pattern generation. Solid understanding of DFT for AMS blocks , including challenges in testability of analog circuits. Familiarity with scripting languages (TCL, Perl, Python) for automation. Good understanding of STA constraints for DFT and impact on synthesis and physical design. Proven experience in silicon debug and production test support. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Renesas’ Analog and Connectivity Business Unit (A&C) is seeking an experienced Test Engineer to join our team. This role offers a unique and exciting opportunity to work on the development of state-of-the-art Memory Interface Devices. You will be part of a cross-functional team, driving the product from conception to volume production. Key Responsibilities Develop test programs for characterization, production, and wafer sort using Advantest 93K platform. Design test hardware for high-speed applications. Participate in testability reviews with DFT/DFM teams to enhance yield and test methodologies. Test pattern conversion to ATE formats. Implement best practices for robust test solutions, including GR&R, HTOL, and Characterization procedures. Qualifications Test Engineer with 10+ Years experience developing hardware and software at Wafer Sort and Final Test for High-Speed products. 10+ Years of experience on Advantest 93K. FPGA knowledge is a plus. Strong analytical and problem-solving skills. Effective communication and teamwork abilities. Self-starter, motivated, and able to work independently. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

DFT Sr. Silicon Design Engineer New Dehli, India Engineering 66819 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFx - SE NIOR SILICON DESIGN ENGINEER THE ROLE : AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS Work with multi-functional teams and handling schedules The successful candidate may also be responsible of: Debugging and verifying block-/chip-level DFT/DFX features Porting or creating the DFT/DFX verification environment Block/Chip test plan creation and development Stimulus writing and debug, and regression clean-up Generating high quality manufacturing test patterns for stuck-at, transition fault models and using on-chip test compression techniques Stimulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Provide technical support to other teams PREFERRED EXPERIENCE: Minimum 5 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus. Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RP1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Position presents an opportunity to join the award winning and market leading Tessent team, India. The focus of the role is advanced design-for-test (DFT) insertion and automatic test pattern generation (ATPG) for semiconductor designs. It will involve understanding and supporting the latest DFT ATPG electronic design automation (EDA) technologies such as Tessent TestKompress and Streaming Scan Network (SSN). Someone in this role will gain a deep understanding of scan design, on-chip clock controls, and IJTAG infrastructure in support of scan testing. They will support the worldwide application engineering team on complex ATPG issues and build testcases for advanced DFT methodologies. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. Responsibilities for this role include: Build and deliver in-depth technical presentations, develop training material, white papers, supplied articles, and application notes. Work with customers as well as Siemens stakeholders such as regional application engineers, global support engineers, and marketing. Are you expertized in working through complex technical issues and independently building solutions and new methodologies! Explain complex principles in simple terms to broad audiences. Some travel, domestic and international. Successful deployment of existing and new Tessent DFT products in customer designs by enabling AEs. Working closely with our key customers on deployment challenges. Working with PEs and R&D to ensure new product readiness testcase in form of testcases, documentation and trainings. Architecture reviews of customer designs. Closely working with AEs to gather top issues blocking their engagement's success. Deep learning opportunities for Tessent DFT products including opportunities to present at various conferences worldwide including ITC and Siemens U2U. We don’t need hard workers, just superminds! BS degree (or equivalent) in Electrical Engineering, Computer Science or related field is required with 10 - 15 years of experience. Knowledge of design logic design languages, tool usage, design flow steps required. We are looking for someone that has exposure to DFT or SoC design for complex ASICs / SOCs. ATPG, IEEE 1687 IJTAG, boundary scan (BSCAN), hierarchical DFT implementation. Knowledge of a scripting language like TCL. We need someone self-motivated and dedication to improvement with strong problem-solving skills. Excellent organizational skills, written and verbal English language communication skills. Proficiency in LINUX and Windows environments. The role presents many opportunities to build specialized DFT and ATPG knowledge. Publications and other promotions of methodologies is encouraged. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday

Location Karnataka Bengaluru Experience Range 5 - 10 Years Job Description 3+ years to 10 yrs design experience Experience with owning chip level DFT and Post Silicon debug / analysis Understanding of DFT architectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification. Must have experience generating scan patterns and coverage statistics for various fault models like stuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E-fuse etc.). Experience debugging tester failures of scan patterns, diagnosis and pattern re-generation. Understanding generation of functional patterns for ATE Knowledge of at least any one of an industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools, etc) Design experience in MBIST / LBIST is an added advantage. Good understanding of constraints development for Physical Design Implementation / Static Timing Analysis. Preferred Skills/ Experience Experience with TCL / Perl is preferred. Understanding of IC design with Analog circuits and it’s design cycles is an added advantage. Effective communication skills to interact with all stakeholders. Team and People Skills: The candidate should have good people skills to work closely with the systems, analog, layout and test team Must be highly focused and remain committed to obtaining closure on project goals

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description In this role you will have the opportunity to Work as Principal Engineer, Quality Assurance accountable for overall product quality of the NPI releases. The Principal Engineer provides independent oversight of the design input process, design V&V activities, design transfer and product realization, and performance in the field to ensure that all design requirements are effectively met. The Principal Engineer also provides analytics to the Business on the efficacy, efficiency of the design and product realization processes. Opportunity to learn End to End product development as Responsible Quality representative driving compliance throughout Product life cycle. We are looking for a dynamic individual to join our Quality and Reliability Engineering team. The candidate is expected to have demonstrated proficiency in the philosophy of Quality. The candidate should demonstrate strong systems engineering fundamentals across all critical engineering domains important to product quality. The candidate should be able to challenge the status quo and be able to appropriately represent the “voice of the customer” to core teams while making decisions related to product quality. The ideal successful candidate Responsibilities Responsible for all aspects of product quality from PRD to Production handover for high volume production development until sustaining. Single point of contact, representing and driving quality in all program team meetings. Conduct cross-site, cross-team lessons learned for any Quality issues during development and sustaining phases of Product Life-Cycle Participate in Engineering reviews ( PRD, DFx, Qualification sync, test plan, RDT ) and forecast potential quality risk Perform quality risk assessment to a project and drive for mitigations enabling business, apart from being a gatekeeper Identify process gaps in the Product Life Cycle (PLC) and continuously highlight improvement actions for the execution teams Influence quality culture and mindset across the company and bring in more strategic goals Demonstrated to take data based decisions and resolve contentions Qualifications Bachelor or Masters Degree in Electrical/Electronic based Engineering 10 to 12yrs of certified professional experience in quality engineering Thorough understanding on Product Life Cycle and process-gap identification Exposure to factory processes and hands-on is a big advantage Experience and hands-on in, E2E product development, factory and customer quality Driving product quality and reliability working with CFT, Six sigma GB/BB would be added advantage Design for Quality / Reliability, pFMEA, DFMEA, DFM, DFT, Root cause analysis NPI product development and sustenance Data analysis and data-based decision making and action Process improvements drives for structural quality improvements Influencing CFT for decisions of betterment of quality Good understanding on Program Management Quality challenges and levers Product Qualification cycle RDT & ORT for Electronics Have Demonstrated, Strong teamwork Communication and leadership capabilities in driving cross-functional working teams Strategically and methodically thinking to bring the right balance of product quality in meeting customer and company needs is essential to the success of this role Influencing skills Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Program Manager 1 THE ROLE: We are seeking an experienced and dynamic Program Manager to join our Custom ASIC/SOC Development Group. In this role, you will lead high-impact technical programs from concept through tapeout to post-silicon validation. You ll manage cross-functional execution across RTL, verification, physical design, packaging, and bring-up, delivering complex SoC solutions to our global partners. THE PERSON: This role is ideal for someone with a strong technical background in chip design and 3 5 years of program management experience, capable of managing complexity, influencing stakeholders, and driving results in a highly matrixed organization. KEY RESPONSIBILITIES Own and drive SoC program execution from requirements through tapeout. Develop detailed plans of record, schedule, deliverables, resources, risks, and mitigation strategies. Coordinate across IP, SoC front-end, back-end, validation, test, and packaging teams. Act as the central point of contact for program status, issues, risks, and escalations internally and externally. Monitor and communicate progress using dashboards, KPIs, Gantt charts, and performance metrics. Ensure quality gates are met and engineering change requests are tracked and resolved promptly. Collaborate with engineering leads to make technical tradeoffs and align with design goals. Facilitate executive reporting and program reviews. Promote best practices in program execution and risk management. PREFERRED EXPERIENCE: Experience in managing multiple SoC programs in domains like mobile, compute, automotive, AI, etc. PMP certification or equivalent program/project management training. Familiarity with program tools such as MS Project, JIRA, Confluence, Power BI, or equivalent. Executive communication experience and ability to influence across technical and business functions. REQUIRED QUALIFICATIONS: Bachelor s or Master s degree in Electronics, Electrical, or Computer Science Engineering. 10-12+ years of experience in the semiconductor industry with 3 5 years in technical program management. Strong hands-on exposure in SoC design flows, IP development, integration, Verification/Validation, DFT, STA, physical design, and tapeout. Proven track record in leading cross-functional, geographically dispersed teams. Strong risk and issue management capabilities, with the ability to escalate and drive resolution effectively. #LI-SR4 Benefits offered are described: AMD benefits at a glance .

SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance .

PCB Design Engineer Job Title : PCB Design Engineer Location : Chennai, Hyderabad ,Bangalore Experience : 1-4 Overview: Responsible for designing printed circuit boards (PCBs) that connect electronic components in a compact and efficient layout. Key Responsibilities: Create schematic diagrams and PCB layouts. Ensure signal integrity and thermal management. Prepare fabrication and assembly files. Collaborate with mechanical and electrical teams. Tools & Technologies: Altium Designer, Eagle, KiCAD DFM/DFT principles IPC standards Career Path: Senior PCB Designer Hardware Integration Lead Manufacturing Design Manager

Job Category: Job Type: Job Location: Qualification: Job Summary: TechiesDesigns is seeking enthusiastic and motivated fresh graduates to join our team as Trainee PCB Design Engineers . This is an exciting opportunity for candidates looking to build a strong foundation in the field of PCB design and electronics hardware development. Key Responsibilities: Assist in the design and development of PCB layouts using industry-standard design tools (such as Altium, Eagle, KiCAD, etc.). Work closely with senior engineers to understand schematic design, layout guidelines, and DFM/DFT principles. Support in creating documentation, Gerber files, and BOM generation. Participate in prototype testing, troubleshooting, and validation. Learn and adhere to industry best practices and company design standards. Continuously upgrade knowledge and skills related to electronics and PCB design. Requirements: Fresh graduates with B.E / Diploma in ECE, EEE, or related streams. Basic understanding of electronics components, schematics, and circuit design. Familiarity with any PCB design tool is a plus. Strong analytical and problem-solving skills. Eagerness to learn and work in a collaborative environment. Good communication and documentation skills. What We Offer: Hands-on training and mentorship from experienced engineers. Exposure to real-world design projects. Opportunity to grow into a full-time PCB Design Engineer role. Supportive and innovative work culture.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded Underpinning our mission is the AMD culture We push the limits of innovation to solve the worlds most important challenges We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives AMD together we advance_ LEAD SOFTWARE SYSTEMS DESIGN ENGINEER The Role AMD is looking for an experienced engineer for an exciting role in Server CPU software development team This person will be a member of a core team and will work with the latest hardware and software technology The person will interact closely with key AMD technical experts to ensure the best possible performance and results on AMD platforms The Person The successful candidate for this position will be interacting with software and hardware technologists working across many locations This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions Key Responsibilities Problem solving across multiple software layers, (user space, kernel, applications, libraries) and hardware Optimization/development of the CPU performance stack (applications, libraries) for AMD server and workstation processors on Windows platform Analyze and solve performance, scalability bottlenecks when code is running on multi-core, multi-node deployments Innovate and publish papers, patents and participate in technical conferences to advance AMD technologies Continuously learn and grow along with evolving X86 server CPU architecture and application landscape Preferred Experience Image processing skills: Color format conversions, Image Filtering and Enhancement operations, Morphological operations, Image transforms and statistical operations Good understanding in Image Detection, Segmentation, Recognition, Restoration and Medical Imaging Knowledge in Signal Processing theory like Sampling, Quantization, DFT and FFT Multi-threaded FFT computing, Distributed FFT computing Very strong data structure and algorithmic skills Experience in identifying performance bottlenecks, and designing/implementing optimizations to relieve analyzed bottlenecks Strong Windows internals with experience in software development using C/C++ and debugging skills on multicore systems (preferably using OpenMP) Experience in performance analysis for data center, HPC (High Performance Computing), MPI (Message passing Interface) applications Experience in x86 (or other architecture based) optimizations Understanding of Cache sub-system, Instruction Set Architecture, pipeline (for any CPU) Bonus skills: Experience on Intel MKL libraries, Linear Algebra, x86 assembly programming (vector/SIMD), porting source code from Linux to Windows, development on Windows servers Knowledge of one or more CPU Profiling tools (preferably in Windows) Academic Credentials Graduate/masters degree in computer science or related fields LOCATION: Bangalore Benefits offered are described: AMD benefits at a glance AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law We encourage applications from all qualified candidates and will accommodate applicantsneeds under the respective laws throughout all stages of the recruitment and selection process

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Requirements: Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company: Did you know KONE moves two billion people every day? As a global leader in the elevator and escalator industry, we employ over 60,000 driven professionals in more than 60 countries worldwide joined together by a shared purpose, to shape the future of cities. In 2023, we had annual net sales of EUR 11.0 billion. Why this role? We are seeking for an Associate Engineer - Electronics supports the design, testing, and implementation of electronic systems and components. This role involves hands-on work with circuit design, embedded systems, and electronic testing, under the guidance of senior engineers. Ideal for candidates with foundational knowledge in electronics and a drive to innovate. What will you be doing? Assist in the design and development of analog and digital electronic circuits. Doing designs with KONE Electronics Design Automation tools or any popular EDA tools in the industry Support testing, troubleshooting, and validation of electronic hardware and embedded systems. Prepare technical documentation, schematics, and test reports. Collaborate with cross-functional teams including mechanical, software, and manufacturing engineers. Conduct component selection and ensure compliance with industry standards. Participate in prototype development and field testing Required Skills: Exposure in Hardware Development Life Cycle (HDLC) Familiar with European & American codes for hardware design (IEC, IPC, EN and CSA etc). Knowledge in Board design on Analog Design, Digital design, microprocessor and microcontroller based design, Memory Interfaces Sound Knowledge on communication protocols like RS232, RS485, SPI, CAN etc Knowledge to EMI, EMC standards & DFM, DFT Knowledge in RF fundamental for design. Knowledge to PCB Design & Simulation tools for Circuit design and analysis. Are you the one? Bachelor’s degree in Electronics/Electrical/Communication/Instrumentation Engineering or related discipline. 1–3 years of experience in electronics design or testing (internships included). Familiarity with EDA tools such as Cadence OrCad, Zuken Cadstar, Zuken CR8000, Cadence OrCAD PSPICE, LTSPICE, SI/PI, DFx etc… Familiarity / Basic Hands on with Lab Equipments - MSO/DSO, Logic analyser, Thermal, High end Power supplies etc… Problem solving skills, Self Learning attitude, Good Communication, Analytical & Presentation skills. What do we offer? Development and growth opportunities within a global organization. Warm and friendly international working environment, covering Being part of an industry leader in sustainability. At KONE, we are focused on creating an innovative and collaborative working culture where we value the contribution of each individual. Employee engagement is a key focus area for us and we encourage participation and the sharing of information and ideas. Sustainability is an integral part of our culture and the daily practice. We follow ethical business practices and we seek to develop a culture of working together where co-workers trust and respect each other and good performance is recognized. In being a great place to work, we are proud to offer a range of experiences and opportunities that will help you to achieve your career and personal goals and enable you to live a healthy and balanced life. Read more on www.kone.com/careers

Company Description Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas is a global, multi-billion dollar, publicly traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi-cultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast-growing data economy-related markets such as infrastructure and data center and strengthening our presence in the industrial/IOT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what’s next in electronics. Job Description  Full PE product lifecycle ownership from concept to end of life with a focus on ensuring the delivery of the highest quality products to our end customers  Definition of ATE test, qualification and manufacturing plans  Product release into manufacturing with adherence to stringent tier 1-customer requirements  Datasheet and automotive compliance reports  Real time customer support for design, product and quality related issues  Temperature/Voltage/Process characterization and production limit setting  Product new product introduction and yield ownership  Product BOM release and maintenance  Excursion management for both suppliers and customers  Use commercially available yield tools for yield improvement and monitoring, generate weekly reports and review with PE teams  KPI achievement in product related deliverables including NPI execution and velocity, product cost (Gross margin improvements), product quality performance and failure analysis cycle times  PAT, SYL, SBL, SPC limit and disposition optimizations to protect quality without excessive waste Requirements  7+ years experience in product engineering. A strong analog circuit background is a must. Familiarity with power management IC testing would be a plus  Familiarity with ATE tester platforms (eg. Teradyne J750, Advantest 93K)  Knowledge of analog and mix-signal circuitry and the common building blocks, device physics, test methodology and DFT knowledge  Experience with common lab test equipment (DC power supply, oscilloscope, multi- meters etc). Bench characterization experience is a plus  Familiarity with JEDEC/AEC qualification standards and stress test conditions. Experience with qual hardware/software development would be preferred  Experience in yield management tools such as PDF Exensio, JMP. Apply statistical analysis to isolate the issue and make data-driven decisions  Ability to managing supplier excursions and customer escalations through problem solving  Knowledge of Semiconductor Failure Analysis is preferable  Strong verbal and written communication skills  A good team player. Effective in fast paced, dynamic work environment

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years’ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG In depth knowledge of DFT concepts. In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. Expertise in scripting languages such as perl, shell, etc. Experience in simulating test vectors. Knowledge of equivalence check and RTL lint tool (like spyglass). Ability to work in an international team, dynamic environment Ability to learn and adapt to new tools and methodologies. Ability to do multi-tasking & work on several high priority designs in parallel. Excellent problem-solving skills Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076259

About Vecmcon: Vecmocon was incubated in 2016 at IIT Delhi by Peeyush Asati (CEO), Adarshkumar Balaraman (COO) and Shivam Wankhede (CTO). The company has now established its presence in major cities including Delhi, Bangalore, Chennai & Lucknow with a passionate team of more than 180 associates. The company is at the forefront of advanced computing solutions for electric mobility, specializing in safety-critical components such as Battery Management Systems (BMS), EV chargers, Vehicle Intelligence Modules (VIM), secure Firmware Over the Air (FOTA), etc for electric vehicles. The company is working with two of the top 5 EV players in India and various leading battery manufacturers ensuring a high level of reliability and safety, delivering robust performance for the next generation of intelligent and smart EVs. With a vision to develop the most reliable, robust, and cost-efficient systems, Vecmocon aims to drive the mass adoption of electric vehicles globally. About Role: We’re seeking a Senior PCB Design Engineer to lead the design and development of PCBs for chargers used in electric two and three-wheelers. The role requires deep expertise in PCB design, strong hardware fundamentals, component selection skills, and a solid understanding of power electronics and PCB manufacturing. Roles and Responsibilities: Lead design of high-reliability power electronics PCBs for automotive-grade products Own schematic creation, stack-up definition, and material selection for high-current, high-voltage designs Ensure compliance with EMI/EMC, thermal, and mechanical constraints during layout Conduct architecture reviews and design validation with the hardware team Select components based on electrical, thermal, cost, and reliability trade-offs Review and maintain schematic symbols, footprints, and library standards Lead root cause analysis for validation and production-level PCB issues Release complete production documentation (Gerbers, BoM, pick-and-place, assembly drawings) Guide junior engineers and drive best practices in layout and design Coordinate with suppliers and manufacturers for DFM/DFA compliance Implement cost reduction and continuous improvement based on field feedback Support ICT and FCT processes Ski lls 3+ years of PCB design experience; proficiency in Altium Designer preferred Strong foundation in electrical engineering and power electronics Expertise in analog, digital, and power layout with good thermal design practices Experience in debugging and testing power electronics systems Familiar with IPC standards (IPC-2221, IPC-2152, IPC-4761) and DFM/DFT guidelines Knowledge of signal/power integrity, impedance control, and EMI/EMC compliance Understanding of mechanical constraints; experience with 3D CAD models (DXF/STEP) Strong documentation and communication skills Leadership abilities to mentor and manage junior team members

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: Program Manager 1 THE ROLE: We are seeking an experienced and dynamic Program Manager to join our Custom ASIC/SOC Development Group. In this role, you will lead high-impact technical programs from concept through tapeout to post-silicon validation. You’ll manage cross-functional execution across RTL, verification, physical design, packaging, and bring-up, delivering complex SoC solutions to our global partners. THE PERSON: This role is ideal for someone with a strong technical background in chip design and 3–5 years of program management experience, capable of managing complexity, influencing stakeholders, and driving results in a highly matrixed organization. KEY RESPONSIBILITIES Own and drive SoC program execution from requirements through tapeout. Develop detailed plans of record, schedule, deliverables, resources, risks, and mitigation strategies. Coordinate across IP, SoC front-end, back-end, validation, test, and packaging teams. Act as the central point of contact for program status, issues, risks, and escalations—internally and externally. Monitor and communicate progress using dashboards, KPIs, Gantt charts, and performance metrics. Ensure quality gates are met and engineering change requests are tracked and resolved promptly. Collaborate with engineering leads to make technical tradeoffs and align with design goals. Facilitate executive reporting and program reviews. Promote best practices in program execution and risk management. PREFERRED EXPERIENCE: Experience in managing multiple SoC programs in domains like mobile, compute, automotive, AI, etc. PMP certification or equivalent program/project management training. Familiarity with program tools such as MS Project, JIRA, Confluence, Power BI, or equivalent. Executive communication experience and ability to influence across technical and business functions. REQUIRED QUALIFICATIONS: Bachelor’s or Master’s degree in Electronics, Electrical, or Computer Science Engineering. 10-12+ years of experience in the semiconductor industry with 3–5 years in technical program management. Strong hands-on exposure in SoC design flows, IP development, integration, Verification/Validation, DFT, STA, physical design, and tapeout. Proven track record in leading cross-functional, geographically dispersed teams. Strong risk and issue management capabilities, with the ability to escalate and drive resolution effectively. #LI-SR4 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Designation: Electrical Design Engineering Experience: 5+ Years Roles & Responsibilities:- Lead the architecture, design, and validation of power converters and electrical hardware platforms. Perform feasibility studies, design calculations, thermal analysis, and component selection. Conduct detailed PCB layout reviews Ensure IPC compliance, signal and power integrity, and manufacturing best practices, Identify and correct layout faults and cosmetic issues. Collaborate with outsourcing partners for hardware design and manufacturing execution. Drive hardware integration, ensuring system-level electrical performance. Focus on innovation initiatives including new converter topologies, design optimizations, and reliability enhancements. Lead technical design reviews, mentor junior engineers, and define internal hardware standards. Support EMC testing, HALT/HASS reliability testing, and regulatory compliance. Key Result Areas: Delivery of robust, high-efficiency power and control hardware architectures. Advancement of innovation initiatives within hardware development. Quality assurance and management of outsourced design and manufacturing partners. Development and enforcement of internal hardware review frameworks and documentation standards. Technical leadership and capability building across the hardware engineering team. Internal: Lead the delivery of high-efficiency power and control hardware architectures across projects. Drive innovation initiatives such as new converter topologies, design optimization, and advanced reliability methods. Establish and enforce hardware review frameworks, DFM/DFT standards, and documentation practices. Mentor and develop internal engineering capabilities through technical leadership and structured reviews. External: Manage collaboration with outsourcing partners for hardware design, manufacturing, and validation. Ensure outsourced work meets internal quality standards, design specifications, and timeline requirements. Lead technical reviews of externally developed designs for IPC compliance, manufacturability, and signal integrity. Coordinate with external suppliers and manufacturers to secure customized components and ensure smooth prototype and production deliveries. Educational Qualification: •Bachelor's or Master’s degree in Electrical Engineering, preferably with specialization in Power Electronics. Required Skills: Expertise in power converter design across major topologies. Strong proficiency in digital and analog control circuit design. Extensive experience in PCB layout reviews emphasizing signal integrity, power distribution, and IPC compliance. Practical knowledge of Design for Manufacturing (DFM) and Design for Testability (DFT). Hands-on with PCB CAD tools (Altium Designer, Cadence Allegro) and Signal Integrity simulation software. Vendor management experience for external hardware development. Strong leadership, technical documentation, communication, and mentoring abilities.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Program Manager 1 The Role We are seeking an experienced and dynamic Program Manager to join our Custom ASIC/SOC Development Group. In this role, you will lead high-impact technical programs from concept through tapeout to post-silicon validation. You’ll manage cross-functional execution across RTL, verification, physical design, packaging, and bring-up, delivering complex SoC solutions to our global partners. The Person This role is ideal for someone with a strong technical background in chip design and 3-5 years of program management experience, capable of managing complexity, influencing stakeholders, and driving results in a highly matrixed organization. Key Responsibilities Own and drive SoC program execution from requirements through tapeout. Develop detailed plans of record, schedule, deliverables, resources, risks, and mitigation strategies. Coordinate across IP, SoC front-end, back-end, validation, test, and packaging teams. Act as the central point of contact for program status, issues, risks, and escalations—internally and externally. Monitor and communicate progress using dashboards, KPIs, Gantt charts, and performance metrics. Ensure quality gates are met and engineering change requests are tracked and resolved promptly. Collaborate with engineering leads to make technical tradeoffs and align with design goals. Facilitate executive reporting and program reviews. Promote best practices in program execution and risk management. Preferred Experience Experience in managing multiple SoC programs in domains like mobile, compute, automotive, AI, etc. PMP certification or equivalent program/project management training. Familiarity with program tools such as MS Project, JIRA, Confluence, Power BI, or equivalent. Executive communication experience and ability to influence across technical and business functions. Required Qualifications Bachelor’s or Master’s degree in Electronics, Electrical, or Computer Science Engineering. 10-12+ years of experience in the semiconductor industry with 3-5 years in technical program management. Strong hands-on exposure in SoC design flows, IP development, integration, Verification/Validation, DFT, STA, physical design, and tapeout. Proven track record in leading cross-functional, geographically dispersed teams. Strong risk and issue management capabilities, with the ability to escalate and drive resolution effectively. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Physical Design Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus. Experience in DMSA/Tweaker ECO flows for PPA improvements. Experience in manual timing fixes, ECO generation for MCMM mode corners. Good understanding of SDC constraints and able to translate timing requirements into constraints. Responsible for integrating the blocks, analog Ip s for full chip timing analysis. we'll aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence. Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management. Participate in Mentoring new joiners in the group on technical skills. Provide inputs for CAD/DA team from Design Implementation perspective. Work closely with Logic design team and Analog teams to provide inputs from physical design and STA. Work closely with DFT team on scan aspects and provide inputs from physical design. Continuously work on methodology and productivity improvements. Qualifications Must have at least 8 years should be related to STA/Synthesis . Must have Involved in high Speed design tape-outs and constraint development across modes. Must have detailed knowledge of Constraints , Signoff closure methodology for STA and RTL2GDS flow is desired Experience in Tcl/Tk, PERL is a Plus.

Experience in dft scan insertion, atpg at ip and soc level Hands on experience in atpg timing and no-timing simulations Proficient in doing basic unit-level verification using simulations. Scan/atpg patterns & test flows development, debug, test and characterization

Apply to this job The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Metas computing efforts with capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Metas data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Implementation Responsibilities Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop Power Intent Specification in UPF for the multi-Vdd designs Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in Design Integration and Front-End Implementation Experience with Register-Transfer Level (RTL) Synthesis and design optimization for Power, Performance, Area Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other Hardware Description Language (HDL) Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues Experience with Electronic Design Automation (EDA) tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. Experience with communicating across functional internal teams and vendors Preferred Qualifications Knowledge of Clock Domain Crossing, Reset Domain Crossing, Logic Error Correction (LEC) Synthesis Background, Timing Constraints Development, Floorplanning and Static Timing Analysis (STA) Experience Knowledge of Register-Transfer Level (RTL) coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, Static Random Access Memory (SRAM) Experience with Power, Performance, Area Analysis and techniques for reducing power Knowledge of Low power design. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Scripting and programming experience using Perl/Python, TCL, and Make About Meta . Equal Employment Opportunity . Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .