2311 Dft Jobs - Page 19

Job Description Knowledge, skills & abilities Required BE/B.Tech in Electronics Engineering with at least 10+ years experience in hardware development 6+ Years of Experience in Product Development, System Architecture Design, Design Implementation, Hardware Development life cycle Expertise in microcontroller / microprocessor-based circuit architecture & design Analog circuit design, Design and development experience with Control system design using Micro controllers, Op-amps circuits, Filter Design, ADC, motor driver Circuits Hardware board design ownership of NPD projects to launch products as per business plan Minimum 3 end to end Product development experience in the role of HW designer, ...

BE/B.Tech in Electronics Engineering with at least 10+ years experience in hardware development 6+ Years of Experience in Product Development, System Architecture Design, Design Implementation, Hardware Development life cycle Expertise in microcontroller / microprocessor-based circuit architecture & design Analog circuit design, Design and development experience with Control system design using Micro controllers, Op-amps circuits, Filter Design, ADC, motor driver Circuits Hardware board design ownership of NPD projects to launch products as per business plan Minimum 3 end to end Product development experience in the role of HW designer, knowledgeable about PDLC process & Practices, Audits. F...

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse...

Job Summary: A technically proficient and detail-oriented Aerospace Valve Assembly and Testing Engineer to handle the end-to-end process of assembling, testing, and qualifying aerospace valves. The ideal candidate will also be responsible for conducting environmental tests as per MIL-STD requirements, ensuring all assemblies meet aerospace and defense compliance standards. Key Responsibilities: Valve Assembly: Assemble aerospace-grade valves (e.g., solenoid, relief, check, control valves & Regulator) per engineering drawings, standard operating procedures, and customer specifications. Ensure clean handling and ESD precautions for sensitive components. Perform torquing, fitting, and sub-assem...

As a Product Validation Engineer at Cadence Design Systems, you will be a crucial part of the Modus R&D team, focusing on validating and supporting Design-for-test (DFT) technologies. Your role will involve working on complex problems that require innovative thinking, debugging customer reported issues, and collaborating with R&D to provide out-of-box solutions with an emphasis on robustness, PPA, and scalability. **Key Responsibilities:** - Work on insertion and validation of DFT technologies such as 1500 Wrapper, Compression, RTL DFT, Low Pin Count Test, Hierarchical Test, LBIST, etc., using Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on in-house and customer design...

About Nexstem: Nexstem is building the Human Body API —a platform to read and write biosignals like EEG, ECG, and EMG. By combining cutting-edge hardware, software, and data infrastructure, we’re accelerating the future of brain-computer interfaces (BCI) and human-computer interaction (HCI). Our mission is to decode the body’s signals to tackle challenges like restoring lost functions, enhancing human capabilities, and enabling breakthroughs in health and cognition. Roles And Responsibilities Product Design and Development: Responsible for the design, development, and support of new and existing hardware products. Manage the design process from conceptual design, parts selection, design simu...

About Nexstem: Nexstem is building the Human Body API —a platform to read and write biosignals like EEG, ECG, and EMG. By combining cutting-edge hardware, software, and data infrastructure, we’re accelerating the future of brain-computer interfaces (BCI) and human-computer interaction (HCI). Our mission is to decode the body’s signals to tackle challenges like restoring lost functions, enhancing human capabilities, and enabling breakthroughs in health and cognition. Roles And Responsibilities Product Design and Development: Responsible for the design, development, and support of new and existing hardware products. Manage the design process from conceptual design, parts selection, design simu...

Job Requirements Conduct DFT Engineering Tasks: DFT Audit/Scan Logic/MBIST Logic/BSCAN Logic Insertion Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design Responsible for development of innovative DFT IP in collaboration with the cross-functional teams, and play a key role in full chip design integration with the testability features integrated in the RTL Work closely with the design/design-verification and physical design teams to enable the integration and validation of the Test logic in all phases of the design, and back-end implementation flow Analyze timing report and suggest for the solutio...

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive de...

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Experience: 10+ years - Should have worked hands-on extensively on full chip DFT design, implementation, vector generation/verification, JTAG, boundary scan and simulation. -Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus. - Should have participated in successful tapeouts ofSoC/ASIC chips at 14nm or below and achieved test targets. - Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. -Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process -Excellent problem solving and debugging skills. Proactive in nature -Leading junior teams, Mentori...

- Should have worked hands-on ASIC DFT design, implementation, vector generation/verification, JTAG, boundary scan and simulation. -Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus. - Should have participated in successful tapeouts ofSoC/ASIC chips at Lower nodes ; 14nm or below and achieved test targets. - Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. -Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process -Excellent problem solving and debugging skills. Proactive in nature - Excellent Customer interaction, Communication and Team w...

Minimum qualifications: Bachelor’s degree in Electrical Engineering or equivalent practical experience. 5 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs. Experience with System on a Chip (SoC) cycles. Experience in high-performance, high-frequency, and low-power designs. Preferred qualifications: Master’s degree in Electrical Engineering. Experience in coding with System Verilog and scripting with TCL. Experience with VLSI design in SoC or multiple-cycles of SoC in ASIC design. Experience with layout verification and design rules. About The Job Be part of a team that pushes boundaries, developing custom silic...

Job Description 8+ years of hands-on ASIC DFT experience with multiple production tapeouts owning full-chip DFT. Proven ownership of MBIST architecture and hands-on insertion across large memory arrays; experience with repair, redundancy, and BIRA/BISR flows. Hands-on scan insertion and compression, ATPG pattern generation and coverage closure. Solid understanding of test-mode timing, constraints, and PnR interactions; experience with test clocks/reset distribution and power intent in test modes. Proficiency with at least one major DFT tool suite : Synopsys (DFTMAX/SpyGlass-DFT/TetraMAX), Siemens Tessent (Scan/MBIST/ATPG), or Cadence Modus. Experience with JTAG/boundary scan and, ideally, IE...

Role Overview: River, an electric vehicle company, is looking for a skilled individual to lead the development and industrialization of complex EE modules for their multi-utility scooters. As a key member of the team, you will work closely with EMS partners to develop manufacturing processes for new products to meet Quality, Cost, and Delivery requirements. Your role will involve collaborating with the R&D team in optimizing design and DFx activities, addressing technical queries with CMs and PCB manufacturing partners, and standardizing/improving manufacturing processes. Additionally, you will be responsible for supplier identification, use of special processes, reviewing design data packag...

You have a job opportunity for the Manager / Senior Role Physical Design Engineer position in Hyderabad. Your primary responsibilities will include: - Performing IP/Block level PnR activities from Netlist to GDS-II - Demonstrating good knowledge of all PnR activities such as Floor-planning, Placement, CTS, Routing, Timing closure (STA), and signoff checks like FEV, VCLP, EMIR, and PV - Executing all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file - Handling signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff - Having knowledge of high performance and low power implementation methods (preferred) - Expertise in ICC2/Fusion Compil...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Role & responsibilities 4-9 years of complete hands-on experience in - DFT Architecture, Design, Scan, MBIST, Gate Level simulations with Timing, DFT Constraints, Pattern Generation, and ATE support. Should be familiar with SoC & IP level DFT Architecture and Flows from RTL to production. Able to understand and implement requirements from Test engineering perspective Familiarity with either Synopsys or Tessent Scan flows. Simulation tools: NCSIM/XCELIUM/VCS Should have handled aspects of Scan Scan Insertion, ATPG, Coverage improvement, Pattern Generation on their own. Familiarity with various test pattern formats – STIL, WGL, VEC formats. Experienced in defining DFT constraints, Timing Closu...

Greetings from TCS!! We're looking for Hardware Design Engineers to join our dynamic team & drive the development of cutting edge solutions. Role - Embedded Hardware Design Engineer Desired Experience Range - 3-8Years Location of Requirement - Pune Required Skills - Analog design: OP-AMP circuits, ADC, data acquisition, sensor interface/signal conditioning circuits. Microprocessor/microcontroller-based hardware designs Power electronics: Linear & Switch mode supply topologies (Hi/Low voltage Buck, boost converters, AC/DC switch mode power supply design experience Various Communication Standards: UART, I2C, RS485, SPI, USB, CAN, Ethernet etc Multilayer PCB design understanding layout & routin...

We are seeking a Hardware Design Lead to take full ownership of BMS hardware development for EV and energy storage applications. The role focuses on designing new hardware using proven architectures, selecting components, and delivering production-ready PCBs in collaboration with firmware and manufacturing teams. You will ensure the hardware platform is robust, manufacturable, and scalable for Indian supply chains and local EMS partners. Key Responsibilities • Hardware Design & Development • Lead schematic capture and PCB layout for BMS hardware (cell monitoring, balancing, power stage, comms). • Optimise designs for manufacturability (DFM/DFT), reliability, and cost. • Select and validate c...

The Client DDRPHY team is looking for an energetic and passionate Logic Design Engineer who will work on high-speed digital design targeted towards low power optimized IP implementations. You will be responsible for overseeing definition, design, verification and your responsibilities will include but are not limited to - defining architecture and microarchitecture features of the block being designed, implementing RTL in System Verilog, setting up Automation flows for IP Logic Design, ensuring RTL quality via Front End tools like Lint, CDC, VCLP, Synthesis QA checks etc, creating FE packages for IP milestones that meet SoC Collateral requirements, create innovative automated solutions to he...

DFT Engineer Job Title: DFT (Design for Testability) Engineer Experience: 1- 4 years Education: B.Tech/M.Tech in ECE, VLSI Responsibilities: Insert scan chains, MBIST, BIST, and boundary scan logic Generate and verify test patterns (ATPG) Analyse coverage and optimize testability Support post-silicon bring-up and yield analysis Requirements: Knowledge of DFT concepts and ATPG tools Familiar with Synopsys DFT Compiler or Mentor Tessent Understanding of scan compression techniques

Job Description Role – PCB Design Engineer Key Responsibilities: Expertise in using ECAD tools such as Allegro/Xpedition software. Understand and analyze technical Requirements and Customer input to execute Layout Engineering. Experience in designing Layout for motherboards using Intel, AMD, NXP, TI processors is big plus. Understanding the design guidelines from PDG and implementation is big plus. Very good knowledge of relevant IPC design standards for Library creation, PCB design and Schematic Entry. PCB layout placement with a strong background dealing with analog, digital, power, and high-speed circuitry. Experience in high-speed net routing and usage of blind & buried vias. Knowledge o...