1109 Dft Jobs - Page 23

Metrology Engineer (Injection Moulding) - Oragadam Exp: 5+ yrs Immediate joiner preferable Skill required: CMM,VMM,Gauges,7QC tools, testing quipments,Lab quality,DFT,CPCK,COPQ,CAPA,MFI CV - lifeturnmgmt6@gmail.com /7358656750

In your new role you will: Responsible for SoC DFT Architecture definition / implementation / verification / silicon debug of SoC/Full Chip. Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. Responsible for ATPG, DRC analysis, Test coverage debug , Memory BIST implementation and verification. Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck-at / TDF / Bridging / Cell-aware / iddq fault models. Good debug skills in ZERO delay and SDF based scan/MBIST/JTAG simulations. Hands on experience in analysis and debug of above-mentioned test domains. Hands of experience in post silicon debug of scan/MBIST patterns/yield fall out You are best equipped for this task if you have: ASIC flow understanding. Experienced in LEC, CLP, power analysis flow is preferred The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the DFT spec, implementation, verification, and Post silicon debug. In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies . The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Scripting skills such as PERL/TCL/Python are preferred Degree & Discipline: BE/B.Tech Electrical/Electronic or ME/M Tech in VLSI design. Experience in Industry: 12+ years of in DFT implementation, verification and post silicon debug areas

Location : Delhi NCR Type : Full-time, in-office (Monday to Friday and Alternate Saturday, 9:30 AM - 6:30 PM) Experience : 4+year’s; Preferably in startup or fast paced organization Salary : More than 5 Lpa What You’ll Do ● PCB testing, troubleshooting and fault analysis. ● Identify and resolve power circuit failures and common fault patterns ● Develop and implement testing SoPs for PCB assemblies ● Maintain detailed repair documentation and failure analysis reports ● Work with design teams to suggest improvements for future product iterations ● Support production by analyzing PCB failures and implementing preventive measures Who Are You? ● Qualifications : Electronics Engineering degree from Tier2+ college. . ● Background : Hands on experience in PCB testing. ● Skillset: PCB Testing, Troubleshooting, DFM, DFT etc. . Competencies - ● PCB design experience ● Experience in one or more of in circuit testing, flying probe testing, functional testing, board level testing, and experience in PCB repair. ● Proficient use of soldering and desoldering equipments, oscilloscopes, multimeters/ and any other equipments required during the testing of the products. ● Experience in replacing faulty components on PCBs across appliance types. ● Ability to write test holistic scenarios and test procedures of different products. ● Ability/ Experience in setting up SOP’s and best practices for common failure scenarios. ● Self starter- someone who can lead the testing and repair initiative. ● Knowledge of analog and digital circuit design ● Proficiency at reading and understanding schematics and other electronic engineering documentation ● Experience in DFM/DFT methodologies ● Experience with SMT

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Responsibilities The role’s day to day responsibilities cover: R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills. Job Qualifications BE/BTech/ME/MTech- Computer Science or others Required Skills Develop reliable, scalable, and high-performance Modus DFT software that is easy to use. Develop software tools in C/C++ to support DFT and ATPG. Research and develop software solutions to allow greater efficiency in architecture, hardware, and software teams. Development environment is C++ on Unix in multi-threaded environment with expertise in C++, data-structure and algorithms. Strong knowledge of Tcl is preferred Experience in language compiler Prior experience with large software development projects is highly recommended. We’re doing work that matters. Help us solve what others can’t.

Job Description Centum Electronics Ltd is a leading ESDM (Electronics System Design & Manufacturing) Indian Multinational Company founded in 1994 that offers Mission Critical design, development & manufacturing of customized system/subsystem solutions for high-reliability applications for global customers in Defence, Aerospace, Space, Industrial, Medical, and Transportation domain. Centum has around 2000 employees and has operations across India, USA France, and Canada. Centum revenue is 150 million USD and has been recognized by World Economic Forum as a global growth company and Forbes Asia featured Centum as ‘Asia’s 200 Best Companies under a Billion’. CENTUM EMS –The Electronics Manufacturing Services business unit addresses high -technology high-reliability complex products in the defence, aerospace, industrial, medical, automotive and transportation segments. The offerings include build to print, PCBA, Box build, system integration, test, environmental screening services. What You'll Do Project Management: Lead and manage NPI projects from concept to production readiness, ensuring timely execution and customer satisfaction. \ Customer Coordination: Act as a primary point of contact for customers during the NPI phase; understand requirements and translate them into internal deliverables. Cross-functional Collaboration: Coordinate with engineering, sourcing, quality, manufacturing, and supply chain teams to ensure alignment and readiness. Process Development: Define and optimize manufacturing processes and workflows for new products. DFX Reviews: Facilitate Design for Manufacturability (DFM), Design for Assembly (DFA), and Design for Testability (DFT) reviews with internal teams and customers. Documentation: Ensure preparation and review of all technical documentation, including BOMs, process flows, FMEA, control plans, and work instructions. Pilot Builds: Plan and execute prototype and pilot builds; collect data to improve yield and performance. Change Management: Implement and manage engineering change orders (ECOs) and revisions during the NPI lifecycle. Risk Management: Identify potential risks during NPI and develop mitigation strategies. Continuous Improvement: Drive initiatives for continuous improvement in time-tomarket, product quality, and cost efficiency. Who You Are? Overall, 15 -20 years of Experience in NPI, Technology Transfer, Manufacturing and Engineering is required. Good communication and presentation skills. Problem solving abilities. Leadership qualities and interpersonal skills. Good skill of MS Office Educational Background: BE – EEE / ECE.

Job Description: We are looking for highly motivated people who perform PCB design work on new products and legacy products. The role requires knowledge of Cadence Allegro 17.4 and Concept HDL packages as well as expertise in PCB manufacturing processes. The role will involve very close working with the rest of the hardware design team for all aspects of PCB design and manufacture. We want them to join our team and help develop the technology of the future. Essential Responsibilities: Read, interpret, and capture electrical schematics. § Design multi-layered PCB’s using industry standard techniques, ensuring considerations for DFM and DFT have been made. Experience with layout of digital, analog, and power converter systems. Manage and maintain shared component libraries, databases, and shared building block designs. Capture new symbols and footprints, including mechanical information. Generate manufacturing collateral, including draftsman mechanical drawings and technical specifications. Participate in design for manufacturing (DFM) reviews. Work closely with power electronic engineers and PCB manufacturers. Analyse and resolve PCB related issues in a timely manner. Ensure processes are followed to comply with quality controls. Setup and manage design rules and stack-ups, pad-stacks for various types of designs. Advise on cost reduction or high-performance techniques. Help establish new and efficient design procedures. Provide technical guidance and mentor team members. Experience: In-depth knowledge of the PCB design process. Knowledge of Power electronic circuit design. Knowledge of high-frequency, digital, RF, and high-density design is a plus. Minimum of 5 to 8 years’ experience using Altium, including in-depth knowledge of working with a database, net classes, high voltage rules, variants, job files, and rooms. Managing shared component libraries using Altium database and git revision control. Experience with CAD drawing tools is a plus. Knowledge of IPC specifications to aid in your ability in design for manufacturability of both fabrication and assembly process. Experience in PCB designs for line voltage applications (AC/DC power supplies) is a must. Experience with Cadence Allegro 17.4 and Concept HDL and Orcad Schematic and PADS power PCB, DX designer additional tools. IPC design Industry standard Attributes: Independent self-starter with good organizational skills. Track record showing understanding of power electronic converters. Strong attention to detail and an ability to work independently. Highly collaborative and responsive with internal resources, fab, customers, etc. Good listening, verbal, written, and interpersonal communications skills. Willing to engage in open, honest interactions and work as part of a team. Ability to work with electrical engineers, test engineers, manufacturing engineers, fabrication, and assembly vendors. Results-oriented, data-driven and must be willing to learn and grow with technology. Soft skills : § Co-ordination Internal § Sense of urgency § Ownership § Communication Skill § Negotiation Requirements: § Diploma /bachelor’s in electrical/Electronic engineering. Primary Location : IN-Karnataka-Bangalore Schedule : Full-time Unposting Date : Ongoing

Job Description: We are seeking a skilled and motivated DFT Engineer with at least 2 to 10 years of industry experience in Design for Test in the VLSI domain. As part of our SoC Design team, you will play a key role in implementing and validating DFT architecture to ensure high test coverage, low DPPM, and efficient silicon debug capabilities. Key Responsibilities: Develop and implement DFT architecture for complex ASICs and SoCs. Integrate and verify DFT features such as: Scan insertion and ATPG Memory BIST (MBIST) Logic BIST (LBIST) JTAG/IEEE 1149.1 (Boundary Scan) Test compression techniques (e.g., Tessent, Synopsys DFTMAX) Work closely with RTL, synthesis, and backend teams for DFT implementation and sign-off. Run and debug simulations for scan and BIST logic. Work with Automatic Test Equipment (ATE) teams to bring up and validate silicon. Support post-silicon debug and yield improvement efforts. Collaborate with cross-functional teams including verification, physical design, and validation. Required Skills: 2+ years of hands-on experience in DFT implementation and test methodology. Strong knowledge of scan insertion, ATPG, and fault grading. Experience with DFT tools such as: Synopsys (DFTMAX, TetraMAX) Mentor Tessent Cadence Modus Proficiency in Verilog/VHDL, TCL, and shell scripting. Understanding of digital design and SoC architecture. Familiarity with STA and timing constraints related to DFT.

Work Schedule Standard (Mon-Fri) Environmental Conditions Office Do you have a passion for innovative ideas and groundbreaking discoveries? With over $1 billion invested annually in R&D, at Thermo Fisher Scientific you’ll help solve some of the world’s toughest challenges, from giving cancer patients hope, ensuring safe drinking water and helping law enforcement tackle cases through forensics. We empower our teams to put science into meaningful action and give our R&D colleagues the autonomy, resources and tools they need to take science a step beyond. Role Purpose Summary: The "Staff Engineer, Electrical" is a member of a global R&D Team. The role is of a hands-on Electrical/Electronic engineer who is motivated to actively contribute to the new design and update of existing products. The person will play key role in architecting the systems, be involved from idea to product launch/update and own the design aspects and address all technical challenges including regulatory certifications. Roles & Responsibilities Work with cross function team to capture requirements, perform system / subsystem design, finalize electronics design requirement by reviewing with systems & global engineering teams. Provide design options & tradeoff analysis to meet the requirements Design schematic of digital, mix signal & power electronics circuit board that satisfied the design requirement Build and review the design documents and verification plan mapping to all the requirements including key performance & reliability requirements. Ensure the design performance meets the requirements, stays in sync with the Manufacturability and Serviceability, and achieve the cost/reliability target. Perform reviews on design concepts, component selections, trade off analysis and resolve technical challenges Collaborate closely with the other engineering team members to have design meet with compelling design and form-factors that also meet regulatory, safety, environmental, reliability, thermal and interface standard (Ethernet, USB, etc.) compliance requirements. To work with the sourcing team and the supplier to coordinate the manufacturing and provide detailed requirement for FCT of PCBA to make sure the PCBA from production line can meet design requirement. Continuously learns and grow technical depth and knowledge across product lines. Candidate Educational & Professional Experience Requirement: Masters or Bachelor’s degree in Electrical/Electronics engineering, or related field or equivalent. 12+ years of experience in hardware design and development in embedded system design with 8/16/32-bit microprocessor design Proficiency Requirements Must Have: Should have shown strength in working with system/software/Firmware/hardware/ Electrical requirements development and validation Hands on experience in analog, digital and power supply design. Also, interfacing electro-mechanical and other peripherals in instrument design with sensors and control algorithm. Indepth understanding in alternate design analysis/part substitute for cost out ideas and obsolescence management including design analysis for quality, reliability, power consumption, timing parameters etc. Should have good knowledge on the compliance requirement & should support product regulatory compliance testing including EMC/EMI, CCC, UL, RoHS, etc. Proficient in debugging instruments (digital oscilloscopes, logic analyzers, spectrum analyzers); Experience in practices for Design for Test (DFT), DFR and Design for Manufacturing (DFM) background. Strong analytical and problem-solving skills and communication skills. Strong knowledge of Software & Firmware Engineering principles Agility to multiple simultaneous projects, tasks & programs to suit business needs Desirable Experience with cost take out/VAVE methodologies and Phase gate process C/C++ Embedded Programming FPGA based Design with programming using HDL Benefits We offer competitive remuneration, annual incentive plan bonus, healthcare, and a range of employee benefits. Thermo Fisher Scientific offers employment with an innovative, forward-thinking organization, and outstanding career and development prospects. We offer an exciting company culture that stands for integrity, intensity, involvement, and innovation!

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are looking for an experienced and driven Senior Test Manager to oversee the test strategy and execution for DCDC converters and Power Management IC (PMIC) solutions. This leadership role requires in-depth technical knowledge of analog/mixed-signal testing, volume production, and collaborative development processes. The successful candidate will lead a test team, working closely with design, validation, product engineering, and manufacturing teams to ensure flawless silicon delivery Key Responsibilities Own and lead test development from design handoff to high-volume production for DCDC and PMIC products. Develop and implement robust test strategies including ATE planning, silicon characterization, qualification, and production ramp-up. Define Design-for-Test (DFT) requirements and partner with design teams to ensure optimal test coverage. Lead the creation of test hardware (load boards, probe cards) and software (test code, automation scripts). Continuously optimize test cost, cycle time, and yield performance. Oversee reliability, corner case, and qualification testing for automotive, industrial, or consumer product standards. Coordinate with foundries and test partners to ensure seamless test flow and high-quality production output. Mentor and develop test engineers; foster a high-performance, innovative team culture. Ensure compliance with quality standards such as AEC-Q100 for automotive-grade products. Qualifications Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) with over 12 years of test engineering experience (preferably in PMIC/DCDC). Strong foundation in analog/mixed-signal testing, especially for LDOs, DC-DC converters, and current/voltage monitors. Experience in writing and debugging test programs, performing silicon validation, and executing production ramps. Understanding of power management architectures, board-level integration, and thermal dynamics. Knowledge of scripting and automation tools (Python, Perl, C/C++). Track record of working effectively in global, cross-functional teams. Experience with automotive semiconductor testing is highly desirable. Strong interpersonal, leadership, and communication skills. Desirable Skills Familiarity with ISO26262 and functional safety verification. Wafer-level testing experience Proficiency with lab instruments like oscilloscopes, SMUs, and electronic loads We recognize and appreciate the value and contributions of individuals with diverse backgrounds and experiences and welcome all qualified individuals to apply. Equal Opportunity Employer: Disability/Veteran Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Role: Senior Design Verification Engineer (PCIe) Role: Bangalore Job Summary: We are looking for a highly experienced and motivated Senior Design Verification Engineer with a deep understanding of the PCIe protocol and hands-on experience in SystemVerilog and UVM. The ideal candidate will lead verification activities for complex PCIe subsystems or SoCs, and contribute to building scalable, reusable verification infrastructure. Key Responsibilities: Develop UVM-based verification environments for PCIe IPs or SoCs . Define and execute comprehensive verification plans for PCIe Gen3/Gen4/Gen5/Gen6 features. Drive testbench development, stimulus generation, score boarding, and coverage closure. Validate protocol compliance including LTSSM, TLP/DLLP, BAR/Address decoding, and interrupt mechanisms. Work closely with RTL, DFT, and system validation teams for debug and feature bring-up. Conduct assertion-based verification and participate in formal verification as needed. Collaborate with cross-functional teams to ensure successful first-silicon quality. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in ECE 8+ years of experience in ASIC/SoC design verification. Proven expertise in System Verilog, UVM, and complex testbench development. Deep knowledge of PCIe protocol (Gen3/Gen4/Gen5/Gen6). Experience in verifying Root Complex (RC) and Endpoint (EP) configurations. Familiarity with AMBA protocols (AXI, AHB) and memory-mapped IO. Proficiency with EDA tools like VCS, Questa, Verdi, Sim Vision. Strong debugging and analytical skills, particularly with PCIe protocol analyzers and simulation waveforms. Scripting proficiency in Python, Perl, TCL, or Shell for automation. Nice to Have: Knowledge of low power (UPF) and DFT concepts. Familiarity with Formal Verification, Portable Stimulus, or Emulation. Exposure to hardware validation, bring-up, or post-silicon debug. Domain experience in datacenter, storage, networking, or automotive industries. Soft Skills: Strong communication and documentation skills Problem-solving mindset and attention to detail Leadership in driving verification tasks and mentoring junior engineers Job Types: Full-time, Permanent Pay: ₹4,000,000.00 - ₹5,000,000.00 per year Benefits: Cell phone reimbursement Health insurance Paid time off Provident Fund Schedule: Day shift Work Location: In person

LTTS India Mysore Job Description Minimum of 10 years of experience in PCB design and schematic capture with expertise in Altium Designer. Strong understanding of analog and digital circuit design. Experience in high-speed PCB routing and signal integrity analysis. Knowledge of EMI/EMC guidelines for PCB design. Familiarity with IEC 60601-1 and IEC 60601-1-2 standards Experience with cable assembly drawings in Altium designer. Ability to interact with PCB/PCBA manufacturers and suppliers to resolve technical issues. Knowledge of DFM (Design for Manufacturability), DFT (Design for Testability), and DFA (Design for Assembly) principles. Knowledge of thermal management techniques in PCB design Strong analytical, troubleshooting, and problem-solving skills. Excellent communication and teamwork skills. Job Requirement PCB Design Engineer

Centum Electronics Ltd is a leading ESDM (Electronics System Design & Manufacturing) Indian Multinational Company founded in 1994 that offers Mission Critical design, development & manufacturing of customized system/subsystem solutions for high-reliability applications for global customers in Defence, Aerospace, Space, Industrial, Medical, and Transportation domain. Centum has around 2000 employees and has operations across India, USA France, and Canada. Centum revenue is 150 million USD and has been recognized by World Economic Forum as a global growth company and Forbes Asia featured Centum as Asias 200 Best Companies under a Billion. CENTUM EMS The Electronics Manufacturing Services business unit addresses high -technology high-reliability complex products in the defence, aerospace, industrial, medical, automotive and transportation segments. The offerings include build to print, PCBA, Box build, system integration, test, environmental screening services. Job Description What You'll Do- Project Management: Lead and manage NPI projects from concept to production readiness, ensuring timely execution and customer satisfaction. \ Customer Coordination: Act as a primary point of contact for customers during the NPI phase; understand requirements and translate them into internal deliverables. Cross-functional Collaboration: Coordinate with engineering, sourcing, quality, manufacturing, and supply chain teams to ensure alignment and readiness. Process Development: Define and optimize manufacturing processes and workflows for new products. DFX Reviews: Facilitate Design for Manufacturability (DFM), Design for Assembly (DFA), and Design for Testability (DFT) reviews with internal teams and customers. Documentation: Ensure preparation and review of all technical documentation, including BOMs, process flows, FMEA, control plans, and work instructions. Pilot Builds: Plan and execute prototype and pilot builds; collect data to improve yield and performance. Change Management: Implement and manage engineering change orders (ECOs) and revisions during the NPI lifecycle. Risk Management: Identify potential risks during NPI and develop mitigation strategies. Continuous Improvement: Drive initiatives for continuous improvement in time-tomarket, product quality, and cost efficiency. Who You Are? Overall, 15 -20 years of Experience in NPI, Technology Transfer, Manufacturing and Engineering is required. Good communication and presentation skills. Problem solving abilities. Leadership qualities and interpersonal skills. Good skill of MS Office Educational Background: BE – EEE / ECE.

About Company Espressif Systems (688018) is a public multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power IoT solutions. We have created the popular ESP8266 and ESP32 series of chips, modules and development boards. By leveraging wireless computing, we provide green, versatile and cost-effective chipsets. We have always been committed to offering IoT solutions that are secure, robust and power-efficient. By open-sourcing our technology, we aim to enable developers to use Espressif’s technology globally and build smart connected devices. In July 2019, Espressif made its Initial Public Offering on the Sci-Tech Innovation Board (STAR) of the Shanghai Stock Exchange (SSE). Espressif has opened a Technology Center in Pune (Baner), India, which will focus on embedded software engineering and IoT solutions development for our growing customers. About Role Job Responsibilities Digital IP design Perform Lint/CDC/LEC/DFT/Low-Power analysis Module level synthesis and timing constraints Must have worked on ARM/RISC-V CPU based designs Familiarity with FPGA/Silicon validation using C based tests and usage of standard debugging tools Qualifications M.Tech/B. Tech in the field of VLSI/Electronics engineering with 4 to 8 years of experience. Proficiency in System Verilog for RTL logic design and verification. Strong understanding of CPU pipeline and computer architecture is a must. EDA tool knowledge of Design Compiler, PrimeTime is preferred. Automation skills in PERL and/or TCL and/or Shell* is an added plus. Team player, with good problem solving and communication skills. What to expect from our interview process The first step is to email your resume or apply to the relevant open position, along with a sample of something you have worked on such as a public GitHub repo or side project etc. Next, post shortlisting your profile recruiter will get in touch with you via a mechanism that works for you e.g. via email, phone. This will be a short chat to learn more about your background and interests, to share more about the job and Espressif, and to answer any initial questions you have. Successful candidates will then be invited for 2 to 3 rounds of technical interview as per previous round feedback. Finally, Successful candidates will have interview with HR. What you offer us Ability to provide technical solutions, support that fosters collaboration and innovation. Ability to balance a variety of technical needs and priorities according to Espressif’s growing needs. What we offer An open minded, collaborative culture of enthusiastic technologist. Competitive salary. 100% company paid medical/dental/vision/life coverage. Frequent trainings by experienced colleagues and chances to take international trips, attend exhibitions, technical meetups and seminars.

Technical Requirements Excellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team. In-depth knowledge of floor planning, power planning, PNR and signoff checks Strong experience in static timing analysis (STA), timing closure, and signal integrity. Expertise in power optimization techniques, Upf, including clock gating and multi-voltage domain design Proficiency in physical design tools, such as Synopsys ICC2, Primetime, Calibre, Redhawk-SC Scripting skills in Tcl, Python, or Perl to enhance automation and streamline physical design tasks. Familiarity with DRC, LVS, and other physical verification processes. Responsibilities Own the physical design implementation of SoC subsystems, including floor planning, placement, clock tree synthesis (CTS), routing, and optimization to meet PPA goals. Work closely with RTL, DFT and IP teams to ensure seamless subsystem integration and resolve physical design issues that impact overall system performance. Collaborate with the Full Chip physical verification team to resolve DRC, LVS, and antenna rule violations, ensuring compliance with top level Lead clock tree synthesis, manage clock skew, insertion delay, and ensure timing closure across all corners and modes. Address timing violations and signal integrity issues. Implement power-saving techniques, such as power gating, multi-voltage domains, and clock gating, to achieve low-power targets while maintaining performance. Develop and optimize custom scripts in Tcl, Perl, or Python to streamline physical design tasks and improve workflow efficiency. Mentor and guide junior physical design engineers, sharing best practices and providing technical guidance to improve team efficiency and expertise. Experience: 4+ Years Job Location: Bangalore

Job Summary Java development Lead with hands-on coding and solution designing skills for Functions DFT. Candidate should be able to code and lead and formulate the deliveries for DFT Functions Domain. The candidate should develop Applications and enable Development teams with cookie cutter reusable patterns / components for development with end-to-end ownership / life cycle. Candidate should also be able to lead and guide community group contributing for reusable component/library. Key Responsibilities Have a strong sense of responsibility and ownership and contributes heavily to technical evaluations, decisions, software design & development activities. Contributes to building prototypes or proof of concepts and translates them to production grade applications or reusable components. Keeping track of industry developments, conducting R&D to incorporate best in class practices and methodologies and sharing the same with team and stakeholders. Leading the end-to-end delivery with adherence to timelines & agile practices. Participate in code reviews, assist & mentor team on technical aspects. Key Expertise Expertise in programming language – Java Expertise in web application development using one or more frameworks such as Spring boot, Quarkus, node.js, go lang. Proficient in designing and developing applications using microservices, cloud native architecture & REST API. Expertise in API design and is proficient in applying various design patterns. Experience on ES6, HTML5, React, Redux, JavaScript MVC patterns / frameworks and CSS pre-processers and strategies for scalable CSS, Babel and Webpack. Strong expertise in one or more databases – RDBMS & NoSQL. Strong coding, debugging, profiling, testing and documentation skills. Proficient in version control – GitHub / bitbucket and code reviews. Strong in one or more container ecosystem – Kubernetes, EKS, AKS. Experience in one or more messaging, streaming systems – Kafka, RabbitMQ. Strong in one or more cloud computing platforms – AWS, GCP, Azure. Experience in creating high level architecture & design diagrams. Strong knowledge in CI/CD - ADO Excellent knowledge of Scrum methodology and related processes. Excellent communication and leadership skills. Regulatory & Business Conduct Display exemplary conduct and live by the Group’s Values and Code of Conduct. Take personal responsibility for embedding the highest standards of ethics, including regulatory and business conduct, across Standard Chartered Bank. This includes understanding and ensuring compliance with, in letter and spirit, all applicable laws, regulations, guidelines and the Group Code of Conduct. Effectively and collaboratively identify, escalate, mitigate and resolve risk, conduct and compliance matters. Key stakeholders Enterprise Architects Technology Delivery teams Business Product owners Skills And Experience Java Web application development using one or more frameworks such as Spring boot, Quarkus, node.js, go lang Knowledge on ES6, HTML5, Lit, React, Redux, JavaScript MVC patterns / frameworks and CSS pre-processers and strategies for scalable CSS, Babel and Webpack Experience in one or more container ecosystem – Kubernetes, Openshift, EKS, AKS One or more container ecosystem – Kubernetes, Openshift, EKS, AKS Communication Skills High level architecture & design diagrams Qualifications Minimum Qualifications Bachelor’s in computer science, software engineering or related technical field. 8+ years of relevant work experience. Experience in one or more following: designing distributed systems, designing scalable enterprise applications, application security, full stack development (is a plus). Certification Graduate in Computer Science or related courses Certification on Java, Architecture, Cyber Security, Cloud will be an added advantage Languages JAVA, JAVA SCRIPT About Standard Chartered We're an international bank, nimble enough to act, big enough for impact. For more than 170 years, we've worked to make a positive difference for our clients, communities, and each other. We question the status quo, love a challenge and enjoy finding new opportunities to grow and do better than before. If you're looking for a career with purpose and you want to work for a bank making a difference, we want to hear from you. You can count on us to celebrate your unique talents and we can't wait to see the talents you can bring us. Our purpose, to drive commerce and prosperity through our unique diversity, together with our brand promise, to be here for good are achieved by how we each live our valued behaviours. When you work with us, you'll see how we value difference and advocate inclusion. Together We Do the right thing and are assertive, challenge one another, and live with integrity, while putting the client at the heart of what we do Never settle, continuously striving to improve and innovate, keeping things simple and learning from doing well, and not so well Are better together, we can be ourselves, be inclusive, see more good in others, and work collectively to build for the long term What We Offer In line with our Fair Pay Charter, we offer a competitive salary and benefits to support your mental, physical, financial and social wellbeing. Core bank funding for retirement savings, medical and life insurance, with flexible and voluntary benefits available in some locations. Time-off including annual leave, parental/maternity (20 weeks), sabbatical (12 months maximum) and volunteering leave (3 days), along with minimum global standards for annual and public holiday, which is combined to 30 days minimum. Flexible working options based around home and office locations, with flexible working patterns. Proactive wellbeing support through Unmind, a market-leading digital wellbeing platform, development courses for resilience and other human skills, global Employee Assistance Programme, sick leave, mental health first-aiders and all sorts of self-help toolkits A continuous learning culture to support your growth, with opportunities to reskill and upskill and access to physical, virtual and digital learning. Being part of an inclusive and values driven organisation, one that embraces and celebrates our unique diversity, across our teams, business functions and geographies - everyone feels respected and can realise their full potential. Recruitment Assessments Some of our roles use assessments to help us understand how suitable you are for the role you've applied to. If you are invited to take an assessment, this is great news. It means your application has progressed to an important stage of our recruitment process. Visit our careers website www.sc.com/careers

ASIC DFx - MTS Silicon Design Engineer New Dehli, India Engineering 66377 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFx - MTS SILICON DESIGN ENGINEER THE ROLE: AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications. Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS. Work with multi-functional teams and handling schedules Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Minimum 8 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus. Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Good understanding of RTL quality checks such as SGLINT, SGDFT, CDC, RDC etc Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience with accelerator architectures and data center workloads. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Preferred qualifications: 2 years of experience post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the job In this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Job description: Architecture and design of digital blocks for integration CMOS IC’s Specification and design of digital blocks at RTL level and addition of DfT concept onto the design Synthesis, block verification and gate level analysis of implemented digital blocks for on-silicon integration Implementation and verification of ECO’s on existing designs Technically lead digital design tasks in strong cooperation with project technical lead and project manager Creation and patenting of new IP Profile description: Successfully completed university degree in Electronics or comparable Extensive years of experience in digital design with hands-on experience on relevant design/simulation/synthesis tools Knowledge of RTL design with HDL (Verilog/VHDL) for integrated devices. Knowledge of relevant digital design flow tools for synthesis, LEC (logic equivalence check), CDC/RDC (clock/reset domain crossing), linting, synthesis constraining Knowledge of advanced digital verification tools and methodologies (e.g UVM) would be a plus Strong team player, committed to deadlines and development discipline, with a visible “what’s best for the company” mentality Soi Kim Kee suki.kee@ams-osram.com +65 () 62402395

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFx - MTS SILICON DESIGN ENGINEER The Role AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications. Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS. Work with multi-functional teams and handling schedules Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Minimum 8 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus. Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Good understanding of RTL quality checks such as SGLINT, SGDFT, CDC, RDC etc Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Soc Power Architecture - Power Artist/PTPX Hyderabad, India Engineering 66223 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ The Role: We are looking for an experienced engineer to join the SOC Power Modeling team in the AMD Client Computing and Graphics group. This role involves collaboration with multiple engineering teams including SoC architecture definition, IP design, integration/physical design, verification, and platform architecture. Contributions have a direct impact on the power & performance of AMD’s Client products. The Person: The candidate should have SOC design process experience from front end to tapeout. The candidate will work closely with the SOC design teams on RTL and emulation-based power estimation, simulation and design data extraction. The candidate must be organized, self-motivated and able to work effectively on teams large and small across multiple sites. He or she must be able to prioritize assignments and drive them to completion. Good verbal and written communication skills are helpful for technical discussions with team members across the globe. Key Responsibilities: Work with front end RTL, DFT, Synthesis, and Physical design teams in the development of power intent (UPF) design at SoC level. Work with emulation team on power estimates during the pre-silicon design process using Power Artist/PTPX emulation environments and ensure power objectives and goals are met. Work with RTL and physical design teams to generate data on design impact from clock and power gating, device type mix and physical implementation options. Track IP power development through the design cycle ensuring it meets power budgets - leakage/dynamic at every milestone. Work with design verification in validating low power design features at SoC and IP level. Preferred Experience Experience with Synopsys EDA tools, particularly PtPx/Power Artist. Understanding of hardware emulation process, stimulus and EDA flows. Experience with Tcl and Python based scripting. Experience with UPF. Academic Credentials Master or Bachelor of Science degree in Electrical Engineering. 3+ years of experience. #LI-RR1 #LI-Hybrid AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Location Bangalore, Karnataka, India Employment Type Full time Location Type Hybrid Department R&D - HW Silicon Engineering At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. DFT ATPG Engineer D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs . We’re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! Your Responsibilities Will Include: Partitioning for ATPG and hierarchical approaches. ATPG compression and serialization. RTL-Scan insertion and design rule fixing. STA constraints, Primetime execution, and timing exception flow. Interfacing with ASIC design teams to ensure DFT design rules and coverages are met. Generating high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models using on-chip test compression techniques. Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis. Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Being responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE. Having experience with state-of-the-art industry-standard DFT tools. Being hands-on from the "nitty gritty" details to high-level planning. Minimum Qualifications: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Job description ROLES & RESPONSIBILITIES: Responsible to check the quality of INCOMING material (raw material, samples, semi-finished goods), in-process goods, finished goods at every stage of production & before client delivery Implement Quality Process for continual improvement of the process Responsible to support Quality management system, vendor audit, internal audit, internal audit ISO-9001. Accountable and responsible for training operators/ engineers on Quality standards. Work closely with PPC & PE team to generate manufacturing inspection test plans, ensure good quality products are produced and minimize non-conformance of products Liaise with team members to ensure smooth introduction of new products and processes Conduct audits & create reports to determine proper corrective and preventive actions. Analyze root causes and implement corrective actions for processes or parts that have concerns Analyze customer warranty returns and implement corrective and preventive actions. Responsible for suggesting and correcting issues at the installation site Responsible for material inspection / test at vendor or supplier location Responsible to follow the ISO process and adhere to the defined procedures Reporting responsibilities – Daily/ weekly/ monthly quality issues and analysis. Maintain and update quality tracker and provide suggestions for quality improvement Preparation of documentation for any product quality change Calibration and certification of test & measuring instruments, tools. Certification of Products Viz., BIS and other applicable industry standards Responsible to communicate with both Technical & Non-technical people effectively Responsible for test fixtures & jigs. Implementation of FMEA, PFMEA, DFM & DFT, Kaizen, 5S, CSO, 7QC Tools, and CAPA, Knowledge of PPAP, APQP for process capability analysis. For mechanical quality Engineer Responsible for plastic, sheet metal, engineering materials, welding, finishing process. QUALIFICATION & SKILLS: BE (or Diploma) Mechanical 0-2 yrs experience in Quality Control/ Assurance department Must have good knowledge of plastic, sheet metal, engineering materials, welding, finishing process. Experience in manufacturing industry is preferred Experience in LED Lighting OR Auto Industry would be an added advantage Candidate needs to be enthusiastic, self-motivated and passionate about their work Should have good communication skills and be able to speak English, Hindi & Kannada fluently Job Type: Full-time Pay: ₹250,000.00 - ₹350,000.00 per year Benefits: Health insurance Provident Fund Schedule: Morning shift Night shift Rotational shift Supplemental Pay: Yearly bonus Work Location: In person

Job Description. Arm’s CE-Systems DFT team implements DFT for test chips and hard macros to prove out Arm soft IP power, performance, area, and functionality within the context of an SoC using the latest DFT and process technologies. The DFT team works closely with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE.. Responsibilities. Architect, implement, and validate innovative DFT techniques on test chips as well as hard macros. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.. Required Skills And Experience. This role is for a Senior Principal DFT Engineer with 15+ years of experience in Design for Test. Experience coding Verilog RTL, TCL and/or Perl. Proficient in Unix/Linux environments. Core DFT skills considered for this position should include some of the following Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics. Bachelors or Master’s degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field. “Nice To Have” Skills and Experience. Familiarity with IEEE 1149, 1500, 1687, 1838. Synthesis & Static Timing Analysis. Familiarity with SoC style architectures including multi-clock domain and low power design practices.. Validated understanding of Siemens DFT tools. Familiarity with Arm IP like the following Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug. Experience with 2.5D and 3D test. Ability to work both collaboratively on a team and independently. Hard-working and excellent time management skills with an ability to multi-task. An upbeat demeanor to working on exciting projects on the cutting edge of technology. Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools. In Return. We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding!. Partner and customer focus. Teamwork and communication. Creativity and innovation. Team and personal development. Impact and influence. Deliver on your promises. Accommodations at Arm. At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.. Hybrid Working at Arm. Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.. Equal Opportunities at Arm. Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.. Show more Show less

To work as a Frontend engineer and taking care of Synthesis, LEC, CLP and Power Analysis for complex SoC projects.. Job Description. In your new role you will:. Implement high-performance, low-power, and area-efficient digital designs.. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis.. Optimize designs for power, performance, and area, and meet PPA goals.. Power analysis using PT-PX or equivalent flow.. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs.. Define and evaluate constraints and signoff Test/DFT mode timing requirements.. Your Profile. You are best equipped for this task if you have:. Strong fundamentals and experience in Synthesis and STA domains.. Write and implement block level and top-level timing constraints for Synthesis. Optimize designs for power, performance, and area, and meet design goals.. Knowledge on Power analysis and PT-PX flow.. Understanding of DFT flows, including scan insertion.. Write and evaluate Test/DFT mode timing constraints.. Thorough with Logic Equivalence Check debug capability.. Well known about UPF concepts and Low Power Checks at block and full chip level.. Defining and verification of STA constraint for Functional and Test/SCAN Modes.. Defining PVT’s corners required for covering all desired scenarios for a design. Knowledge on OCV/AOCV/POCV derates.. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues.. VASTA timing closure based on chip IR drop.. Knowledge on signal SI analysis and PT-PX flow.. Contact:. swati.gupta@infineon.com. #WeAreIn for driving decarbonization and digitalization.. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.. Are you in?. We are on a journey to create the best Infineon for everyone.. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills.. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.. Click here for more information about Diversity & Inclusion at Infineon.. Show more Show less

Principal DFT Engineer (MBIST) in Pune, MH, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: The ideal candidate will work with multi-functional global teams to design, implement and verify Boundary Scan, ATPG (Stuck-AT/AT-Speed) SCAN, MBIST, IO BIST and JTAG/IJTAG DFT features on our next generation highly complex server class processor products. Will work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug. What youll achieve: DFT features like EDT, SSN, shared bus based MBIST insertion, ijtag, simulation and debug on RTL and gates netlist Boundary Scan insertion, simulation and verification Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis Scan ATPG pattern generation, simulation and debug on RTL and gates netlist Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor, Cadence, Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data Bachelors degree & 8 years of related experience or Masters degree & 6 years of related experience Expert with methods and techniques to design, implement and verify regular and shared bus based Memory BIST on repairable and non-repairable memories using Electrical fuses. Expert knowledge and practical work experience partnering with designers to implement highly customized and tools-driven MBIST solutions. Solid understanding of MBIST algorithms needed for 5nm and lower technology nodes and ability to code new algorithms, operation sets supporting tool driven solutions. Experience in implementing EDT, SSN, boundary scan, jtag/ijtag features. Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level Hands on experience in the usage of industry standard tools, like Siemens Tessent Shell flow, or Synopsys SMS/SHS flow Expert understanding tradeoffs to optimize coverage and test time reduction with the ability to foresee physical implementation and timing challenges during early development. Experience in working with physical design teams to support STA constraints, reviewing timing reports. Expert in using silicon debug/diagnosis tools to root cause silicon bringup and production test issue. Experience in setting up and running Scan DRC flows in RTL. Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl. Experience in revision control systems like GIT, perforce etc.. Needs in depth experience in stuck at, transition delay, path delay, etc. coverage loss analysis and identifying solutions to improve test coverage Experience in leading the effort to derive cell aware fault models and develop necessary flows to generate ATPG and to support silicon debug. Good knowledge of functional safety, clock domain crossing analysis, logic synthesis and scan insertion At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.