1109 Dft Jobs - Page 18

About Company Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. We’re Hiring – DFT (Design for Test) Engineer Locations: Bangalore | Hyderabad | Cochin | Pune Experience: 7 to 12 Years Qualification: Bachelor’s in Computer Science / Electronics / Electrical Engineering Key Responsibilities Collaborate with ASIC design teams to ensure DFT rules and coverage are met Generate high-quality ATPG patterns for SAF/TDF using on-chip test compression Work on MBIST verification and repair using tools like Mentor Run ATPG & MBIST verification using unit delay and min/max corner simulations Deliver manufacturing test patterns for ATE in collaboration with product/test teams Support post-silicon debug and issue resolution Develop diagnostic tools for ATPG, MBIST, and ATE bring-up Enhance and maintain scripting for DFT flows Preferred Experience & Skills Hands-on experience with Full Chip DFT and Silicon Validation Strong understanding of DFT concepts, ATPG coverage, yield enhancement, and silicon debug Proficient in Memory test & failure analysis Tool knowledge: ATPG – TestKompress MBIST – MentorETVerify Simulation – VCS (preferred), ModelSim Scripting in Perl, Shell is a plus Comfortable working in international teams with strong communication skills Ability to multitask and work on high-priority designs in parallel Quick learner, adaptable to new tools and methodologies Qualifications Bachelor’s degree in Computer Science, Electronics, or Electrical Engineering Minimum of 7 years of relevant experience in DFT Strong analytical and troubleshooting skills Ability to work independently and as part of a team Excellent verbal and written communication skills Experience with industry-standard tools and methodologies Benefits and Perks Competitive Salary Good work culture Skills: memory test,dft,failure analysis,atpg,communication,scripting,silicon validation,mbist

Job Summary Understand requirement, prepare and execute tests and adhere to all test controls Good experience in Integration Testing, System Testing, API Testing. Automate functional test cases They will ensure that teams can validate the quality of the product delivered to the stakeholders as per group standards. Works within scrum and reports to Test manager Must Have Technical Skills Understand BDD and functional test automation Have demonstrable programming knowledge in one OOP language, preferably Java Ability to coach, and guide junior test engineers Full understanding of the SDCLC especially Agile methodologies Familiar with test management process ISTQB or Agile Test Certified Banking domain knowledge is a plus Understanding of continuous integration and deployment processes, or have the desire to learn Key Responsibilities Strategy Identify and analyse issues in requirements, design specifications, application architecture as well as product documentation. Develop test specifications based on various requirement documents within schedule constraints. Develop test bed and/or test data and verify test environments (based on project requirements). Develop regression packs to ensure that requirements from previous scope are still functioning as before. Perform functional and technical test execution activities (automated testing, where applicable) as per project engagement. Identify and is familiar with negative testing, to be included in the developed test specifications. Report and update test status promptly and accurately. Conduct reviews and inspections of project deliverables (for small size projects). Able to contribute to multiple projects, whilst still ensuring process compliance and deliverables are adhere to. Able to work independently as well as a team in providing out-of-the box solution if required. Business Constant communication and follow up with various stakeholders during test planning and execution phases. Enable project meetings to provide feedback and statistics of the project in relation to the test quality. Processes Good understanding and able to apply test processes laid down within the test team, and/or standards as defined by project and SCB. Understand that traceability and reporting are extremely important in highly compliant environments and be prepared to engrain these practices in team’s ways of working People & Talent Ability to work in a highly compliant landscape and work within the boundaries of globally defined software quality management practices and policies Able to work independently in scrum team as a tester, but maintain good collaboration with other team members and stake holders. Risk Management To collaborate/troubleshoot with the development and delivery team for technical issues that requires result analysis and feedback. Raise any concerns at the right time to Test manager and delivery manager Governance Effectively and collaboratively identify, escalate, mitigate and resolve risk, conduct and compliance matters. Regulatory & Business Conduct Display exemplary conduct and live by the Group’s Values and Code of Conduct. Take personal responsibility for embedding the highest standards of ethics, including regulatory and business conduct, across Standard Chartered Bank. This includes understanding and ensuring compliance with, in letter and spirit, all applicable laws, regulations, guidelines and the Group Code of Conduct. Key stakeholders Engineering leads (Scrum master), Test manager Our Ideal Candidate Functional testing Automation testing selenium and cucumber Test management SDLC process Agile team work Competencies Action Oriented Collaborates Customer Focus Gives Clarity & Guidance Manages Ambiguity Develops Talent Drives Vision & Purpose Nimble Learning Decision Quality Courage Instills Trust Strategic Mindset Technical Competencies: This is a generic competency to evaluate candidate on role-specific technical skills and requirements About Standard Chartered We're an international bank, nimble enough to act, big enough for impact. For more than 170 years, we've worked to make a positive difference for our clients, communities, and each other. We question the status quo, love a challenge and enjoy finding new opportunities to grow and do better than before. If you're looking for a career with purpose and you want to work for a bank making a difference, we want to hear from you. You can count on us to celebrate your unique talents and we can't wait to see the talents you can bring us. Our purpose, to drive commerce and prosperity through our unique diversity, together with our brand promise, to be here for good are achieved by how we each live our valued behaviours. When you work with us, you'll see how we value difference and advocate inclusion. Together We Do the right thing and are assertive, challenge one another, and live with integrity, while putting the client at the heart of what we do Never settle, continuously striving to improve and innovate, keeping things simple and learning from doing well, and not so well Are better together, we can be ourselves, be inclusive, see more good in others, and work collectively to build for the long term What We Offer In line with our Fair Pay Charter, we offer a competitive salary and benefits to support your mental, physical, financial and social wellbeing. Core bank funding for retirement savings, medical and life insurance, with flexible and voluntary benefits available in some locations. Time-off including annual leave, parental/maternity (20 weeks), sabbatical (12 months maximum) and volunteering leave (3 days), along with minimum global standards for annual and public holiday, which is combined to 30 days minimum. Flexible working options based around home and office locations, with flexible working patterns. Proactive wellbeing support through Unmind, a market-leading digital wellbeing platform, development courses for resilience and other human skills, global Employee Assistance Programme, sick leave, mental health first-aiders and all sorts of self-help toolkits A continuous learning culture to support your growth, with opportunities to reskill and upskill and access to physical, virtual and digital learning. Being part of an inclusive and values driven organisation, one that embraces and celebrates our unique diversity, across our teams, business functions and geographies - everyone feels respected and can realise their full potential. Recruitment Assessments Some of our roles use assessments to help us understand how suitable you are for the role you've applied to. If you are invited to take an assessment, this is great news. It means your application has progressed to an important stage of our recruitment process. Visit our careers website www.sc.com/careers

About Company Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. We’re Hiring – DFT (Design for Test) Engineer Locations: Bangalore | Hyderabad | Cochin | Pune Experience: 7 to 12 Years Qualification: Bachelor’s in Computer Science / Electronics / Electrical Engineering Key Responsibilities Collaborate with ASIC design teams to ensure DFT rules and coverage are met Generate high-quality ATPG patterns for SAF/TDF using on-chip test compression Work on MBIST verification and repair using tools like Mentor Run ATPG & MBIST verification using unit delay and min/max corner simulations Deliver manufacturing test patterns for ATE in collaboration with product/test teams Support post-silicon debug and issue resolution Develop diagnostic tools for ATPG, MBIST, and ATE bring-up Enhance and maintain scripting for DFT flows Preferred Experience & Skills Hands-on experience with Full Chip DFT and Silicon Validation Strong understanding of DFT concepts, ATPG coverage, yield enhancement, and silicon debug Proficient in Memory test & failure analysis Tool knowledge: ATPG – TestKompress MBIST – MentorETVerify Simulation – VCS (preferred), ModelSim Scripting in Perl, Shell is a plus Comfortable working in international teams with strong communication skills Ability to multitask and work on high-priority designs in parallel Quick learner, adaptable to new tools and methodologies Qualifications Bachelor’s degree in Computer Science, Electronics, or Electrical Engineering Minimum of 7 years of relevant experience in DFT Strong analytical and troubleshooting skills Ability to work independently and as part of a team Excellent verbal and written communication skills Experience with industry-standard tools and methodologies Benefits and Perks Competitive Salary Good work culture Skills: memory test,dft,failure analysis,atpg,communication,scripting,silicon validation,mbist

Institute Description Indian Institute of Science Education and Research (IISER), Thiruvananthapuram is an autonomous institution dedicated to scientific research and science education of international standards. Role Description This is a full-time on-site role for a Postdoctoral Researcher at IISER Thiruvananthapuram. The Postdoctoral Researcher will be responsible to utilize Machine Learning (ML) and DFT to predict the ligand effects in cross-coupling reactions. Qualifications Ph.D. in a related field. Experience in ML and experience in DFT are not compulsory. Basic in PyTorch and build a neural network. Apply Here https://forms.gle/3ZMfRtbzdPvnVVnW7

S MTS SOFTWARE SYSTEMS DESIGN ENGINEER THE ROLE: AMD is looking for an experienced engineer for an exciting role in Server CPU software development team. This person will be a member of a core team and will work with the latest hardware and software technology. The person will interact closely with key AMD technical experts to ensure the best possible performance and results on AMD platforms. THE PERSON: The successful candidate for this position will be interacting with software and hardware technologists working across many locations. This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. KEY RESPONSIBILITIES: Optimization/development of the CPU performance stack (applications, libraries) for AMD server and workstation CPUs Analyze and solve performance, scalability bottlenecks when code is running on multi-core, multi-node deployments. Problem solving across multiple software layers, (user space, kernel, applications, libraries) and hardware. Innovate and publish papers, patents and participate in technical conferences to advance AMD technologies. Continuously learn and grow along with evolving X86 server CPU architecture and application landscape. PREFERRED EXPERIENCE: Image processing skills: Color format conversions, Image Filtering and Enhancement operations, Morphological operations, Image transforms and statistical operations. Good understanding in Image Detection, Segmentation, Recognition, Restoration and Medical Imaging. Knowledge in Signal Processing theory like Sampling, Quantization, DFT and FFT. Multi-threaded FFT computing, Distributed FFT computing Very strong data structure and algorithmic skills. Experience in identifying performance bottlenecks, and designing/implementing optimizations to relieve analyzed bottlenecks. Strong experience in software development using C/C++ and debugging skills on multicore systems (preferably using OpenMP). Experience in performance analysis for data center, HPC (High Performance Computing), MPI (Message passing Interface) applications. Experience in x86 (or other architecture based) optimizations. Understanding of Cache sub-system, Instruction Set Architecture, pipeline (for any CPU). Bonus skills: Experience on Intel MKL libraries, Linear Algebra, x86 assembly programming (vector/SIMD), porting source code from Linux to Windows, development on Windows servers Knowledge of one or more CPU Profiling tools

floor planning, bump planning, routing, power grid design, clock design, optimization for high-speed digital circuits high-speed digital layouts, DDR and other high-speed interfaces EDA tools for chip-level physical verification (DRC, LVS, ERC) Accessible workspace Food allowance Health insurance Annual bonus Provident fund

Role & responsibilities Leading DFT ATPG implementation, integration and verification of System-on-Chip (SoC) from initial specification till tapeout and production. Ensure Test Coverage Goals are met at SoC Level. Addressing test quality targets in DFT architecture and test pattern generation. Leading various aspects of Test architecture including MBIST, Scan & ATPG. Work with different functions like front-end design, verification and physical design to ensure production quality silicon. Specific Knowledge/Skills Master/Bachelors Degree in Electrical/Electronic Engineering. Experience of 6 to 10 Years in DFT with successful delivery of production quality chips. Senior SoC DFT engineers, with experiences in all aspects of DFT, including MBIST, scan & ATPG, logic BIST. Good understanding of design flow from specification / micro-architecture definition to design and verification, timing analysis, and physical design. Self-motivated. Excellent written and verbal communication skill. Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components. Should be a team player and willing to work with cross functional teams in issues resolution. Preferred candidate profile Perks and benefits

Job Title: Physical Design Engineer Company: Wipro Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities: End-to-end ownership of chip-level and block-level floor planning . Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis , DRC/LVS closure , and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required: Strong experience in chip-level and block-level physical design . Hands-on expertise with Innovus and/or Fusion Compiler . Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Interview Process: L1 Technical Round – Virtual L2 Final Round – Virtual Job Types: Full-time, Permanent Pay: ₹3,000,000.00 - ₹7,500,000.00 per year Schedule: Monday to Friday Ability to commute/relocate: Pune, Maharashtra: Reliably commute or planning to relocate before starting work (Preferred) Application Question(s): End-to-end ownership of chip-level and block-level floor planning? Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation? Perform timing analysis, DRC/LVS closure, and physical verification? Work Location: In person

Job Requirements Assist in Design for Testability (DFT) activities for VLSI chip designs. Support scan insertion, ATPG pattern generation, and simulation tasks. Work with senior engineers to validate test coverage and resolve issues. Learn and apply industry-standard DFT tools and methodologies. Prepare basic documentation and status reports as required. Bachelor’s degree in Electronics, Electrical, or related field. Basic understanding of digital design and DFT concepts. Familiarity with Verilog or VHDL is an advantage. Good analytical and communication skills Work Experience Assist in Design for Testability (DFT) activities for VLSI chip designs. Support scan insertion, ATPG pattern generation, and simulation tasks. Work with senior engineers to validate test coverage and resolve issues. Learn and apply industry-standard DFT tools and methodologies.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are looking for an experienced and driven Senior Test Manager to oversee the test strategy and execution for DCDC converters and Power Management IC (PMIC) solutions. This leadership role requires in-depth technical knowledge of analog/mixed-signal testing, volume production, and collaborative development processes. The successful candidate will lead a test team, working closely with design, validation, product engineering, and manufacturing teams to ensure flawless silicon delivery Key Responsibilities •Own and lead test development from design handoff to high-volume production for DCDC and PMIC products. •Develop and implement robust test strategies including ATE planning, silicon characterization, qualification, and production ramp-up. •Define Design-for-Test (DFT) requirements and partner with design teams to ensure optimal test coverage. •Lead the creation of test hardware (load boards, probe cards) and software (test code, automation scripts). •Continuously optimize test cost, cycle time, and yield performance. •Oversee reliability, corner case, and qualification testing for automotive, industrial, or consumer product standards. •Coordinate with foundries and test partners to ensure seamless test flow and high-quality production output. •Mentor and develop test engineers; foster a high-performance, innovative team culture. •Ensure compliance with quality standards such as AEC-Q100 for automotive-grade products. Qualifications •Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) with over 12 years of test engineering experience (preferably in PMIC/DCDC). •Strong foundation in analog/mixed-signal testing, especially for LDOs, DC-DC converters, and current/voltage monitors. •Experience in writing and debugging test programs, performing silicon validation, and executing production ramps. •Understanding of power management architectures, board-level integration, and thermal dynamics. •Knowledge of scripting and automation tools (Python, Perl, C/C++). •Track record of working effectively in global, cross-functional teams. •Experience with automotive semiconductor testing is highly desirable. •Strong interpersonal, leadership, and communication skills. Desirable Skills •Familiarity with ISO26262 and functional safety verification. •Wafer-level testing experience •Proficiency with lab instruments like oscilloscopes, SMUs, and electronic loads We recognize and appreciate the value and contributions of individuals with diverse backgrounds and experiences and welcome all qualified individuals to apply. Equal Opportunity Employer: Disability/Veteran

Expertise and strong hands-on experience in RTL design using System Verilog or VHDL Digital system architecture, Processor subsystem architecture and block definition,complex SoCs, RTL design quality analysis – Lint, CDC, RDC,DFT,simulation,

I am hiring a junior research fellow (JRF) for an ANRF-funded project. The project involves molecular dynamics (MD) and density functional theory (DFT) simulations for Shape Memory Alloys. Interested candidates with a valid GATE score are encouraged to send their CVs directly to me at shivamt@iitk.ac.in . Prior experience with Python, DFT, and MD will be helpful.

Renesas Analog and Connectivity Business Unit (A&C) is seeking an experienced Test Engineer to join our team. This role offers a unique and exciting opportunity to work on the development of state-of-the-art Memory Interface Devices. You will be part of a cross-functional team, driving the product from conception to volume production. Key Responsibilities: Develop test programs for characterization, production, and wafer sort using Advantest 93K platform. Design test hardware for high-speed applications. Participate in testability reviews with DFT/DFM teams to enhance yield and test methodologies. Test pattern conversion to ATE formats. Implement best practices for robust test solutions, including GR&R, HTOL, and Characterization procedures. Qualifications Test Engineer with 10+ Years experience developing hardware and software at Wafer Sort and Final Test for High-Speed products. 10+ Years of experience on Advantest 93K. FPGA knowledge is a plus. Strong analytical and problem-solving skills. Effective communication and teamwork abilities. Self-starter, motivated, and able to work independently. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Roles and Responsibility 3+ years to 10 yrs design experience Experience with owning chip level DFT and Post Silicon debug / analysis Understanding of DFT architectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification. Must have experience generating scan patterns and coverage statistics for various fault models like stuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E-fuse etc.). Experience debugging tester failures of scan patterns, diagnosis and pattern re-generation. Understanding generation of functional patterns for ATE Knowledge of at least any one of an industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools, etc) Design experience in MBIST / LBIST is an added advantage. Good understanding of constraints development for Physical Design Implementation / Static Timing Analysis. Preferred Skills/ Experience Experience with TCL / Perl is preferred. Understanding of IC design with Analog circuits and it s design cycles is an added advantage. Effective communication skills to interact with all stakeholders. Team and People Skills: The candidate should have good people skills to work closely with the systems, analog, layout and test team Must be highly focused and remain committed to obtaining closure on project goals

Job Title: General Manager Purchase Electronics Components Manufacturing Location: Noida, Uttar Pradesh Experience Required: 18 to 23 Years Salary: Up to 40 LPA Industry: Electronics / EMS / Automotive Electronics / Consumer Electronics Position Overview: We are looking for a seasoned leader to head our Electronics Components Manufacturing Division . The ideal candidate should have deep expertise in SMT, PCBA, component assembly , and high-volume electronics production , with strong business acumen to drive productivity, cost optimization, and delivery excellence. Manufacturing Operations Leadership: Lead and manage end-to-end electronics manufacturing operations including SMT lines, DIP, wave soldering, testing, and packaging . Ensure high throughput, efficiency, and productivity through Lean Manufacturing, TPM, and Six Sigma practices. Own production planning, scheduling, and resource allocation in alignment with demand forecasts. Quality & Process Control: Drive stringent process controls, inline inspection (AOI/X-ray), ICT, FCT, and yield improvement initiatives . Ensure compliance with ISO 9001, IATF 16949, ISO 14001 , and other customer-specific quality standards. Implement zero-defect culture and structured problem-solving (RCA, 8D, CAPA). Technology & Engineering: Lead introduction and scale-up of new technologies including automation, robotics, and Industry 4.0 practices. Collaborate with R&D for DFM/DFT reviews and seamless new product introductions (NPI). Optimize machine layouts, material flow, and equipment efficiency (OEE). People & Cost Management: Manage a workforce of 300 800+ people, including engineers, supervisors, operators, and support staff. Lead training and competency development across levels. Drive cost reduction, inventory control, scrap minimization , and utility optimization initiatives. Cross-functional Collaboration: Work closely with procurement, quality, planning, and sales teams for integrated execution. Engage with top leadership for monthly KPIs, plant reviews, and strategic growth initiatives. Key Skills & Expertise: Expertise in electronics components manufacturing , PCBA , SMT/DIP processes , and EMS operations . Strong knowledge of electronics component behavior and manufacturing defects . Excellent leadership, decision-making, and stakeholder management skills. Experience with SAP/ERP , MES systems , and automated production data tracking . Educational Qualification: B.E./B.Tech in Electronics / Electrical / Industrial Engineering. Procurement Strategy, Strategic Sourcing, Vendor Development

In this role you will have the opportunity to Work as Principal Engineer, Quality Assurance accountable for overall product quality of the NPI releases. The Principal Engineer provides independent oversight of the design input process, design V&V activities, design transfer and product realization, and performance in the field to ensure that all design requirements are effectively met. The Principal Engineer also provides analytics to the Business on the efficacy, efficiency of the design and product realization processes. Opportunity to learn End to End product development as Responsible Quality representative driving compliance throughout Product life cycle. We are looking for a dynamic individual to join our Quality and Reliability Engineering team. The candidate is expected to have demonstrated proficiency in the philosophy of Quality. The candidate should demonstrate strong systems engineering fundamentals across all critical engineering domains important to product quality. The candidate should be able to challenge the status quo and be able to appropriately represent the voice of the customer to core teams while making decisions related to product quality. The ideal successful candidate Responsibilities: Responsible for all aspects of product quality from PRD to Production handover for high volume production development until sustaining. Single point of contact, representing and driving quality in all program team meetings. Conduct cross-site, cross-team lessons learned for any Quality issues during development and sustaining phases of Product Life-Cycle Participate in Engineering reviews ( PRD, DFx, Qualification sync, test plan, RDT ) and forecast potential quality risk Perform quality risk assessment to a project and drive for mitigations enabling business, apart from being a gatekeeper Identify process gaps in the Product Life Cycle (PLC) and continuously highlight improvement actions for the execution teams Influence quality culture and mindset across the company and bring in more strategic goals Demonstrated to take data based decisions and resolve contentions Qualifications Bachelor or Masters Degree in Electrical/Electronic based Engineering 10 to 12yrs of certified professional experience in quality engineering Thorough understanding on Product Life Cycle and process-gap identification Exposure to factory processes and hands-on is a big advantage Experience and hands-on in, E2E product development, factory and customer quality Driving product quality and reliability working with CFT, Six sigma GB/BB would be added advantage Design for Quality / Reliability, pFMEA, DFMEA, DFM, DFT, Root cause analysis NPI product development and sustenance Data analysis and data-based decision making and action Process improvements drives for structural quality improvements Influencing CFT for decisions of betterment of quality Good understanding on Program Management Quality challenges and levers Product Qualification cycle RDT & ORT for Electronics Have Demonstrated, Strong teamwork Communication and leadership capabilities in driving cross-functional working teams Strategically and methodically thinking to bring the right balance of product quality in meeting customer and company needs is essential to the success of this role Influencing skills

Forza Silicon is a Business Unit in the Materials Analysis Division of AMETEK, Inc. Forza s history begins at the formation of the CMOS imaging industry where company co-founders, Barmak Mansoorian and Daniel Van Blerkom were a critical part of the Photobit team. Along with Photobit Co-founder, Dr. Eric Fossum, and many others, the team pioneered the development of CMOS imaging technology. Founded in 2001, Forza Silicon has established itself as an innovator and industry leader in the field of mixed-signal IC and CMOS imaging designs that have set the standard of the possible. Primarily through long standing customer relationships and partner referrals, Forza Silicon has grown to where today the company employs one of the industry s largest and most experienced independent CMOS imaging engineering teams. To learn more about Forza Silicon, please go to www.forzasilicon.com Postition Summary: This position will report to the engineering manager and assume engineering responsibility to plan, manage, and oversee detailed sensor design and analysis for custom CMOS image sensors. This position will involve all phases of a design project, including specification and architectural design, detailed circuit design, simulation, layout, verification, and design bring-up and test. The candidate will also be expected to interface extensively with customers and external vendors to communicate specifications, design status, technical details, etc. Primary Responsibilities: Oversee all phases of sensor design: specification, design and tapeout, test, transition to product. Work with customers to understand sensor requirements, translate requirements to detailed specifications, and develop sensor architecture to ensure specifications are met. Work collaboratively with a team of engineers to execute design according to technical specification and schedule in an efficient manner. Perform detailed circuit analysis, design, simulation, layout, verification of mixed-mode circuits Interface with foundry partners to understand process details in support of design implementation, manage pixel design and performance, and oversee tapeout and fabrication. Work with test engineers to facilitate development of test hardware, test plans, and oversee chip bring-up and characterization efforts and results. Position Requirements B.S. in Electrical Engineering (M.S./Ph.D. preferred) 4-7 years of experience in practical analog/mixed signal design for image sensors or other relevant areas. Expert at transistor level circuit design, simulation, verification using modern EDA tools from Cadence, Siemens, Synopsys, etc. Knowledgeable in ADC architectures for image sensor readoutRelevant experience with bandgaps, bias, op-amps, switched-cap circuits, LDOs, PLL, SERDES, high-speed TX, general feedback, and compensation techniques. Expert in noise analysis, transistor/capacitor matching and sources of errors in analog integrated circuits. Experienced in all stages of mixed-signal chip design (preferably in the context of image sensors) flow including DFT, timing analysis, top chip integration and tapeout, and silicon bring up. Experience leading a design team is highly preferred. Excellent communication skills are required.

Work Experience: 7-10 Years Location: Gurugram Qualification: B.Tech/B.E in EE/ECE or relevant (Mandatory) Job Summary: We are seeking a highly skilled and experienced PCB Design Engineer to join our Power Electronics team. The ideal candidate will have a strong background in designing high-performance, reliable PCBs for power electronic systems using Altium Designer. A solid understanding of EMI/EMC design practices, thermal management, and 3D component modelling is essential. Key Responsibilities: Design multilayer PCBs for power electronics applications including DC-DC converters, inverters, SMPS, and motor drives. Create and manage schematic diagrams, PCB layouts, footprints, and libraries using Altium Designer . Optimize layout for signal integrity , power integrity , thermal management , and high-current routing . Ensure compliance with EMI/EMC standards during the design phase, and implement best practices for electromagnetic compatibility. Perform Design Rule Checks (DRC) , Electrical Rule Checks (ERC) , and support DFM/DFT reviews. Collaborate closely with electrical engineers, mechanical engineers, and firmware teams throughout the product development cycle. Integrate 3D models of components and perform mechanical fit checks using Altium’s 3D PCB design tools. Interface with PCB fabrication and assembly vendors for prototyping and production builds. Support prototype bring-up, debugging, and validation in coordination with the test and development team. Maintain documentation for PCB designs including Gerber files, BOMs, assembly drawings, and revision control. Required Qualifications & Skills: Bachelor’s degree in Electronics Engineering or related field. 7 to 10 years of hands-on experience in PCB design , specifically in power electronics applications. Proficiency in Altium Designer (schematic capture, layout, 3D, library management). In-depth knowledge of EMI/EMC design principles , grounding, shielding, and filtering techniques. Experience in designing for high-voltage , high-current , and thermal-critical circuits. Competence in 3D modeling and mechanical integration of PCB assemblies. Strong understanding of IPC standards and PCB manufacturing processes. Excellent analytical and problem-solving skills. Good communication and teamwork skills.

About the Company Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. About the Role Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Responsibilities Own end-to-end SOC RTL delivery while analyzing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains. Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA). Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4. Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Design Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 5+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams.

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs , supporting complex architectures with multi-core, multi-power, and multi-reset domains . Demonstrate strong proficiency with front-end flows , including Lint, CDC, low-power (UPF) checks, synthesis, DFT , and Static Timing Analysis (STA) . Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI , and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4 . Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation , working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 10+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams.

We are a growing talent solutions partner specializing in high-impact recruitment for niche industries. As we expand our presence in the semiconductor domain , we are looking for a strategic leader to head our Semiconductor Hiring Practice — someone who understands the industry's nuances and can drive end-to-end talent strategy, client acquisition, and delivery excellence. Role Overview As the Vertical Head – Semiconductor Recruitment , you will own and drive the recruitment function for this fast-evolving domain. You will be responsible for scaling up the practice through client partnerships, building a high-performance team, and delivering top-tier talent solutions for global and Indian semiconductor clients. Key Responsibilities Strategic Leadership Define and execute the talent acquisition roadmap for the semiconductor vertical Identify market opportunities and create differentiated solutions for niche hiring Drive business planning, forecasting, and budgeting for the vertical Client Acquisition & Relationship Management Develop new business in the semiconductor and fabless/foundry ecosystem across design, manufacturing, packaging, and EDA segments Represent the company in client pitches, capability presentations, and negotiations Maintain and grow long-term relationships with key clients and stakeholders Team Building & Leadership Hire, mentor, and lead a team of recruitment professionals specializing in semiconductor hiring Train the team on domain knowledge, sourcing strategies, and client engagement Establish KPIs, monitor performance, and foster a collaborative, high-performance culture Recruitment Delivery Management Own delivery of mid to senior-level positions across domains like VLSI, Analog/Digital Design, DFT, Embedded Systems, Firmware, Verification, and EDA tools Ensure timely and quality closures through structured sourcing, screening, and interview coordination Optimize recruitment operations, including ATS usage, candidate experience, and reporting Market Intelligence & Innovation Stay updated on trends in semiconductor hiring, talent supply, compensation benchmarks, and skill shortages Collaborate with marketing to build domain-specific campaigns, thought leadership content, and talent communities Desired Profile 8–15 years of experience in recruitment, preferably with a strong focus on the semiconductor, electronics, or embedded tech industry Proven track record in client acquisition , business development , and growing accounts in the technology sector Experience in managing and mentoring high-performing recruitment teams Deep understanding of roles like RTL, ASIC, FPGA, SoC, Embedded Firmware, AMS Verification, Layout, Packaging , etc. Excellent communication, leadership, and stakeholder management skills Prior exposure to working with both product companies and staffing/RPO setups is a strong advantage Passionate about tech hiring , building teams , and delivering value. Please write to amit.n@careerxperts to get connected!

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains. Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA). Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4. Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 10+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams.

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors 6. Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives 7. Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization 8. Stakeholder influencing and people skills must be excellent. 9. Needs to be able to set aggressive goals and manage risks effectively 10. Must have a thorough understanding of tool development methodology. 11. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. 12. MS or Ph.D. Engineering degree (EE or equivalent) with 3-7 years semiconductor industry experience.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Contribute/Lead towards Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers as well as custom macros in 2nm and other cutting edge process technologies Job Description Contribute/Lead towards Memory Design Validation of all types of custom memory macros and memory compilers Perform functional verification, root cause design discrepancies, and help resolve them Perform signal integrity analysis, identify design weaknesses, and propose possible solutions to address them Perform transistor level simulations to check for any Power Up or Lock up issues and help resolve them Perform EM/IR analysis/simulations and evaluate impact on timing and internal margins Perform transistor level simulations to validate timing and internal margins, identify timing characterization holes, and help resolve them Perform various QA and validation checks to ensure accurate timing and power models Develop scripts to automate verification flow and data analysis Support silicon debugs and correlation to spice models Coordinate with memory design leads, modelling leads, and managers to define and execute on the memory validation plan Skill Sets Strong expertise in development of memory macros of all types and architectures Strong understanding of transistor level circuit behavior and analysis Good understanding of the layout and their related challenges in sub nanometer process technologies Good understanding of signal integrity, EM/IR, and reliability analysis Good understanding of memory behavioral and physical models Good understanding of DFT Schemes and chip level integration Proficient in running transistor level simulators, writing automation scripts, and are tools savvy Complete hands on experience in using Cadence schematic/layout editor tools Complete hands on experience with transistor level simulators, Monte Carlo variation analysis, waveform viewer tools such as; HSPICE, HSIM, XA, FineSim, XARA, nWave, waveform viewer, etc.. Experience in Skill/Perl/Python Scripting is a strong plus Good communication, interpersonal, and leadership skills Good debugging skills, problem solving and logical reasoning skills Motivated, self-driven and good at multi-tasking .