1109 Dft Jobs - Page 22

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Depending on the expertise, the below set of responsibilities can be interpreted for fastspice(Primesim/Finesim) or Verilog (Xcelium/VCS) based verification. Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Good to Have Skills/Experience Common Circuit simulation experience Analysis of Circuits , Timing concepts DFT knowledge schematic analysis Digital Verification High level understanding of UVM DFT Features – Both custom DFT and standard like scan chains Exposure to IEEE1500/JTAG FastSpice Verification Critical timing, data path timing analysis Simulation based reliability analysis (BTI, HC) About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: You will be working with our DFT team from Hyderabad/Work from Home as required to develop DFT tests. These tests are intended to catch manufacturing defects in targeted IPs inside FPGA/SoC. In this role you will have an opportunity to understand in depth FPGA/SoC silicon architectures, ATPG, MBIST Verification at full chip level, DFT/Testability hooks in Silicon, methods and principles to develop ATPG/Functional test vectors, simulate, debug and generate patterns for production tests. You will work closely with Architects, Design engineers, Verification engineers and Software engineers across the globe to ensure FPGA division deploys new products with the highest quality and shortest time to market. Skills will be developed to work on multiple projects supporting key functions within the organization. Good communication and presentation skills are required. Requirements/Qualifications: Understanding basics of DFT structures (OCC, SSN, SIB, WBRs, compression engine), ATPG(Intest/Extest) , MBIST, Boundary Scan (IEEE 1149.1) Tap Controller, Generating, verifying and debugging test patterns at block and chip-level retargeting to test the designs and firmware for new FPGA families. Improving, extending and porting existing manufacturing test designs to all FPGA family members. Test specification, plan, and documentation Hands on experience with industry standard ATPG tools, MBIST, pattern simulation and debugging skills at block and chip-level. Hands-on experience with Verilog behavioral RTL and Gate level netlist. Comfortable with Unix, Perl and/or Shell scripting and familiar with Revision Control (CVS, SVN, …) Strong analytical and problem-solving skills Excellent communication, documentation and presentation skills. Must have strong self-learning ability and enjoy working in teams spread across globe. Good programming skill/Firmware development skills with C, C++/assembly will be a big plus. Exposure to ASIC/FPGA design flow and methodology is a plus (HDL, synthesis, static timing analysis, constraining, Place & Route) BS or MS in EE with 5 to 6 years of experience of working in DFT Travel Time: 0% - 25% To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Designkey digital blocks such as accelerators/ datapath IP in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffs Develop strong understanding of heterogenous processor cores & subsystems (A55/ M55/ M4/ U55/ RISC-V/ DSP core, and associated infrastructure such as caches, interconnect fabric, GIC, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, SPU) and their integration requirements Package Digital IP for seamless integration into design flow at different stages - RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc Consolidate & curate digital IP for SPI/ I2C/ UART/ JTAG and other slow serial interfaces & peripherals Evaluate 3 rd party IPs on Power/ Performance/ Area (PPA) and other key qualitative aspects such as design quality, Design For Testability, robustness of Design Verification (DV) practice, ease of integration and make recommendations Build expertise on complex interfaces, peripherals & protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2D Develop and maintain catalog of digital IPs to enable ease of information sharing to customers across different BUs Develop User Guides for RTL Integration, Synthesis, DFT, PnR, Programming Sequence, characterization etc Establish evaluation flows for home-grown & 3 rd party IPs for consistent benchmarking of evaluation Position Requirements : Minimum B.E. / B.Tech degree in Electrical/Electronics/Computer science 4 - 8 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions Experience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality Knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis Good interpersonal, teamwork and communication skills to logically & effectively drive discussions with teams spread geographically Understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus Experience with end-to-end ASIC/ SoC product development & productization is very desirable

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description You will be working with our DFT team from Hyderabad/Work from Home as required to develop DFT tests. These tests are intended to catch manufacturing defects in targeted IPs inside FPGA/SoC. In this role you will have an opportunity to understand in depth FPGA/SoC silicon architectures, ATPG, MBIST Verification at full chip level, DFT/Testability hooks in Silicon, methods and principles to develop ATPG/Functional test vectors, simulate, debug and generate patterns for production tests. You will work closely with Architects, Design engineers, Verification engineers and Software engineers across the globe to ensure FPGA division deploys new products with the highest quality and shortest time to market. Skills will be developed to work on multiple projects supporting key functions within the organization. Good communication and presentation skills are required. Requirements/Qualifications Understanding basics of DFT structures (OCC, SSN, SIB, WBRs, compression engine), ATPG(Intest/Extest) , MBIST, Boundary Scan (IEEE 1149.1) Tap Controller, Generating, verifying and debugging test patterns at block and chip-level retargeting to test the designs and firmware for new FPGA families. Improving, extending and porting existing manufacturing test designs to all FPGA family members. Test specification, plan, and documentation Hands on experience with industry standard ATPG tools, MBIST, pattern simulation and debugging skills at block and chip-level. Hands-on experience with Verilog behavioral RTL and Gate level netlist. Comfortable with Unix, Perl and/or Shell scripting and familiar with Revision Control (CVS, SVN, …) Strong analytical and problem-solving skills Excellent communication, documentation and presentation skills. Must have strong self-learning ability and enjoy working in teams spread across globe. Good programming skill/Firmware development skills with C, C++/assembly will be a big plus. Exposure to ASIC/FPGA design flow and methodology is a plus (HDL, synthesis, static timing analysis, constraining, Place & Route) BS or MS in EE with 5 to 6 years of experience of working in DFT Travel Time 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Design key digital blocks such as data path IPs(DSP functions, accelrators) in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffs Develop strong understanding of ARM processor cores & subsystems (M series associated infrastructure such as caches, interconnect fabric, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, SPU) and their integration requirements Experience of AFE based projects is an add on. Package Digital IP for seamless integration into design flow at different stages - RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc. Consolidate & curate digital IP for SPI/ I2C/ UART/ JTAG and other slow serial interfaces & peripherals Develop User Guides for RTL Integration, Synthesis, DFT, PnR, Programming Sequence, characterization etc Minimum Qualifications Minimum B.E. / B.Tech degree in Electrical/Electronics/Computer science 4 - 8 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions Experience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality Knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis Good interpersonal, teamwork and communication skills to logically & effectively drive discussions with teams spread geographically Understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus Experience with end-to-end ASIC/ SoC product development & productization is very desirable Experience in IP integration (memories, IO s, embedded processors, hard macros, Analog IP) Knowledge of Microelectronics concepts Scripting skills in Python, Tcl, C etc Ability to collaborate and work directly with the tool vendors to resolve tools bugs, as well as implement the required improvements Great communication and teamwork skills

Lead and manage the DFT team responsible for delivering comprehensive DFT solutions for complex SoCs. Take end-to-end ownership of the DFT lifecycle - from architecture definition to silicon bring-up and production ramp. Collaborate cross-functionally with architecture, design, and physical design teams to ensure optimal testability integration. Define and track DFT milestones, quality metrics, and progress, ensuring alignment with program schedules and quality standards. Represent DFT in program and customer meetings, communicating status, risks, and mitigation plans. Architect and guide the implementation of DFT features, including Scan chain insertion and optimization, Test compression techniques, LBIST/MBIST (including repair logic), Boundary scan structures Lead efforts in performing DFT rule checks (DFT DRC) at RTL and netlist levels to ensure compliance with internal and industry standards. Use industry-standard EDA tools (e.g., Cadence, Siemens/Tessent) for DFT Design, DRC, Pattern Generation and work with EDA/Internal CAD team for tool/flow improvements Drive DFT pattern generation and validation, including gate-level simulations with and without SDF. Partner with the verification team to define and execute DFT verification plans. Collaborate with physical design and STA teams to implement DFT constraints and strategies for synthesis and timing closure. Analyze silicon test data, debug test failures, and work with the test engineering team to resolve bring-up and production issues. Provide technical leadership, mentorship, and career development for DFT engineers on the team. Qualifications and Experience: Proven experience in leading DFT teams through end-to-end SoC execution, from architecture to silicon bring-up. Demonstrated expertise in developing DFT architecture from scratch for complex SoC designs. Strong team management and leadership experience with a track record of mentoring and growing engineering talent. Bachelors or Master s degree in Electrical/Electronics Engineering or a closely related field. 12+ years of hands-on experience in DFT methodologies and industry-standard test techniques. Deep knowledge and hands-on experience with: Logic BIST (LBIST) Automatic Test Pattern Generation (ATPG) DFT Rule Checks (DFT DRC) Scan chain compression and stitching Low-power DFT techniques and constraints Memory BIST (MBIST) including repair mechanisms Boundary Scan (IEEE 1149.1) Analog DFT strategies JTAG architecture and TAP integration DFT-specific STA constraints Proficient in using industry-standard DFT EDA tools, including cadence, Siemens. Strong scripting and automation skills using Perl, Tcl, and/or Python. Solid understanding of digital design fundamentals, including RTL design, Lint/CDC, low power checks, and the full ASIC design flow. Excellent problem-solving skills, with the ability to troubleshoot and resolve complex DFT issues efficiently. Strong communication and interpersonal skills, capable of working effectively in cross-functional and team-oriented environments.

Provide technical and managerial Leadership to a PD team for a SoC Chip development owning partitions and full-chip from synthesis to place and route through all sign-off including timing signoff, physical verification, EMIR signoff, and formal verification. Influence tools, flows, and overall design methodology in design construction, signoff, and optimization. Work closely with architecture/RTL/DFT/DV/Package development teams. Be a technology expert in the area of Physical Design with in the team and business Unit. Minimum Qualifications 10 to 15 years of experience in Physical Design. Proven experience in implementing designs through synthesis, Floorplanning, place and route, extraction, timing, and physical verification. Technically lead a team of PD engineers on the Physical Design activities of complex SoCs. Strong understanding of constraints generation, timing optimization, and timing closure and STA. Strong technical problem solving and debugging ability Experience in EDA tools related to Place and route, Synthesis, Physical Verification , STA etc. Proficient understanding of CTS and different clock building techniques Experience with multi-clock, multi-power-domain design, UPF etc Experience in IP integration (memories, IO s, embedded processors, hard macros, Analog IP) Knowledge of Microelectronics concepts Scripting skills in Python, Tcl, C etc Ability to collaborate and work directly with the tool vendors to resolve tools bugs, as well as implement the required improvements Great communication and teamwork skills

We're looking for a skilled and highly motivated Digital Design Engineer to join our team. In this role, you'll be instrumental in translating complex design specifications into optimal micro-architectures for digital blocks, driving the development of high-performance, power-efficient, and area-optimized silicon. Key Responsibilities: Translate design specifications into optimal micro-architectures for digital blocks, ensuring efficiency and performance. Perform RTL coding using Verilog and SystemVerilog, bringing designs to life. Achieve stringent power, performance, and area (PPA) goals through meticulous micro-architecture optimization. Conduct block-level design verification, ensuring the robustness and correctness of your designs. Collaborate closely with the Design Verification (DV) team to develop comprehensive test plans. Drive front-end implementation activities, including Lint/CDC checks, synthesis, and timing constraint development. Work closely with Design-for-Test (DFT) and Physical Design (PD) teams for successful sign-off. Support Silicon validation, ensuring the fabricated chip meets all design specifications. Position Requirements: BE/BS/MTech/ME/PhD degree in Electrical/Electronics/Computer Science from a reputed institute. 3-10 years of relevant experience in digital design. Hands-on experience in digital logic design, RTL coding, simulation, and debug. Proven experience in writing and debugging timing constraints at both block and full-chip levels. Experience in Synthesis and Logical Equivalence Checking (LEC). Excellent verbal and written communication skills to effectively collaborate with geographically dispersed teams. Experience in digital signal processing and MATLAB modeling is highly desirable. Experience in Processor Subsystem design or System-on-Chip (SoC) development is a plus.

In your new role you will: Responsible for SoC DFT Architecture definition / implementation / verification / silicon debug of SoC/Full Chip. Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. Responsible for ATPG, DRC analysis, Test coverage debug , Memory BIST implementation and verification. Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck-at / TDF / Bridging / Cell-aware / iddq fault models. Good debug skills in ZERO delay and SDF based scan/MBIST/JTAG simulations. Hands on experience in analysis and debug of above-mentioned test domains. Hands of experience in post silicon debug of scan/MBIST patterns/yield fall out You are best equipped for this task if you have: ASIC flow understanding. Experienced in LEC, CLP, power analysis flow is preferred The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the DFT spec, implementation, verification, and Post silicon debug. In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies . The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Scripting skills such as PERL/TCL/Python are preferred

Role : Physical Design Experience : 2 - 20 yrs. Strong background of ASIC Physical Design : Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.. Hands-on experience on technology nodes like 7nm, 14nm, 10nm.. Good knowledge of EDA tools from Synopsys , Cadence and Mentor. Hands-on experience in floor planning, placement optimizations, CTS and routing.. Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS). Skills : Static timing analysis, Application Specific Integrated Circuit (ASIC), Floorplan Manager, Extraction, Synopsys and Physical Design. We are looking for a highly skilled Physical Design Engineer with a strong background in ASIC physical design. The ideal candidate should have hands-on experience in advanced technology nodes (7nm, 10nm, 14nm), and deep expertise in P&R, STA, IR drop analysis, and EDA tools such as Synopsys, Cadence, and Mentor. You will be responsible for all aspects of physical design implementation from RTL to GDSII. Key Responsibilities Execute complete RTL-to-GDSII physical design flow for complex ASICs. Perform floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification. Conduct timing closure using Static Timing Analysis (STA) with tools like PrimeTime (PT/PTSI) or Tempus. Perform IR drop and EM analysis, including extraction and signal integrity verification. Optimize physical designs for power, performance, and area (PPA). Run physical verification checks such as LVS, DRC, and Antenna. Collaborate with logic designers, verification, DFT, and packaging teams to drive design convergence. Debug and resolve physical design issues during implementation and tape-out phases. Utilize scripting (TCL, Perl, Python, etc.) to automate flows and improve efficiency. Key Skills Required Solid background in ASIC physical design, including floorplanning, P&R, extraction, STA, IR/EM analysis, and signal integrity. Hands-on experience with advanced process nodes like 7nm, 10nm, and 14nm. Proficiency In EDA Tools, Such As Synopsys : ICC, DC, PrimeTime (PT/PTSI) Cadence : Innovus, Tempus Mentor : Calibre Experience with floorplan managers, placement optimization, CTS, and final routing. Familiarity with parasitic extraction and delay modeling. Proficient in scripting using TCL, Perl, Python, or Shell for tool automation and flow management. Bachelor's or Master's degree in Electronics Engineering, VLSI, or related field. Knowledge of DFT, DFM, and low-power design techniques. Experience working on full-chip or block-level implementation. Experience with multi-voltage and multi-corner designs. Exposure to 3D-IC, chiplet-based architecture, or advanced packaging flows. Knowledge of RTL synthesis and constraints development. (ref:hirist.tech)

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are seeking a diligent Verification leader to join our team at Renesas. The Verification engineer will be responsible for performing various verification tasks including Test Plan creation, Testcase creation, Coverage closure, Requirements traceability and Gate Level Simulation. They will also review system requirements and track quality assurance metrics. Ultimately, the role of the Verification Engineer is to ensure that our products, applications, and systems work correctly, safely & securely. Responsibilities Drive Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers and microprocessors. Work closely with system architects to understand high level specifications to be able to verify them. Work with various EDA vendors to deploy next generation tools Build strong collaboration with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation, and Validation to achieve project milestones Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies Responsible for developing detailed Technical SoC verification execution plans, progress reports and tracking milestones, managing technical risks, and providing mitigations to meet schedule quality and costs commitments. Communicate across technical teas as well as provide executive level presentations Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs. Drive best in class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI. Qualifications Degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science At least 10 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits. Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC. Experience in Microcontroller and Microprocessor architecture & Interconnect Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR5/5x) and memory controllers. Advanced knowledge of Verilog, System Verilog, C/C++, Shell. Good knowledge in scripting like Perl, TCL or Python is a plus High proficiency in Metric Driven Verification concepts, functional and code coverage. Expertise in directed and constrained random methodologies. Good knowledge of formal verification methodologies and assertions. Experience with debugging of designs pre- and post-silicon, in simulation and on the bench. Excellent written and verbal communication skill. Must have worked on complex, multi-core SoC’s with extensive interconnects and a large range of peripherals. Fair domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, UCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/Flex NOC interconnect; Flash memory subsystems. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Lead development efforts for AMS design collaterals generation fortop level integration, ensuring optimized performance Job Description In your new role you will: Lead development efforts for AMS design collaterals generation for top level integration, ensuring optimized performance. Enforce consistency of all required views for AMS macro integration. Ensure quality of digital design deliverables to RTL2GDS counter parts by running preliminary RTL synthesis and timing checks. Identify and apply methodologies to allow optimal timing closure of complex AMS IP (ADCs, clocking) in the context of digital-on-top integration. Collaborate with cross-functional teams, including digital design,AMS design, layout, and test engineers, to ensure successful productintegration. Interface with design system community, design flow and methodologyteams across multiple sites (Europe, US and Asia). Validate AMS views generation flow to guarantee smooth execution incase of design system and/or design package updates. Your Profile You are best equipped for this task if you have: Master s or Ph.D. in Electrical Engineering or a related field. 15+ years of experience in complex AMS & SoC integration within thesemiconductor industry Proven track record of successful product implementation in advancedCMOS and BCD technologies Deep technical knowledge of mixed-signal IC design and integrationflows Very good understanding of RTL2GDS flows and experience in runningsynthesis, timing closure, DFT insertion Ability to work in a multinational environment and connect designteams with RTL2GDS and SoC integration teams across the organization Ability to support project planning and commitment to ensure timelyexecution. Ability to report progress and issues related to SoC integration tosenior executives

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 1-3 yrs years of experience in Physical Design/Implementation

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Additional o BE/BTech degree in CS/EE with 3+ years’ experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred : o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Principal Duties and Responsibilities: 5+ Years of Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. o BE/BTech degree in CS/EE with 3+ years’ experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred : o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. DFT ATPG Engineer D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs . We re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! Your Responsibilities Will Include: Partitioning for ATPG and hierarchical approaches. ATPG compression and serialization. RTL-Scan insertion and design rule fixing. STA constraints, Primetime execution, and timing exception flow. Interfacing with ASIC design teams to ensure DFT design rules and coverages are met. Generating high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models using on-chip test compression techniques. Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis. Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Being responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE. Having experience with state-of-the-art industry-standard DFT tools. Being hands-on from the "nitty gritty" details to high-level planning. Minimum Qualifications: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. The Role: DFT Engineer - MBIST D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs. We re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! What you will do: Your responsibilities will include: Defining Memory Built-In-Self-Test (MBIST) architecture and running MBIST logic insertion tools. Bringing up and writing constraints for register-transfer-level (RTL) test DRC tools. Enabling DFT RTL verification and designing tests to validate all DFT logic. Identifying and implementing any required RTL fixes. Running scan chain insertion flows and tools. Generating scan coverage figures and debugging any gaps. Delivering schedules and staging plans for DFT intercepts into overall product timelines. What you will bring: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation. Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NAMinimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities:Bachelors degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience.Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of DesignsCore DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debugUnderstanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax)Experience coding in Verilog RTL, and scripting language like TCL, and/or PerlProficient in Unix/Linux environmentsStrong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT)- Strong understanding of software development methodologies- Experience in leading and managing software development projects- Knowledge of technologies and tools used in software development- Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT)- This position is based at our Chennai office- A 15 years full time education is required Qualification 15 years full time education

Company Description Clarity Medical is a leading developer and manufacturer of medical equipment used in Cardiology, Neurology, Critical care, and Clinical Applications. The company specializes in developing high-quality medical devices for the healthcare industry and sells its products globally. Clarity's Research & Development team has over 100 years of cumulative experience in the medical field and follows the industry's best practices to deliver the products that are brought to the market. The company's professional, passionate & confident workforce is dedicated to quality and best-in-class healthcare solutions. Role Description This is a full-time on-site role for a Printed Circuit Board Design Engineer located in Sahibzada Ajit Singh Nagar. The Printed Circuit Board Design Engineer will be responsible for designing, testing, and troubleshooting analog circuits, electrical engineering, and board layouts. The Printed Circuit Board Design Engineer will also be responsible for radio frequency (RF) circuit design and implementation. Job title- Design Engineer No of vacancy- 2 Experience- 3-5Yrs Qualification-Diploma/B. tech electronics Job Location- Mohali (PB) Preference -Local Candidate Strong fundamentals in electronics design (digital & analog) and ability to read schematics. Excellent understanding of Altium Designer Software. Excellent understanding of PCB materials, fabrication processes and PCB layout techniques. Building and maintaining component library for various company products. Initial hardware bring-up and test of PCBs to check initial level of functioning. Generating and maintaining proper record of BOM, Gerber files, fabrications and assembly documents. Co-ordinating with manufacturing house over DFM/DFA and various other aspects for building a scalable and reliable product. Experience in electronic circuit debugging/diagnosing with microcontroller-based embedded systems. Develop and generate drawings and documentation to facilitate PCB fabrication and assembly. Perform drawings and documentation updates per the instructions of engineering changes requests. Collaboration with mechanical team, software team regarding the design constraints with respect to PCB. Should have knowledge about EMI, EMC, DFT and DFM procedure. Knowledge of IPC, ISO and IEC standards. Knowledge of instruments like oscilloscopes, Multimeters and LCR meters.

We Are Hiring: Principal Engineers Chip Design (Back End / Front End / Analog IP/IC) Preferred Skills and Experience: Minimum 1+ years of experience in Project Management (Waterfall and Agile Hybrid methodology) Exposure to continuous improvement and cross-functional collaboration Educational Qualifications: Master's degree in VLSI Design from reputed institutes (IITs/NITs preferred) Bachelor's in Electronics and Communication or a related field 1. Job Title: Principal Engineer – Chip Design Back End Required Skills & Experience: Minimum 8+ years of strong experience in backend flows for MCU or low-power SoC designs Leadership experience with DFT, Physical Design, and Formal Verification teams Exposure to Frontend and Analog design processes Ability to collaborate effectively across functional teams Experience in product support during both pre- and post-production stages (including RMA support) 2. Job Title: Principal Engineer – Chip Design Front End Required Skills & Experience: Minimum 8+ years of experience in system architecture for ARM-based MCU product development Expertise in RTL design, RTL coding, and RTL integration Strong debugging and design capabilities Experience leading verification teams, including static and dynamic verification, test management (UPF, GLN, Test Modes) Familiarity with industry-standard EDA tools (e.g., Synopsys for LINT, CDC, SDC validation, and power analysis) Exposure to Backend and Analog design processes Cross-functional collaboration with PD, DFT, and STA teams for timing and power closure Experience in pre- and post-production product support and RMA handling 3. Job Title: Principal Engineer – Analog IP/IC Design Required Skills & Experience: Minimum 8+ years of experience in custom analog/mixed-signal IC design Proficiency in variation-aware design, verification planning, and analog layout parasitic extraction (LPE) Hands-on experience with analog/mixed-signal EDA tools (e.g., Cadence, Synopsys) Strong debugging and design validation skills Product support experience across development lifecycle, including RMA stage

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Responsibilities: The role’s day to day responsibilities cover: R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills. Job Qualifications: BE/BTech/ME/MTech- Computer Science or others Required Skills Develop reliable, scalable, and high-performance Modus DFT software that is easy to use. Develop software tools in C/C++ to support DFT and ATPG. Research and develop software solutions to allow greater efficiency in architecture, hardware, and software teams. Development environment is C++ on Unix in multi-threaded environment with expertise in C++, data-structure and algorithms. Strong knowledge of Tcl is preferred Experience in language compiler Prior experience with large software development projects is highly recommended. We’re doing work that matters. Help us solve what others can’t.

Job Title : DFT Engineer Location : Bangalore, India Experience : 4 to 8 Years Role Overview We are looking for a passionate and detail-oriented Design-for-Test (DFT) Engineer to join our dynamic ASIC design team. As a DFT Engineer, you will be responsible for architecting and implementing robust test strategies to ensure first-pass silicon success in complex SoC designs. Key Responsibilities Develop and implement DFT architecture and methodologies for SoC/ASIC designs Design and insertion of scan chains , MBIST , LBIST , and boundary scan (JTAG) Work closely with RTL, STA, and Physical Design teams to integrate and validate DFT logic Generate and validate test patterns (ATPG/MBIST) and support silicon bring-up and validation Ensure DFT logic meets coverage goals , timing, and area/power constraints Work with ATE teams on test vectors and debug silicon issues Required Skills & Qualifications 4-8 years of experience in DFT implementation and verification Hands-on experience with tools like Mentor Tessent, Synopsys DFT Compiler, TestMax, TetraMAX Strong knowledge of scan insertion , ATPG , JTAG (IEEE 1149.x) , MBIST , and LBIST Good understanding of ASIC/SoC design flow , RTL to GDSII Proficiency in scripting (TCL, Perl, or Python) for automation Experience working with advanced technology nodes (16nm, 7nm or below) is a plus Excellent analytical, problem-solving, and communication skills Nice to Have Experience in DFT signoff and silicon debug Knowledge of safety-critical designs (ISO 26262) or low-power DFT techniques Familiarity with ATE patterns and post-silicon validation Why Join Us? Work on industry-leading SoCs and IPs Collaborate with some of the best minds in the semiconductor industry Fast-paced, innovation-driven, and engineer-friendly environment Flexible work culture and competitive benefits

In your new role you will: Develop Automated Test Equipment(ATE) test solutions for highly integrated RF SoC Integrated Circuits(ICs) for Wireless connectivity devices on UFlex tester platforms. Interface with cross-functional Design, DFT, PMU, RF, and DVT teams to develop and present test plans. Debug and design the required hardware and test programs that are to be used for device characterization, qualification, and production. Cooperate with Partner and Product Engineering Teams for production characterization and reliability testing. Optimize test times and yields of the Final Test Program for both FE and BE production releases. Your Profile You are best equipped for this task if you have: A bachelors degree (or foreign equivalent) in Electrical Engineering, Electronics Engineering, or a related field. 6 years of experience in ATE test program development for SoC microcontroller-based RF devices. Must have experience in: ATE Platforms (UFlex is must);Version Control Systems (SVN, GIT); Scripting (PERL, PYTHON);Programming (Visual C++, C++, ECLIPSE BASED IDE ); Bench platforms (Labview, ARM Cortex-M Firmware coding, Spectrum Analyzer); and Device Technology: - IEEE 802.11ax WIFI 6/6E, BT/BLE (Bluetooth)