1121 Dft Jobs - Page 24

Technical Requirements Excellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team. In-depth knowledge of floor planning, power planning, PNR and signoff checks Strong experience in static timing analysis (STA), timing closure, and signal integrity. Expertise in power optimization techniques, Upf, including clock gating and multi-voltage domain design Proficiency in physical design tools, such as Synopsys ICC2, Primetime, Calibre, Redhawk-SC Scripting skills in Tcl, Python, or Perl to enhance automation and streamline physical design tasks. Familiarity with DRC, LVS, and other physical verification processes. Responsibilities Own the physical design implementation of SoC subsystems, including floor planning, placement, clock tree synthesis (CTS), routing, and optimization to meet PPA goals. Work closely with RTL, DFT and IP teams to ensure seamless subsystem integration and resolve physical design issues that impact overall system performance. Collaborate with the Full Chip physical verification team to resolve DRC, LVS, and antenna rule violations, ensuring compliance with top level Lead clock tree synthesis, manage clock skew, insertion delay, and ensure timing closure across all corners and modes. Address timing violations and signal integrity issues. Implement power-saving techniques, such as power gating, multi-voltage domains, and clock gating, to achieve low-power targets while maintaining performance. Develop and optimize custom scripts in Tcl, Perl, or Python to streamline physical design tasks and improve workflow efficiency. Mentor and guide junior physical design engineers, sharing best practices and providing technical guidance to improve team efficiency and expertise. Experience: 4+ Years Job Location: Bangalore

Job Summary Java development Lead with hands-on coding and solution designing skills for Functions DFT. Candidate should be able to code and lead and formulate the deliveries for DFT Functions Domain. The candidate should develop Applications and enable Development teams with cookie cutter reusable patterns / components for development with end-to-end ownership / life cycle. Candidate should also be able to lead and guide community group contributing for reusable component/library. Key Responsibilities Have a strong sense of responsibility and ownership and contributes heavily to technical evaluations, decisions, software design & development activities. Contributes to building prototypes or proof of concepts and translates them to production grade applications or reusable components. Keeping track of industry developments, conducting R&D to incorporate best in class practices and methodologies and sharing the same with team and stakeholders. Leading the end-to-end delivery with adherence to timelines & agile practices. Participate in code reviews, assist & mentor team on technical aspects. Key Expertise Expertise in programming language – Java Expertise in web application development using one or more frameworks such as Spring boot, Quarkus, node.js, go lang. Proficient in designing and developing applications using microservices, cloud native architecture & REST API. Expertise in API design and is proficient in applying various design patterns. Experience on ES6, HTML5, React, Redux, JavaScript MVC patterns / frameworks and CSS pre-processers and strategies for scalable CSS, Babel and Webpack. Strong expertise in one or more databases – RDBMS & NoSQL. Strong coding, debugging, profiling, testing and documentation skills. Proficient in version control – GitHub / bitbucket and code reviews. Strong in one or more container ecosystem – Kubernetes, EKS, AKS. Experience in one or more messaging, streaming systems – Kafka, RabbitMQ. Strong in one or more cloud computing platforms – AWS, GCP, Azure. Experience in creating high level architecture & design diagrams. Strong knowledge in CI/CD - ADO Excellent knowledge of Scrum methodology and related processes. Excellent communication and leadership skills. Regulatory & Business Conduct Display exemplary conduct and live by the Group’s Values and Code of Conduct. Take personal responsibility for embedding the highest standards of ethics, including regulatory and business conduct, across Standard Chartered Bank. This includes understanding and ensuring compliance with, in letter and spirit, all applicable laws, regulations, guidelines and the Group Code of Conduct. Effectively and collaboratively identify, escalate, mitigate and resolve risk, conduct and compliance matters. Key stakeholders Enterprise Architects Technology Delivery teams Business Product owners Skills And Experience Java Web application development using one or more frameworks such as Spring boot, Quarkus, node.js, go lang Knowledge on ES6, HTML5, Lit, React, Redux, JavaScript MVC patterns / frameworks and CSS pre-processers and strategies for scalable CSS, Babel and Webpack Experience in one or more container ecosystem – Kubernetes, Openshift, EKS, AKS One or more container ecosystem – Kubernetes, Openshift, EKS, AKS Communication Skills High level architecture & design diagrams Qualifications Minimum Qualifications Bachelor’s in computer science, software engineering or related technical field. 8+ years of relevant work experience. Experience in one or more following: designing distributed systems, designing scalable enterprise applications, application security, full stack development (is a plus). Certification Graduate in Computer Science or related courses Certification on Java, Architecture, Cyber Security, Cloud will be an added advantage Languages JAVA, JAVA SCRIPT About Standard Chartered We're an international bank, nimble enough to act, big enough for impact. For more than 170 years, we've worked to make a positive difference for our clients, communities, and each other. We question the status quo, love a challenge and enjoy finding new opportunities to grow and do better than before. If you're looking for a career with purpose and you want to work for a bank making a difference, we want to hear from you. You can count on us to celebrate your unique talents and we can't wait to see the talents you can bring us. Our purpose, to drive commerce and prosperity through our unique diversity, together with our brand promise, to be here for good are achieved by how we each live our valued behaviours. When you work with us, you'll see how we value difference and advocate inclusion. Together We Do the right thing and are assertive, challenge one another, and live with integrity, while putting the client at the heart of what we do Never settle, continuously striving to improve and innovate, keeping things simple and learning from doing well, and not so well Are better together, we can be ourselves, be inclusive, see more good in others, and work collectively to build for the long term What We Offer In line with our Fair Pay Charter, we offer a competitive salary and benefits to support your mental, physical, financial and social wellbeing. Core bank funding for retirement savings, medical and life insurance, with flexible and voluntary benefits available in some locations. Time-off including annual leave, parental/maternity (20 weeks), sabbatical (12 months maximum) and volunteering leave (3 days), along with minimum global standards for annual and public holiday, which is combined to 30 days minimum. Flexible working options based around home and office locations, with flexible working patterns. Proactive wellbeing support through Unmind, a market-leading digital wellbeing platform, development courses for resilience and other human skills, global Employee Assistance Programme, sick leave, mental health first-aiders and all sorts of self-help toolkits A continuous learning culture to support your growth, with opportunities to reskill and upskill and access to physical, virtual and digital learning. Being part of an inclusive and values driven organisation, one that embraces and celebrates our unique diversity, across our teams, business functions and geographies - everyone feels respected and can realise their full potential. Recruitment Assessments Some of our roles use assessments to help us understand how suitable you are for the role you've applied to. If you are invited to take an assessment, this is great news. It means your application has progressed to an important stage of our recruitment process. Visit our careers website www.sc.com/careers

ASIC DFx - MTS Silicon Design Engineer New Dehli, India Engineering 66377 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFx - MTS SILICON DESIGN ENGINEER THE ROLE: AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications. Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS. Work with multi-functional teams and handling schedules Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Minimum 8 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus. Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Good understanding of RTL quality checks such as SGLINT, SGDFT, CDC, RDC etc Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience with accelerator architectures and data center workloads. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Preferred qualifications: 2 years of experience post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the job In this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Job description: Architecture and design of digital blocks for integration CMOS IC’s Specification and design of digital blocks at RTL level and addition of DfT concept onto the design Synthesis, block verification and gate level analysis of implemented digital blocks for on-silicon integration Implementation and verification of ECO’s on existing designs Technically lead digital design tasks in strong cooperation with project technical lead and project manager Creation and patenting of new IP Profile description: Successfully completed university degree in Electronics or comparable Extensive years of experience in digital design with hands-on experience on relevant design/simulation/synthesis tools Knowledge of RTL design with HDL (Verilog/VHDL) for integrated devices. Knowledge of relevant digital design flow tools for synthesis, LEC (logic equivalence check), CDC/RDC (clock/reset domain crossing), linting, synthesis constraining Knowledge of advanced digital verification tools and methodologies (e.g UVM) would be a plus Strong team player, committed to deadlines and development discipline, with a visible “what’s best for the company” mentality Soi Kim Kee suki.kee@ams-osram.com +65 () 62402395

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFx - MTS SILICON DESIGN ENGINEER The Role AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications. Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS. Work with multi-functional teams and handling schedules Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Minimum 8 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus. Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Good understanding of RTL quality checks such as SGLINT, SGDFT, CDC, RDC etc Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Soc Power Architecture - Power Artist/PTPX Hyderabad, India Engineering 66223 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ The Role: We are looking for an experienced engineer to join the SOC Power Modeling team in the AMD Client Computing and Graphics group. This role involves collaboration with multiple engineering teams including SoC architecture definition, IP design, integration/physical design, verification, and platform architecture. Contributions have a direct impact on the power & performance of AMD’s Client products. The Person: The candidate should have SOC design process experience from front end to tapeout. The candidate will work closely with the SOC design teams on RTL and emulation-based power estimation, simulation and design data extraction. The candidate must be organized, self-motivated and able to work effectively on teams large and small across multiple sites. He or she must be able to prioritize assignments and drive them to completion. Good verbal and written communication skills are helpful for technical discussions with team members across the globe. Key Responsibilities: Work with front end RTL, DFT, Synthesis, and Physical design teams in the development of power intent (UPF) design at SoC level. Work with emulation team on power estimates during the pre-silicon design process using Power Artist/PTPX emulation environments and ensure power objectives and goals are met. Work with RTL and physical design teams to generate data on design impact from clock and power gating, device type mix and physical implementation options. Track IP power development through the design cycle ensuring it meets power budgets - leakage/dynamic at every milestone. Work with design verification in validating low power design features at SoC and IP level. Preferred Experience Experience with Synopsys EDA tools, particularly PtPx/Power Artist. Understanding of hardware emulation process, stimulus and EDA flows. Experience with Tcl and Python based scripting. Experience with UPF. Academic Credentials Master or Bachelor of Science degree in Electrical Engineering. 3+ years of experience. #LI-RR1 #LI-Hybrid AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Location Bangalore, Karnataka, India Employment Type Full time Location Type Hybrid Department R&D - HW Silicon Engineering At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. DFT ATPG Engineer D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs . We’re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! Your Responsibilities Will Include: Partitioning for ATPG and hierarchical approaches. ATPG compression and serialization. RTL-Scan insertion and design rule fixing. STA constraints, Primetime execution, and timing exception flow. Interfacing with ASIC design teams to ensure DFT design rules and coverages are met. Generating high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models using on-chip test compression techniques. Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis. Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Being responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE. Having experience with state-of-the-art industry-standard DFT tools. Being hands-on from the "nitty gritty" details to high-level planning. Minimum Qualifications: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Job description ROLES & RESPONSIBILITIES: Responsible to check the quality of INCOMING material (raw material, samples, semi-finished goods), in-process goods, finished goods at every stage of production & before client delivery Implement Quality Process for continual improvement of the process Responsible to support Quality management system, vendor audit, internal audit, internal audit ISO-9001. Accountable and responsible for training operators/ engineers on Quality standards. Work closely with PPC & PE team to generate manufacturing inspection test plans, ensure good quality products are produced and minimize non-conformance of products Liaise with team members to ensure smooth introduction of new products and processes Conduct audits & create reports to determine proper corrective and preventive actions. Analyze root causes and implement corrective actions for processes or parts that have concerns Analyze customer warranty returns and implement corrective and preventive actions. Responsible for suggesting and correcting issues at the installation site Responsible for material inspection / test at vendor or supplier location Responsible to follow the ISO process and adhere to the defined procedures Reporting responsibilities – Daily/ weekly/ monthly quality issues and analysis. Maintain and update quality tracker and provide suggestions for quality improvement Preparation of documentation for any product quality change Calibration and certification of test & measuring instruments, tools. Certification of Products Viz., BIS and other applicable industry standards Responsible to communicate with both Technical & Non-technical people effectively Responsible for test fixtures & jigs. Implementation of FMEA, PFMEA, DFM & DFT, Kaizen, 5S, CSO, 7QC Tools, and CAPA, Knowledge of PPAP, APQP for process capability analysis. For mechanical quality Engineer Responsible for plastic, sheet metal, engineering materials, welding, finishing process. QUALIFICATION & SKILLS: BE (or Diploma) Mechanical 0-2 yrs experience in Quality Control/ Assurance department Must have good knowledge of plastic, sheet metal, engineering materials, welding, finishing process. Experience in manufacturing industry is preferred Experience in LED Lighting OR Auto Industry would be an added advantage Candidate needs to be enthusiastic, self-motivated and passionate about their work Should have good communication skills and be able to speak English, Hindi & Kannada fluently Job Type: Full-time Pay: ₹250,000.00 - ₹350,000.00 per year Benefits: Health insurance Provident Fund Schedule: Morning shift Night shift Rotational shift Supplemental Pay: Yearly bonus Work Location: In person

Job Description. Arm’s CE-Systems DFT team implements DFT for test chips and hard macros to prove out Arm soft IP power, performance, area, and functionality within the context of an SoC using the latest DFT and process technologies. The DFT team works closely with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE.. Responsibilities. Architect, implement, and validate innovative DFT techniques on test chips as well as hard macros. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.. Required Skills And Experience. This role is for a Senior Principal DFT Engineer with 15+ years of experience in Design for Test. Experience coding Verilog RTL, TCL and/or Perl. Proficient in Unix/Linux environments. Core DFT skills considered for this position should include some of the following Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics. Bachelors or Master’s degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field. “Nice To Have” Skills and Experience. Familiarity with IEEE 1149, 1500, 1687, 1838. Synthesis & Static Timing Analysis. Familiarity with SoC style architectures including multi-clock domain and low power design practices.. Validated understanding of Siemens DFT tools. Familiarity with Arm IP like the following Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug. Experience with 2.5D and 3D test. Ability to work both collaboratively on a team and independently. Hard-working and excellent time management skills with an ability to multi-task. An upbeat demeanor to working on exciting projects on the cutting edge of technology. Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools. In Return. We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding!. Partner and customer focus. Teamwork and communication. Creativity and innovation. Team and personal development. Impact and influence. Deliver on your promises. Accommodations at Arm. At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.. Hybrid Working at Arm. Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.. Equal Opportunities at Arm. Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.. Show more Show less

To work as a Frontend engineer and taking care of Synthesis, LEC, CLP and Power Analysis for complex SoC projects.. Job Description. In your new role you will:. Implement high-performance, low-power, and area-efficient digital designs.. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis.. Optimize designs for power, performance, and area, and meet PPA goals.. Power analysis using PT-PX or equivalent flow.. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs.. Define and evaluate constraints and signoff Test/DFT mode timing requirements.. Your Profile. You are best equipped for this task if you have:. Strong fundamentals and experience in Synthesis and STA domains.. Write and implement block level and top-level timing constraints for Synthesis. Optimize designs for power, performance, and area, and meet design goals.. Knowledge on Power analysis and PT-PX flow.. Understanding of DFT flows, including scan insertion.. Write and evaluate Test/DFT mode timing constraints.. Thorough with Logic Equivalence Check debug capability.. Well known about UPF concepts and Low Power Checks at block and full chip level.. Defining and verification of STA constraint for Functional and Test/SCAN Modes.. Defining PVT’s corners required for covering all desired scenarios for a design. Knowledge on OCV/AOCV/POCV derates.. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues.. VASTA timing closure based on chip IR drop.. Knowledge on signal SI analysis and PT-PX flow.. Contact:. swati.gupta@infineon.com. #WeAreIn for driving decarbonization and digitalization.. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.. Are you in?. We are on a journey to create the best Infineon for everyone.. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills.. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.. Click here for more information about Diversity & Inclusion at Infineon.. Show more Show less

Principal DFT Engineer (MBIST) in Pune, MH, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: The ideal candidate will work with multi-functional global teams to design, implement and verify Boundary Scan, ATPG (Stuck-AT/AT-Speed) SCAN, MBIST, IO BIST and JTAG/IJTAG DFT features on our next generation highly complex server class processor products. Will work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug. What youll achieve: DFT features like EDT, SSN, shared bus based MBIST insertion, ijtag, simulation and debug on RTL and gates netlist Boundary Scan insertion, simulation and verification Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis Scan ATPG pattern generation, simulation and debug on RTL and gates netlist Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor, Cadence, Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data Bachelors degree & 8 years of related experience or Masters degree & 6 years of related experience Expert with methods and techniques to design, implement and verify regular and shared bus based Memory BIST on repairable and non-repairable memories using Electrical fuses. Expert knowledge and practical work experience partnering with designers to implement highly customized and tools-driven MBIST solutions. Solid understanding of MBIST algorithms needed for 5nm and lower technology nodes and ability to code new algorithms, operation sets supporting tool driven solutions. Experience in implementing EDT, SSN, boundary scan, jtag/ijtag features. Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level Hands on experience in the usage of industry standard tools, like Siemens Tessent Shell flow, or Synopsys SMS/SHS flow Expert understanding tradeoffs to optimize coverage and test time reduction with the ability to foresee physical implementation and timing challenges during early development. Experience in working with physical design teams to support STA constraints, reviewing timing reports. Expert in using silicon debug/diagnosis tools to root cause silicon bringup and production test issue. Experience in setting up and running Scan DRC flows in RTL. Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl. Experience in revision control systems like GIT, perforce etc.. Needs in depth experience in stuck at, transition delay, path delay, etc. coverage loss analysis and identifying solutions to improve test coverage Experience in leading the effort to derive cell aware fault models and develop necessary flows to generate ATPG and to support silicon debug. Good knowledge of functional safety, clock domain crossing analysis, logic synthesis and scan insertion At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Principal DFT Engineer (MBIST) in Bangalore, KA, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: The ideal candidate will work with multi-functional global teams to design, implement and verify Boundary Scan, ATPG (Stuck-AT/AT-Speed) SCAN, MBIST, IO BIST and JTAG/IJTAG DFT features on our next generation highly complex server class processor products. Will work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug. What youll achieve: DFT features like EDT, SSN, shared bus based MBIST insertion, ijtag, simulation and debug on RTL and gates netlist Boundary Scan insertion, simulation and verification Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis Scan ATPG pattern generation, simulation and debug on RTL and gates netlist Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor, Cadence, Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data Bachelors degree & 8 years of related experience or Masters degree & 6 years of related experience Expert with methods and techniques to design, implement and verify regular and shared bus based Memory BIST on repairable and non-repairable memories using Electrical fuses. Expert knowledge and practical work experience partnering with designers to implement highly customized and tools-driven MBIST solutions. Solid understanding of MBIST algorithms needed for 5nm and lower technology nodes and ability to code new algorithms, operation sets supporting tool driven solutions. Experience in implementing EDT, SSN, boundary scan, jtag/ijtag features. Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level Hands on experience in the usage of industry standard tools, like Siemens Tessent Shell flow, or Synopsys SMS/SHS flow Expert understanding tradeoffs to optimize coverage and test time reduction with the ability to foresee physical implementation and timing challenges during early development. Experience in working with physical design teams to support STA constraints, reviewing timing reports. Expert in using silicon debug/diagnosis tools to root cause silicon bringup and production test issue. Experience in setting up and running Scan DRC flows in RTL. Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl. Experience in revision control systems like GIT, perforce etc.. Needs in depth experience in stuck at, transition delay, path delay, etc. coverage loss analysis and identifying solutions to improve test coverage Experience in leading the effort to derive cell aware fault models and develop necessary flows to generate ATPG and to support silicon debug. Good knowledge of functional safety, clock domain crossing analysis, logic synthesis and scan insertion At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

As a member of the AECG ASIC Group, you will help bring to life cutting-edge designs. As a member of the Back-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA we'll versed with timing signoff methodology and corner definitions Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring full chip level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure P REFERRED EXPERIENCE : 12+ years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Successfully led static timing analysis (STA) and closure for 2 3 SoC projects from RTL to tape-out. Proficient in analyzing SoC architecture to derive appropriate timing constraints and define STA methodology. Skilled in translating architectural and design specifications into accurate timing constraints (SDC), including clock definitions, generated clocks, exceptions (false paths, multi-cycle paths), and hierarchical timing. Coordinated cross-functional efforts across design, synthesis, P&R, and verification teams to ensure timing signoff. Owned timing budgets, constraint development, and timing ECOs, achieving first-pass silicon success. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc Excellent communication and interpersonal skills and always enthusiastic to collaborate with diverse teams. Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Experience in working full-chip STA closure, defining mode requirements and corners for timing closure. Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: we'll versed with timing signoff methodology and corner definitions Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring block/SS level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure PREFERRED EXPERIENCE: 3+ years of experience for timing closure of block/SS Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory. Good understanding of SDC construct ( clock generation , false path , multi cycle paths..) ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

PMTS SILICON DESIGN ENGINEER THE ROLE: We are looking for a senior DFT Engineer to join our team to develop world-class DFT architecture for EPYC Server products. In this role you will be engaged with the SoC Architects, Micro Architects, PD Engineers, Product Engineers, etc, to define/implement the DFT Architecture and technically guide and lead the DFT execution team. You will also be responsible for driving innovation to continuously improve the execution and also drive TTR (Test Time Reduction) THE PERSON: You will possess very strong DFT knowledge and bring broad experience in with a strong, self-motivated work ethic and leadership qualities. KEY RESPONSIBILITIES: Work closely with the SoC Architecture and uArch teams to define the DFT architecture. Be the Tech Lead driving DFT RTL implementation, DFT functional and Scan capture timing closure, Scan/ATPG implementation to hit the product coverage goals, interactions with the Product Engineering team to ensure on-time and FirstTimeRight pattern delivery and silicon bring-up Drive the required pre-silicon reviews for RTL, DFT DV and ATPG to ensure clean tape-out and silicon bring-up Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to comprehend and validate all the usage models Work with the post-silicon team on debug support and to help root-cause failures Be upto date with the industry trends and bring-in the latest to the AMD products Work with DFT Tool Vendors and drive improvements based on our requirements REQUIREMENTS: 15+ years of in-depth DFT experience having driven multiple Tapeouts and silicon bring-ups across different process nodes. Good understanding and exposure to SoC design and architecture Very good understanding of verif and timing concepts having handled DFT timing closure Exposure to all DFT concepts such as JTAG, SCAN, MBIST, BScan, etc Comfortable with VCS/Verdi and Mentor TK. Logical in thinking and ability to gel well within a team Good stakeholder management Ability to quickly adapt to changes and handle pressure Good communication and leadership skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer engineering/Electrical Engineering #LI-AA1 Benefits offered are described: AMD benefits at a glance .

As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world-class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Key Responsibilities & Expertise Minimum of 3+ years experience in the area of DFT (Design-for-Test) , including ATPG (Automatic Test Pattern Generation), Scan Insertion, MBIST (Memory Built-In Self-Test), JTAG . In-depth knowledge of DFT concepts . In-depth knowledge and hands-on experience in DFT (scan/MBIST) insertion, ATPG pattern generation/verification, MBIST verification, and post-silicon bring-up/yield analysis . Expertise in test mode timing constraints definition , knowledge in providing timing fixes/corrective actions for timing violations. Ability to analyze and devise new tests for new technologies/custom RAM design/RMA (Return Material Authorization) etc. Expertise in scripting languages such as Perl, Shell, etc. Experience in simulating test vectors . Knowledge of equivalence check and RTL lint tool (like Spyglass). Ability to work in an international team, dynamic environment. Ability to learn and adapt to new tools and methodologies. Ability to do multi-tasking & work on several high priority designs in parallel. Excellent problem-solving skills. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Title: PCB Designer Location: Noida Salary Range: ₹3 LPA – ₹7 LPA Job Description: We are seeking a skilled and detail-oriented PCB Designer to join our team, specializing in IoT hardware development . The ideal candidate will have hands-on experience with designing compact, power-efficient circuit boards for connected devices. Key Responsibilities: Design PCBs tailored for IoT devices, with a focus on compact and power-efficient layouts. Create schematics and multi-layer PCB layouts for wireless-enabled circuits (e.g., Wi-Fi, BLE, LoRa, Zigbee). Integrate microcontrollers, sensors, actuators, and communication modules into PCB designs. Ensure signal integrity and optimize power efficiency in low-power IoT designs. Perform high-speed routing and impedance matching for RF and wireless circuits. Generate Gerber files, BOMs, and complete production-ready documentation for manufacturing. Apply DFM (Design for Manufacturing) and DFT (Design for Test) principles to compact IoT product designs. Work with flexible PCBs, small-form-factor boards, and battery-powered hardware configurations. Conduct prototyping, testing, and debugging of IoT circuit boards. Ensure compliance with relevant industry standards, including FCC, CE, and RoHS for wireless and IoT devices. Stay informed about the latest trends in IoT hardware, wireless communication modules, and PCB design tools. Job Types: Full-time, Permanent, Fresher, Internship Pay: ₹300,000.00 - ₹700,000.00 per year Schedule: Day shift Work Location: In person

Job Title: PCB Designer Location: Noida Salary Range: ₹3 LPA – ₹7 LPA Job Description: We are seeking a skilled and detail-oriented PCB Designer to join our team, specializing in IoT hardware development . The ideal candidate will have hands-on experience with designing compact, power-efficient circuit boards for connected devices. Key Responsibilities: Design PCBs tailored for IoT devices, with a focus on compact and power-efficient layouts. Create schematics and multi-layer PCB layouts for wireless-enabled circuits (e.g., Wi-Fi, BLE, LoRa, Zigbee). Integrate microcontrollers, sensors, actuators, and communication modules into PCB designs. Ensure signal integrity and optimize power efficiency in low-power IoT designs. Perform high-speed routing and impedance matching for RF and wireless circuits. Generate Gerber files, BOMs, and complete production-ready documentation for manufacturing. Apply DFM (Design for Manufacturing) and DFT (Design for Test) principles to compact IoT product designs. Work with flexible PCBs, small-form-factor boards, and battery-powered hardware configurations. Conduct prototyping, testing, and debugging of IoT circuit boards. Ensure compliance with relevant industry standards, including FCC, CE, and RoHS for wireless and IoT devices. Stay informed about the latest trends in IoT hardware, wireless communication modules, and PCB design tools.

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world-class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Role: SOC level Mixed Signal and High Speed Interfaces verification Engineer Experience: 1 to 6 years in Design Verification Responsibilities: Responsible for RTL and GLS level validation at SOC. Post Silicon validation support. Required Skills and Knowledge: Familiarity with basic concepts of SV, UVM, and C-based test case bring-up. Understanding of GLS simulations and debug is a plus. Good in communication. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

About The Opportunity A pioneering player in the Electronics Manufacturing sector, we design and produce advanced electronic components that are integral to modern technology solutions. Our focus is on innovative board design, delivering high-quality, reliable, and efficient products that meet the diverse needs of our global clientele. Role & Responsibilities Design and develop high-performance printed circuit boards (PCBs) for various electronic applications. Conduct thorough analysis and simulation to ensure design integrity and reliability. Collaborate with cross-functional teams to optimize board layout and component selection. Implement design for test (DFT) strategies to facilitate effective product testing. Ensure designs meet all relevant regulatory and industry standards, including EMC compliance. Engage in troubleshooting and problem-solving throughout the design cycle to mitigate potential issues. Skills & Qualifications Must-Have Proven experience in circuit design and PCB layout. Strong understanding of signal integrity and analysis techniques. Familiarity with simulation tools for electronic design. Ability to work collaboratively in cross-functional teams. Effective problem-solving skills and attention to detail. Preferred Experience with DFT strategies and methodologies. Knowledge of analog design principles. Awareness of industry standards for electronic design. Benefits & Culture Highlights Dynamic work environment fostering innovation and creativity. Opportunities for professional growth and development. Collaborative culture with a focus on teamwork and support. Skills: emc compliance,circuit design,problem solving,analog design principles,problem-solving,pcb layout,simulation tools,attention to detail,signal integrity,dft strategies

Execute the customer projects with high quality, cost and deliverables within agreed timelines with close follow-ups with internal CFTs & customers. Calibration work packages, Vehicle calibration, Documenting in the form of development reports Vehicle functions :- Veh speed acquisition, Vehicle drivability, Low & high idle governing, Start system, Expedition (Summer, winter & Altitude), Gear detection, Top speed limitation, FAS, Smoke limitation. Special functions: - ZFC, FBC, Dew point detection, FMO, P4 modelling. Dataset and project management, ARCs, PRCs, SSDs & CSSDs checks - follow ups with internal CFTs. Label responsibility list. INCA Flow, iCDM, vCDM, E-Handbook and Uniplot usage PSR-C for dataset containerization OHW specific functions (CEV & genset calibration) Preparation of first firing activities. Executing necessary preliminary tests on the labcar Preparing necessary test set up for calibration activities on the Engine/vehicle Executing necessary measurements on the engine & Vehicles based on functional experts requirements Executing calibration activities on the dyno and real driving conditions Participation in customer discussion and updating the status on regularly Creating the calibration development reports Calibration review with calibration functional experts Field data analysis and report creation Frequent update to calibration activity status to internal team and customers Calibration data and status update in ICDM & VCDM Handling of test vehicles as per the predefine procedure Participation in vehicle expedition at extreme ambient conditions Support for calibration efficiency improvements and innovation Calibration automation and tools development Domestic travel to customer site for calibration activities

Should have worked hands-on Full chip DFT implementation, Scan, DRCs, ATPGgeneration & Simulations along with Pattern Porting/re-targeting and Coverage improvement Experience with Scan, Compression, ATPG and simulations withSynopsys EDAtools. Should have participated in successful tape-outs of SoC/ASIC chips at 3nm or below and achieved test targets. Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process Excellent problem solving and debugging skills. Proactive in nature Excellent Customer interaction, Communication and Team work skills

Location Bangalore, Karnataka, India Employment Type Full time Location Type Hybrid Department R&D - HW Silicon Engineering At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. DFT ATPG Engineer D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs . We’re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! Your Responsibilities Will Include: Partitioning for ATPG and hierarchical approaches. ATPG compression and serialization. RTL-Scan insertion and design rule fixing. STA constraints, Primetime execution, and timing exception flow. Interfacing with ASIC design teams to ensure DFT design rules and coverages are met. Generating high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models using on-chip test compression techniques. Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis. Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Being responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE. Having experience with state-of-the-art industry-standard DFT tools. Being hands-on from the "nitty gritty" details to high-level planning. Minimum Qualifications: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Location Bangalore, Karnataka, India Employment Type Full time Location Type Hybrid Department R&D - HW Silicon Engineering At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. The Role: DFT Engineer - MBIST D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs. We’re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! What you will do: Your responsibilities will include: Defining Memory Built-In-Self-Test (MBIST) architecture and running MBIST logic insertion tools. Bringing up and writing constraints for register-transfer-level (RTL) test DRC tools. Enabling DFT RTL verification and designing tests to validate all DFT logic. Identifying and implementing any required RTL fixes. Running scan chain insertion flows and tools. Generating scan coverage figures and debugging any gaps. Delivering schedules and staging plans for DFT intercepts into overall product timelines. What you will bring: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation. Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.