1121 Dft Jobs - Page 28

Role: CAD Engineer (Frontend and Backend) Experience: 10+years Location: Bangalore Notice Period: Max 15days preferred Role Overview We are looking for a CAD Engineer (Frontend and Backend)to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What youll do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What you need to have B.Tech/B.E in Computer Engineering (or allied discipline e.g. Electrical, Electronics) 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Senior Digital Design Engineer - PCIe We are seeking a Senior Digital Design Engineer with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions. Key Responsibilities: Design and implement high-performance digital solutions, including RTL development and synthesis. Collaborate with cross-functional teams on IP integration for processor IPs and peripherals Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes 16nm. Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug. Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verification flows Basic Qualifications / Experience Level: Bachelor s in Electronics/Electrical engineering (Masters preferred). 8+ years of digital design experience, with 4+ years focused on processor, peripherals and full chip implementation. Proven expertise in RTL development, synthesis, and timing closure. Experience with front-end design, gate-level simulations, and design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. Required Expertise: Proven expertise in micro-architecture development and RTL development for block level and full-chip designs at advanced nodes ( Experience with front-end design, gate-level simulations, and supporting design verification through multiple ASIC T/O cycles . Hands-on experience with processor IP (ARM/ARC) Experience of working on PCIe is a must. Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART Hands-on experience with complex DMA engines and FW interaction. Strong proficiency in System Verilog/Verilog and scripting (Python/Perl). Experience with block-level and full-chip design at advanced nodes ( 16nm). Silicon bring-up and post-silicon debug experience. Familiarity with industry standard simulation, debug, quality checking and synthesis tools Synopsys/Cadence tools and UVM-based design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. Preferred Experience: Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation is a plus. Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems Experience of working on PCIe/UAL is a big plus. Understanding of PAD design, DFT, and floor planning. Experience in synthesis, and timing closure is a big plus. Experience with NIC, switch, or storage product development. Familiarity with working in design and verification workflows in a CI/CD environment. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Job Summary: As a Static Timing Analysis (STA) Engineer at Astera Labs, you will play a pivotal role in ensuring our digital ASIC designs meet stringent timing and performance requirements, with a strong emphasis on Design for Test (DFT). You will be responsible for timing analysis, identifying critical paths, and driving timing closure across complex ASICs and chiplets. This is a unique opportunity to contribute to the development of cutting-edge silicon for AI infrastructure. Key Responsibilities: Collaborate with design and architecture teams to define and refine timing constraints for DFT across complex ASICs and chiplets. Perform timing analysis and signoff in all DFT modes using industry-standard tools such as PrimeTime. Analyze and resolve timing violations, with a focus on test modes and scan paths. Integrate and validate timing constraints from third-party IPs and external vendors. Generate detailed timing reports, highlighting violations and providing optimization recommendations. Work closely with RTL, physical design, DFT, and verification teams to resolve timing-related issues. Contribute to the development and enhancement of STA methodologies, flows, and automation. Demonstrate a professional attitude with the ability to prioritize tasks, plan effectively for meetings, and work independently with minimal supervision. Exhibit an entrepreneurial mindset and a can-do attitude, acting quickly and decisively with the customer in mind. Collaborate effectively with cross-functional and globally distributed teams. Basic Qualifications: Bachelor s degree in Electrical or Computer Engineering with 8+ years of ASIC experience, or a Master s degree with 6+ years. Proven experience with block- and full-chip timing constraints, including test modes. Strong understanding of DFT architectures and hands-on experience closing timing specifically for DFT. Experience integrating third-party IPs and managing associated timing constraints. Proficiency in STA tools such as PrimeTime and scripting for automation. Preferred Qualifications: Experience with automated constraint generation and validation tools. Familiarity with high-speed interfaces such as PCIe, CXL, and DDR. Strong communication and collaboration skills in cross-functional, globally distributed teams. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains. Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA). Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4. Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are seeking a highly skilled and experienced Synthesis and Static Timing Analysis (STA) expert to join our semiconductor team. The ideal candidate will have a strong background in digital design and a deep understanding of synthesis and STA processes. This role involves working closely with cross-functional teams to ensure the successful implementation and optimization of digital designs. Key Responsibilities: Good Understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints Generation, UPF, Timing Closure and Signoff. Develop TCL scripts and design constraints to perform synthesis, DFT insertion, and static timing analysis. Interface for DFT strategy and implementation. Responsible for design convergence in timing and logic equivalence. Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, LEC, VCLP. Knowledge of scripting languages such as Perl, Python, or TCL. Qualifications Exp : 5 to 12 years of experience Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are seeking a highly skilled and experienced Synthesis and Static Timing Analysis (STA) expert to join our semiconductor team. The ideal candidate will have a strong background in digital design and a deep understanding of synthesis and STA processes. This role involves working closely with cross-functional teams to ensure the successful implementation and optimization of digital designs. Key Responsibilities: Good Understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints Generation, UPF, Timing Closure and Signoff. Develop TCL scripts and design constraints to perform synthesis, DFT insertion, and static timing analysis. Interface for DFT strategy and implementation. Responsible for design convergence in timing and logic equivalence. Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, LEC, VCLP. Knowledge of scripting languages such as Perl, Python, or TCL. Qualifications Exp : 2 to 5 years of experience Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are seeking a highly skilled and experienced Synthesis and Static Timing Analysis (STA) expert to join our semiconductor team. The ideal candidate will have a strong background in digital design and a deep understanding of synthesis and STA processes. This role involves working closely with cross-functional teams to ensure the successful implementation and optimization of digital designs. Key Responsibilities: Good Understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints Generation, UPF, Timing Closure and Signoff. Develop TCL scripts and design constraints to perform synthesis, DFT insertion, and static timing analysis. Interface for DFT strategy and implementation. Responsible for design convergence in timing and logic equivalence. Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, LEC, VCLP. Knowledge of scripting languages such as Perl, Python, or TCL. Qualifications Exp : 5 to 12 years of experience Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

The position is with one of our IDM client. Job Summary: As a Functional Verification Engineer, you will be responsible for verifying RTL designs using SystemVerilog and UVM . You’ll develop testbenches, build reusable components, and ensure complete functional coverage of IPs or SoC-level designs. Key Responsibilities: Develop and maintain UVM-based testbenches for IP/subsystem/SoC verification Create test plans from microarchitecture/design specifications Write and debug directed and constrained-random tests Implement functional coverage , assertions (SVA), and checkers Run regressions using simulators like VCS, Xcelium, or Questa Interface with RTL, DFT, and Firmware teams to track and resolve bugs. Analyze waveforms (using DVE/SimVision), track bugs, and maintain bug databases (JIRA, Bugzilla) Education: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design Job Types: Full-time, Permanent Pay: ₹520,585.58 - ₹1,589,173.72 per year Schedule: Day shift Work Location: In person

Role: CAD Engineer (Frontend and Backend) Experience: 10+years Location: Bangalore Notice Period: Max 15days preferred Role Overview We are looking for a CAD Engineer (Frontend and Backend) to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What You Need To Have B.Tech/B.E in Computer Engineering (or allied discipline e.g. Electrical, Electronics) 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks Show more Show less

Description Invent the future with us. Recognized byFast Company’s 2023 100 Best Workplaces for Innovators List,Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us. About The Role Ampere is seeking a highly skilled and experienced candidate with proven expertise in PHY hardening, particularly in DDR and SerDes, with a focus on digital implementation and convergence. We are looking for a self-motivated individual with a proven track record in hardening state-of-the-art PHYs and contributing to the development of cutting-edge expertise. What You’ll Achieve As a PHY Hardening Engineer, you will collaborate with architects, RTL designers, packaging and PCB design teams, and post-silicon validation groups. This is an exceptional opportunity to showcase your engineering skills in a dynamic, fast-paced environment that fosters innovation and operates at the forefront of technology. High-Speed Digital Design Develop high-speed digital layouts, including DDR and other high-speed interfaces. Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits. Optimize layouts to minimize signal integrity issues, reduce power consumption, and meet timing, power, and manufacturability requirements. Coordinate with PHY vendors for hardening activities and deliverables. Estimate effort and timelines for PHY hardening tasks and provide feedback on timing/PDV. Chip-Level Physical Design Perform chip-level tasks such as floor planning, partitioning, and power/clock distribution. Handle chip assembly and ensure seamless integration of multiple IP blocks into the top-level design. Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC). Collaborate with the packaging team to refine bump placement and package routing considerations. Signal and Power Integrity Familiarity with signal and power integrity concepts in high-performance memory systems. Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation. Perform thermal and power integrity analysis to ensure reliable designs. Knowledge of advanced packaging techniques and considerations, an added plus Design-for-Test (DFT) Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms. Contribute to DFT-based timing closure activities. About You Bachelor's degree & 8 years of related experience or Master's degree & 6 years of related experience Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits Experience developing high-speed digital layouts, including DDR and other high-speed interfaces Handling chip assembly and ensure seamless integration of multiple IP blocks into the top-level design Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC) Worked with architects and RTL teams to develop physical constraints and optimize their design Integrate PHYs, controllers, and memory stacks into the top-level design Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation Experience with advanced packaging technologies, such as 2.5D/3D integration, TSV, and interposer-based designs Handle micro-bump design to ensure proper alignment and minimize resistance Understand the SIPI impacts of bump placement Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms Strong communication and articulation skills are required to excel in this role What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits includingcrechereimbursement, as well as a retirement plan,so thatyou can feel secure in your health,financial futureand child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law. Show more Show less

About Marvell . Your Team, Your Impact Central Engineering (CCDS) - ASIC India in Marvell is a Custom Logic Design and Methodology group responsible for delivering complex ASIC chips. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements. What You Can Expect The candidate Marvell is looking for will have: Very good knowledge on SCAN/ATPG/JTAG/MBIST Good Knowledge and understanding on JTAG for IEEE1149. 1/6 standards Proficiency in Industry standard Tools for Scan insertion, ATPG, MBIST and JTAG. (Preferably Synopsys/Mentor tools) Proven experience on Test structures for DFT, IP Integration, ATPG Fault models, test point insertion, coverage improvement techniques Proven experience in Scan insertion techniques at block level and Chip top level Good hands on experience on Memory BIST generation, Insertion, verification on RTL/Netlist level Cross domain knowledge to resolve DFT issues with design, synthesis, Physical design, STA team Good knowledge on Perl/ Tcl scripting Proven experience on gate level simulations with notiming and SDF based simulations Experience with Post-Si ramp up and debug on ATE Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization High sense of responsibility and ownership within the team for successful Tapeout and Post -Si ramp up of the project. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and at least 5 years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-4 years of experience. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

JOB description 4-14years Very good knowledge on SCAN/ATPG/JTAG/MBIST Experience with one or more chip tape out that includes chip ATE bring up. Experience on gate level simulation with no timing and timing (SDF) simulations (ATPG/MBIST/JTAG) Experience in Test structures for DFT, IP integration, ATPG fault models, test point insertion, coverage improvement techniques. Experience in scan insertion techniques at block level and chip top level. Experience on Memory BIST generation, insertion, verification on RTL/Netlist level. Good knowledge and understanding in Analog PHY and Analog Macro tests. Good knowledge and understanding on JTAG for IEEE 1149.1/IEEE1149.6 standards. Good knowledge on test mode timing constraints Good knowledge about running block level and chip STA flows. Cross domain knowledge to resolve DFT issues with design, synthesis, physical design, STA team. Proficiency in industry standard tools for scan insertion, ATPG, MBIST and JTAG (preferable Cadence/Tessent tools) Experience with post-silicon bring up and debug on ATE. Good knowledge on Perl/Tcl scription skills Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization. High sense of responsibility and ownership within the team for successful tape out and post-silicon bring up of project. Should have B-Tech/M-tech with 5 Years to 15 Years relevant experience. Show more Show less

LEAD SOFTWARE SYSTEMS DESIGN ENGINEER THE ROLE: AMD is looking for an experienced engineer for an exciting role in Server CPU software development team. This person will be a member of a core team and will work with the latest hardware and software technology. The person will interact closely with key AMD technical experts to ensure the best possible performance and results on AMD platforms. THE PERSON: The successful candidate for this position will be interacting with software and hardware technologists working across many locations. This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. KEY RESPONSIBILITIES: Problem solving across multiple software layers, (user space, kernel, applications, libraries) and hardware. Optimization/development of the CPU performance stack (applications, libraries) for AMD server and workstation processors on Windows platform. Analyze and solve performance, scalability bottlenecks when code is running on multi-core, multi-node deployments. Innovate and publish papers, patents and participate in technical conferences to advance AMD technologies. Continuously learn and grow along with evolving X86 server CPU architecture and application landscape. PREFERRED EXPERIENCE: Image processing skills: Color format conversions, Image Filtering and Enhancement operations, Morphological operations, Image transforms and statistical operations. Good understanding in Image Detection, Segmentation, Recognition, Restoration and Medical Imaging. Knowledge in Signal Processing theory like Sampling, Quantization, DFT and FFT. Multi-threaded FFT computing, Distributed FFT computing Very strong data structure and algorithmic skills. Experience in identifying performance bottlenecks, and designing/implementing optimizations to relieve analyzed bottlenecks. Strong Windows internals with experience in software development using C/C++ and debugging skills on multicore systems (preferably using OpenMP). Experience in performance analysis for data center, HPC (High Performance Computing), MPI (Message passing Interface) applications. Experience in x86 (or other architecture based) optimizations. Understanding of Cache sub-system, Instruction Set Architecture, pipeline (for any CPU). Bonus skills: Experience on Intel MKL libraries, Linear Algebra, x86 assembly programming (vector/SIMD), porting source code from Linux to Windows, development on Windows servers Knowledge of one or more CPU Profiling tools (preferably in Windows). ACADEMIC CREDENTIALS: Graduate/master s degree in computer science or related fields LOCATION: Bangalore Benefits offered are described: AMD benefits at a glance .

Responsibilities As a creative design engineer with a knowledge of subsystems and SoCs you will be part of a team developing Subsystems & SoCs. You will work the Architecture team to gather the requirements and develop Micro-architecture specifications for one or more SOC Infrastructure areas such as Power management, Debug, Clocks, Resets. Your key responsibilities will include writing micro-architecture specifications, developing the RTL, fixing bugs and running various design checks. You will work with the verification team to review test plans, and help debug design issues. You will work with the Power and Performance analysis team to evaluate and improve Subsystem/SOC PPA. You will also contribute to developing and enhancing the design methodologies used by the team. You will guide and support other members of the team as needed to enable the successful completion of project activities. You will balance other opportunities such as working with Project Management on activities, plans, and schedules Required Skills and Experience: In addition to bringing your accomplishment of either Bachelors or Master s degree or equivalent experience in Computer Science or Electrical/Computer Engineering. Experience of 5+ years working in design of complex compute subsystems or SoCs, you will need: Expertise in creating Micro-architecture and Design specifications for the SoC Infrastructure areas such as Power management, Debug, Clocks and Resets. Strong knowledge of digital hardware design and Verilog HDL. A thorough understanding and experience of the current design techniques for complex SoC development. Experience leading and developing RTL for Subsystems or SoCs. Conversant with Lint, CDC and RDC flows. Good communication (written, verbal, presentations) skills. Experience with Perl, Python or other scripting language Desired Skills and Experience: Experience with ARM-based designs and/or ARM System Architectures Experience developing subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet Experience with SystemVerilog and verification methodologies UVM/OVM Experience leading small teams or projects Experience or knowledge in the following areas Synthesis and timing analysis Static design checks, including CDC, RDC, X-Propagation, Linting Power management techniques DFT and physical implementation #LI-KR2 Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm

Job Details: : Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU. Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications: Qualifications: B.Tech with 3+ years or M.Tech with 2+ Years of hands-on experience with end-to-end SD flow - synthesis to GDS using industry standard EDA tool, with a proven track record of successful projects. Has good understanding on timing methodology, constraints building etc. Experience in floorplaning concepts and actual work, and integration of hierarchical design Good understanding and experience with multiple power domains designs. Have hands on experience on LV flow and clean up. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI the next era of computing. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life s work, to amplify human imagination and intelligence. Make the choice to join us today. NVIDIA is an equal opportunity employer. We are now looking for a DFT Verification Engineer. Design-for-Test (DFT) Engineering at NVIDIA works on groundbreaking innovations every day involving crafting creative solutions for DFT architecture, implementation, verification and post-silicon validation on some of the industrys most complex semiconductor chips. We use the best industry tools and go beyond with internal methodologies to address some of NVIDIAs unique challenges. We are looking for you to implement the best verification methodologies for DFT IP at unit and system levels. You will bring in expertise in SystemVerilog, UVM, FPGA and Emulation application in DFT domain. What youll be doing: As a member of our team, You will build "state of the art" verification test benches and methodologies to verify DFT features in complex IPs/Sub-systems/SOCs. Develop and own verification environment using UVM or equivalent. Your responsibility will include to build reusable bus functional models, monitors, checkers and scoreboards. Own functional coverage driven verification closure and own design verification sign-offs at multiple levels. Collaborate closely with multi-functional teams like chip architecture, ASIC design, functional verification, and post silicon teams. Will be part of innovation to strive to improve the quality of DFT methods What we need to see: BSEE with 3+ or MSEE with 2+ years of experience in IP verification or related domains Expertise in System Verilog and verification methodologies like UVM/VMM. Expertise in prototyping, verification and debug tools (Emulation, FPGA, VCS, Debussy, Formality, PrimeTime etc). Good exposure to ASIC design methodologies: RTL design, clocking, timing and low-power architectures. Strong programming/scripting skills in C++, Perl, Python or Tcl Excellent written and oral communication skills Excitement to work on rare challenges Strong analytical and problem solving skills Ways to stand out from the crowd: Strong experience or interest in both DFT and RTL Verification domains Knowledge in Formal verification methodologies and tools for IP and SoC level verification Hands-on experience in post silicon debug on ATE and/or system labs. #LI-Hybrid

What We Offer At Magna, you can expect an engaging and dynamic environment where you can help to develop industry-leading automotive technologies. We invest in our employees, providing them with the support and resources they need to succeed. As a member of our global team, you can expect exciting, varied responsibilities as well as a wide range of development prospects. Because we believe that your career path should be as unique as you are. Group Summary Transforming mobility. Making automotive technology that is smarter, cleaner, safer and lighter. That’s what we’re passionate about at Magna Powertrain, and we do it by creating world-class powertrain systems. We are a premier supplier for the global automotive industry with full capabilities in design, development, testing and manufacturing of complex powertrain systems. Our name stands for quality, environmental consciousness, and safety. Innovation is what drives us and we drive innovation. Dream big and create the future of mobility at Magna Powertrain. Job Responsibilities Job title: PCB Layout Design Engineer Job Introduction We are seeking a highly skilled PCB Layout Design Engineer with 5+ years of experience and expertise in designing Power Electronics PCBs with Altium Designer EDA tool. As a PCB Design Engineer, you will be responsible for designing and developing printed circuit boards for automotive Traction Inverter, Power electronics & Mixed signal electronic systems. Major Responsibilities Develop, design, validate and optimize complex Power Electronics PCB layouts using Altium Designer, ensuring adherence to IPC standards and best practices. Perform PCB Library creation, schematic capture, component placement, routing and generate manufacturing files considering signal integrity, power integrity, and EMI/EMC requirements. Perform Design rules settings in Altium designer EDA tool following specified Clearance and Creepage standards and other DFM specifications. Create Altium Schematic and Footprint Libraries according to IPC standards and reliable to Manufacturer specifications and managing the database. Create and maintain accurate PCB design documentation, including design guidelines, Fabrication and Assembly Notes/drawings. Work closely with hardware engineers, Mechanical engineers, Manufacturing Engineers and software teams to create PCB that meeting required specifications. Conduct and participate in design reviews, offering insights and suggestions to enhance the functionality and manufacturability of designs. Estimate timeline and plan PCB layout workflow and ensure Layout completion within Projected timeline. Knowledge And Education Bachelor’s or master’s degree in electrical engineering or a related field. Work Experience 5+ years of experience Hands-on experience in PCB layout design for power electronics, Traction inverters and Converters and motor drives. Skills And Competencies Proficiency in Altium Design EDA tool is must. Ability to read electrical schematic and good understanding about hardware design lifecycle. Basic understanding of Signal Integrity, Power Integrity and EMI/EMC. Strong knowledge in DFM, DFM & DFT. Solid understanding of basic Electrical and Electronics principles. Strong problem-solving skills and ability to work independently or in a team. Experience in the automotive sector is desirable. Conscientious, precise and independent way of working. Very good written and spoken English skills. Awareness, Unity, Empowerment At Magna, we believe that a diverse workforce is critical to our success. That’s why we are proud to be an equal opportunity employer. We hire on the basis of experience and qualifications, and in consideration of job requirements, regardless of, in particular, color, ancestry, religion, gender, origin, sexual orientation, age, citizenship, marital status, disability or gender identity. Magna takes the privacy of your personal information seriously. We discourage you from sending applications via email or traditional mail to comply with GDPR requirements and your local Data Privacy Law. Worker Type Regular / Permanent Group Magna Powertrain Show more Show less

HI Greetings for the day!!1 I am hiring for TOP MNC for VLSI Design Engineer, check the attached JD for more clarity, kindly revert with below details ON swati@thinkpeople.in Total Experience Rel Exp Current CTC Exp ctc Location Notice period Current org primary skill ; Skills : PD / DV / AMS / DFT / ASIC OR RTL Design: (please mention) JD; Analog Circuit Design Lead : TitleMandatory Skills Experience : 7+ years Responsibilities :1. Experience in entire Analog IP development including circuit design, layout, AMS verification, and characterization.2. Must have led the entire Analog IP development cycle and team.3. Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc.4. Analog/custom layout design in advanced CMOS process.5. Ability to understand design constraints and implement high-quality layouts.6. Conceptualize and implement chip-level mixed signal simulation environments (testbenches, run scripts, etc...).7. Characterization.8. Hands-on experience on lower FINFET technology nodes and design/PPA trade-offs DFT Interface with ASIC design teams to ensure DFT design rules and coverages are met. Generate high-quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques. MBIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Work with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting post-silicon debug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE. Developing, enhancing and maintaining scripts as necessary. Preferred Experience : Bachelor's degree in Computer Science, Electrical/Electronics Engineering 7 to 12 years' experience in ASIC/DFT - simulation and Silicon validation. Should have worked in at least one Full chip DFT Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement. In-depth knowledge and hands-on experience in ATPG - coverage analysis. In-depth knowledge of Memory verification, repair and failure root-cause analysis. Experience with any of these tools is required: ATPG - TestKompress, MBIST - MentorETVerify, Simulation - VCS (preferred), ModelSim. Expertise in scripting languages such as Perl, shell, etc. is an added advantage. Ability to work in an international team, dynamic environment with good communication skills. Ability to learn and adapt to new tools, methodologies. Ability to do multi-tasking & work on several high-priority designs in parallel. RTL Role : ASIC RTL Engineer / Digital Design Exp : 7 + Mandatory Skill : • RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory • PCIe/DDR/Ethernet - Any One • I2C,UART/SPI - Any One • Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One • Scripting languages like Make flow, Perl ,shell, python - Any One Good to have : • processor architecture / ARM debug architecture • debug issues for multiple subsystems • create/review design documents for multiple subsystems • Able to support physical design, verification, DFT and SW teams on design queries and reviews Details JD : Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint, CDC) Knowledge of synthesis and low power is a plus Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) Good understanding of timing concepts Knowledge of one or more of the interface protocols a. PCIe b. DDR c. Ethernet d. I2C, UART, SPI PD; Floor Planning/Innovus/Fusion Compiler Experience on programming in Tcl/Tk/Perl. Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. DV Must Have: SV/UVM Test Bentch Developement Any Protocols: (PCI Express or UCIe, CXL or NVM • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR or LPDDR or HBM) • 8+ years of hands-on DV experience in System Verilog/UVM. •Must be able to own and drive the verification of a block / subsystem or a SOC. •Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. •Must have extensive experience in verification of one or more of the following: •PCI Express or UCIe, CXL or NVM • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR or LPDDR or HBM • ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages • Power Aware Simulations using UPF

Arcadis is the world's leading company delivering sustainable design, engineering, and consultancy solutions for natural and built assets. We are more than 36,000 people, in over 70 countries, dedicated to improving quality of life. Everyone has an important role to play. With the power of many curious minds, together we can solve the world’s most complex challenges and deliver more impact together. Role description: We are now recruiting for an Assistant/Engineer with experience in transportation planning and modelling for our Mobility Advisory group in the GEC Bangalore office to support project delivery focusing on supporting project managers to deliver their project objectives and outcomes. Role accountabilities: Experience in transport modelling (e.g. highways, public transport, multimodal modelling, junction modelling). Knowledge and awareness in transport planning and strategy development (e.g., development planning, Transport Assessment, active travel) Experience of specification, delivery and application of strategic transport models. Proven ability to build, calibrate and validate traffic models with minimum supervision and experience in implementing demand models. Proven experience in PTV VISUM/VISSIM/CUBE/SATURN modelling suite. Experience with spreadsheet analysis and spreadsheet-based models. Knowledgeable user of data analytics and mapping tools (GIS) and able to interpret quantitative transport models. Ability to support the delivery of transport technical documents including Excel, GIS and Word skills, client letters/emails. Ability to work within a team / Working on your own initiative. Aptitude to learn and diversify skill base. Good communication skills. Good organisational skills. Mathematics and Statistic skills are all important. Strong problem solving and attention to detail. Ability to come up with practical solutions. Enthusiastic, Willing to learn, Punctual, Reliable, Committed. Qualifications & Experience: Degree qualified or equivalent essential (e.g. transport planning, civil engineering, geography, economics, mathematics or data science). Additional qualifications in a relevant discipline would be desirable. Working towards a professional qualification with a relevant professional institution (CIHT, ICE, RTPI) desirable. Nice to Have: Knowledge and understanding of Department for Transport’s Transport Appraisal Guidance (TAG). Experience of working with strategic transport clients such as National Highways, HS2, DfT, Welsh Government, Regional Transport Bodies for role 1 and for role 2 with developers, key clients such as Hs2, airports, local authorities etc. Experience in more than one Strategic modelling platform i.e, SATURN, EMME, CUBE, VISUM. Experience in Operational Modelling Platform i.e., VISSIM/SYNCHRO/LINSIG/AIMSUN Have an interest in developing digital skills such as data analysis or Python coding. Why Arcadis? We can only achieve our goals when everyone is empowered to be their best. We believe everyone's contribution matters. It’s why we are pioneering a skills-based approach, where you can harness your unique experience and expertise to carve your career path and maximize the impact we can make together. You’ll do meaningful work, and no matter what role, you’ll be helping to deliver sustainable solutions for a more prosperous planet. Make your mark, on your career, your colleagues, your clients, your life and the world around you. Together, we can create a lasting legacy. Join Arcadis. Create a Legacy. Our Commitment to Equality, Diversity, Inclusion & Belonging We want you to be able to bring your best self to work every day which is why equality and inclusion is at the forefront of all our activities. Our ambition is to be an employer of choice and provide a great place to work for all our people. We are an equal opportunity employer; women, minorities, and people with disabilities are strongly encouraged to apply. We are dedicated to a policy of non-discrimination in employment on any basis including race, caste, creed, colour, religion, sex, age, disability, marital status, sexual orientation, and gender identity. #JoinArcadis #CreateALegacy #Hybrid Show more Show less

Arcadis is the world's leading company delivering sustainable design, engineering, and consultancy solutions for natural and built assets. We are more than 36,000 people, in over 70 countries, dedicated to improving quality of life. Everyone has an important role to play. With the power of many curious minds, together we can solve the world’s most complex challenges and deliver more impact together. Role description: We are now recruiting for an Assistant/Engineer with experience in transportation planning and modelling for our Mobility Advisory group in the GEC Bangalore office to support project delivery focusing on supporting project managers to deliver their project objectives and outcomes. Role accountabilities: Experience in transport modelling (e.g. highways, public transport, multimodal modelling, junction modelling). Knowledge and awareness in transport planning and strategy development (e.g., development planning, Transport Assessment, active travel) Experience of specification, delivery and application of strategic transport models. Proven ability to build, calibrate and validate traffic models with minimum supervision and experience in implementing demand models. Proven experience in PTV VISUM/VISSIM/CUBE/SATURN modelling suite. Experience with spreadsheet analysis and spreadsheet-based models. Knowledgeable user of data analytics and mapping tools (GIS) and able to interpret quantitative transport models. Ability to support the delivery of transport technical documents including Excel, GIS and Word skills, client letters/emails. Ability to work within a team / Working on your own initiative. Aptitude to learn and diversify skill base. Good communication skills. Good organisational skills. Mathematics and Statistic skills are all important. Strong problem solving and attention to detail. Ability to come up with practical solutions. Enthusiastic, Willing to learn, Punctual, Reliable, Committed. Qualifications & Experience: Degree qualified or equivalent essential (e.g. transport planning, civil engineering, geography, economics, mathematics or data science). Additional qualifications in a relevant discipline would be desirable. Working towards a professional qualification with a relevant professional institution (CIHT, ICE, RTPI) desirable. Nice to Have: Knowledge and understanding of Department for Transport’s Transport Appraisal Guidance (TAG). Experience of working with strategic transport clients such as National Highways, HS2, DfT, Welsh Government, Regional Transport Bodies for role 1 and for role 2 with developers, key clients such as Hs2, airports, local authorities etc. Experience in more than one Strategic modelling platform i.e, SATURN, EMME, CUBE, VISUM. Experience in Operational Modelling Platform i.e., VISSIM/SYNCHRO/LINSIG/AIMSUN Have an interest in developing digital skills such as data analysis or Python coding. Why Arcadis? We can only achieve our goals when everyone is empowered to be their best. We believe everyone's contribution matters. It’s why we are pioneering a skills-based approach, where you can harness your unique experience and expertise to carve your career path and maximize the impact we can make together. You’ll do meaningful work, and no matter what role, you’ll be helping to deliver sustainable solutions for a more prosperous planet. Make your mark, on your career, your colleagues, your clients, your life and the world around you. Together, we can create a lasting legacy. Join Arcadis. Create a Legacy. Our Commitment to Equality, Diversity, Inclusion & Belonging We want you to be able to bring your best self to work every day which is why equality and inclusion is at the forefront of all our activities. Our ambition is to be an employer of choice and provide a great place to work for all our people. We are an equal opportunity employer; women, minorities, and people with disabilities are strongly encouraged to apply. We are dedicated to a policy of non-discrimination in employment on any basis including race, caste, creed, colour, religion, sex, age, disability, marital status, sexual orientation, and gender identity. #JoinArcadis #CreateALegacy #Hybrid #LI-MS4

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today. NVIDIA is an equal opportunity employer. We are now looking for a DFT Verification Engineer. Design-for-Test (DFT) Engineering at NVIDIA works on groundbreaking innovations every day involving crafting creative solutions for DFT architecture, implementation, verification and post-silicon validation on some of the industry's most complex semiconductor chips. We use the best industry tools and go beyond with internal methodologies to address some of NVIDIA's unique challenges. We are looking for you to implement the best verification methodologies for DFT IP at unit and system levels. You will bring in expertise in SystemVerilog, UVM, FPGA and Emulation application in DFT domain. What you'll be doing: As a member of our team, You will build "state of the art" verification test benches and methodologies to verify DFT features in complex IP's/Sub-systems/SOC's. Develop and own verification environment using UVM or equivalent. Your responsibility will include to build reusable bus functional models, monitors, checkers and scoreboards. Own functional coverage driven verification closure and own design verification sign-offs at multiple levels. Collaborate closely with multi-functional teams like chip architecture, ASIC design, functional verification, and post silicon teams. Will be part of innovation to strive to improve the quality of DFT methods What we need to see: BSEE with 3+ or MSEE with 2+ years of experience in IP verification or related domains Expertise in System Verilog and verification methodologies like UVM/VMM. Expertise in prototyping, verification and debug tools (Emulation, FPGA, VCS, Debussy, Formality, PrimeTime etc). Good exposure to ASIC design methodologies: RTL design, clocking, timing and low-power architectures. Strong programming/scripting skills in C++, Perl, Python or Tcl Excellent written and oral communication skills Excitement to work on rare challenges Strong analytical and problem solving skills Ways to stand out from the crowd: Strong experience or interest in both DFT and RTL Verification domains Knowledge in Formal verification methodologies and tools for IP and SoC level verification Hands-on experience in post silicon debug on ATE and/or system labs. #LI-Hybrid

Arcadis is the world's leading company delivering sustainable design, engineering, and consultancy solutions for natural and built assets. We are more than 36,000 people, in over 70 countries, dedicated to improving quality of life. Everyone has an important role to play. With the power of many curious minds, together we can solve the world’s most complex challenges and deliver more impact together. Role Description: You will support a wide range of transport planning services, including but not limited to: Multimodal transport strategy development Future mobility planning (EVs, MaaS, alternative fuels) Business case and funding bid support Multimodal and junction modelling Pedestrian and active travel planning Feasibility studies and concept design Transport inputs to masterplanning and planning applications Behaviour change and sustainable travel strategies Local operational modelling and transport assessments Role Accountabilities: Experience in transport modelling (e.g. highways, public transport, multimodal) Knowledge of strategic model development and application Proficiency in tools such as VISUM, VISSIM, SATURN, CUBE or Experience with operational modelling (e.g. LINSIG, SYNCHRO, AIMSUN ) Strong skills in data analysis, spreadsheet modelling, and GIS Ability to contribute to technical reports and client communication Good problem-solving, organisation, and communication skills A proactive, motivated approach with a willingness to learn and collaborate Nice to have : Familiarity with DfT’s Transport Appraisal Guidance (TAG) Exposure to working with public sector clients (e.g. HS2, National Highways, DfT) or developers Interest or experience in Python coding or data analysis Qualifications and Experience: Degree in a relevant field (e.g. Transport Planning, Civil Engineering, Geography, Economics, Mathematics, or Data Science) Working towards or interested in professional qualification (CIHT, ICE, RTPI) Why Arcadis? We can only achieve our goals when everyone is empowered to be their best. We believe everyone's contribution matters. It’s why we are pioneering a skills-based approach, where you can harness your unique experience and expertise to carve your career path and maximize the impact we can make together. You’ll do meaningful work, and no matter what role, you’ll be helping to deliver sustainable solutions for a more prosperous planet. Make your mark, on your career, your colleagues, your clients, your life and the world around you. Together, we can create a lasting legacy. Join Arcadis. Create a Legacy. Our Commitment to Equality, Diversity, Inclusion & Belonging We want you to be able to bring your best self to work every day which is why equality and inclusion is at the forefront of all our activities. Our ambition is to be an employer of choice and provide a great place to work for all our people. We are an equal opportunity employer; women, minorities, and people with disabilities are strongly encouraged to apply. We are dedicated to a policy of non-discrimination in employment on any basis including race, caste, creed, colour, religion, sex, age, disability, marital status, sexual orientation, and gender identity. #JoinArcadis #CreateALegacy #Hybrid #LI-MS4

Job Title: Quality Control (QC) Manager – Radiator Transformer Industry Location: Vadodara Job Summary: We are seeking a skilled and detail-oriented Quality Control (QC) Manager to lead and manage the QC function in our radiator manufacturing division for power transformers. The QC Manager will ensure that all products meet rigorous internal standards and comply with applicable industry norms such as ISO 9001, ISO 14001, IEC/ANSI standards for transformer components. Key Responsibilities: Develop, implement, and maintain quality control systems and procedures for radiator and transformer component production. Ensure compliance with industry standards and customer specifications. Oversee incoming material inspections, in-process inspections, and final product quality checks. Conduct root cause analysis for non-conformance issues and lead corrective and preventive action (CAPA) initiatives. Maintain documentation such as inspection reports, test certificates, NCRs, calibration records, and audit findings. Coordinate with Production, Design, and Procurement teams to ensure smooth quality integration across functions. Manage a team of quality inspectors, lab technicians, and quality engineers. Liaise with customers and third-party inspection agencies for product validation, FAT (Factory Acceptance Testing), and audits. Implement continuous improvement methodologies such as 5S, Six Sigma, and Kaizen. Train team members on quality tools, customer requirements, and regulatory compliance. Qualifications: Bachelor's degree in Mechanical / Electrical Engineering or related technical field. Minimum 5–8 years of QC experience in heavy engineering or transformer component manufacturing (preferably radiator/fabrication shop). Strong knowledge of welding quality standards (ASME/AWS), painting/coating standards, pressure testing, and sheet metal fabrication. Familiarity with ISO 9001:2015 QMS implementation and audits. Proficiency in using measuring instruments like Vernier, micrometer, UT gauge, DFT meter, etc. Experience with ERP systems and QC documentation software. Job Type: Full-time Pay: ₹50,000.00 - ₹70,000.00 per month Schedule: Day shift Work Location: In person

We are looking for Program manager for Hyderabad Location Key Responsibilities: Manage multiple VLSI projects end-to-end Plan resources, track progress, and ensure timely delivery Handle client communication and project reporting Identify risks and drive issue resolution Work with cross-functional teams (RTL, DV, PD, DFT, etc.) Requirements: 5+ years of experience in VLSI/semiconductor industry Strong project or program management skills Good communication and coordination abilities Tech background (B.Tech/M.Tech); MBA is a plus Available to join within 30 days Show more Show less

Position Title: Electrical CAD Designer Electrical CAD Position Electrical Designer for complete PCBA design cycle from schematic to Gerber generation and electrical drawings such as wiring harnesses. Main Functions/Responsibilities  Design Printed Circuit Board Assemblies (PCBAs) using toolsets Cadence Allegro and Altium.  Design PCBAs from schematic to Gerber generation, layer stack up and DFA, DFM, DFT analysis.  Design and edit PCBAs as per customer requirements and all applicable Schlumberger standards.  Make and maintain electrical drawings such as wiring harnesses and connectors using AutoCAD.  Prepare and update BOMs in the Client Product File Database.  Study and understand component datasheets to collect information for the circuit design.  Learn and follow all relevant standards specific to Schlumberger for PCB Design and library creation.  Update the Internal checklists and standards as per continuous feedback from the customers.  Effectively coordinate with interfacing personnel and/or groups, and provides timely updates to the team lead. Education Diploma in Electrical or Electronics Engineering from a premier Diploma college in India. Work Experience 3 to 6 years work experience in a similar position. Skills and Qualifications Required  Experience in PCB design for multilayer boards.  Good knowledge of Cadence Allegro.  Sound Electrical or Electronics knowledge.  Attention to quality and detail is paramount.  Knowledge of English with good oral and written communication skills. Desired (Optional)  Knowledge of IPC standards (Institute for Interconnecting and Packaging Electronic Circuits).  Knowledge of EMI/EMC & Signal integrity issues for analog and digital boards including high frequency boards.  Understands the schematics and basic functionality of schematic flow.  Knowledge of CAD tools Altium, Mentor Graphics and AutoCAD is preferred.  Knowledge of CAD tool ProE is a plus. Show more Show less