ASIC Engineer 2

Acesoft Labs

3 - 7 years

5 - 9 Lacs

hyderabad

Posted:20 hours ago| Platform:

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Skills Required

tempus innovus asic genus sta rtl synthesis timing analysis rtl functional testing rtl design design compiler dft timing closure

Work Mode

Work from Office

Job Type

Full Time

Job Description

Synthesis & STA Engineers:
Synthesis & STA engineers will perform RTL Synthesis to achieve the best Performance/ Power/ Area of the designs, DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation.
Proven hands-on experience on Design compiler/ Genus/ Fusioncompiler
Experience timing analysis/debug and driving the timing convergence for complex blocks and release the netlists to PD team
Ability to own and release the complex blocks from RTL to netlist with timing QOR, CLP cleanup, Check timing, DFT constraint integration.
Ability to work with RTL design team to identify the must changes in RTL to coverge the timing and work with PD teams to analyze the post route timing and support the final timing closure.
Hands-on experience constraint development for synthesis from scratch is a plus
Excellent problem-solving skills.
Team player with great interpersonal communication skills.

Experience

Tools

Based out of Hyderabad/Bangalore location

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