9 Tempus Jobs

Job Title: STA Full-Chip Lead Location: Bangalore / Hyderabad / Noida / Chennai (Hybrid or On-site) Experience: 8 18 Years Job Type: Full-Time | Permanent Industry: Semiconductor / VLSI / ASIC Design Functional Area: Physical Design / STA / Timing Signoff Job Description We are seeking an experienced and detail-oriented Full-Chip STA Lead to join our high-performance ASIC/SOC design team. You will be responsible for leading full-chip static timing analysis (STA) efforts, driving timing convergence, and managing STA signoff activities across multiple blocks and subsystems. This is a lead-level role requiring deep technical expertise in STA flows and tools, as well as the ability to collaborate with cross-functional teams including RTL, PnR, DFT, and physical verification. Key Responsibilities Own and drive full-chip STA flow , methodology, and signoff. Define and manage SDC constraints for top-level and multi-mode/multi-corner (MMMC) analysis. Perform setup/hold, cross-talk, IR drop-aware timing analysis , and provide ECO guidance for convergence. Collaborate with physical design, RTL, and DFT teams to resolve timing issues across partitions. Work closely with tool/methodology teams to define STA automation, reports, and dashboard mechanisms . Perform signoff-level timing checks : SI, CRPR, path-based analysis, and report generation. Drive STA-related reviews, documentation, and inter-team discussions to meet tapeout timelines. Participate in floorplan feasibility and clock architecture discussions to reduce timing risks early. Support timing correlation between RTL vs. netlist, PnR vs. signoff, and signoff vs. silicon validation. Required Skills & Qualifications B.E/B.Tech or M.E/M.Tech in Electronics/ECE/VLSI or equivalent. 814 years of hands-on STA experience in ASIC/SoC designs, including at least 3 years in a full-chip lead role . Proven track record in closing full-chip STA at advanced nodes (7nm, 5nm, 3nm, or 16FF+). Strong hands-on experience with PrimeTime, Tempus , and industry-standard STA flows. Deep understanding of clock tree structures, multi-mode/multi-corner (MMMC) , and signoff flows. Excellent debugging and scripting skills (Tcl, Perl, Python). Experience with low power design (UPF), hierarchical STA, and ECO timing flows. Exposure to physical design flows and PnR tool interactions (ICC2, Innovus) is highly desirable. Nice to Have: Experience with signoff dashboards and automation frameworks. Familiarity with EMIR-aware timing analysis (RedHawk/Voltus). Experience in STA correlation with post-silicon measurements. Why Join Us? Work on next-generation SoCs in AI, Automotive, Mobile, and Networking domains. Opportunity to lead critical tapeout projects with Tier-1 customers. Fast-track leadership growth with technically challenging and rewarding work. Competitive compensation, training, and certification support.

Principal STA / Synthesis Engineer Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore A US based well-funded product-based startup looking for Highly talented Engineers for the following roles. Constraint development Constraint management Constraint validation Chip top level synthesis, sta and Timing Closure. RTL2GDS flow. Ability to handle synthesis,sta, lec, upf flow methodologies. TCL/perl/python scripting. Candidate with 12-17 yrs exp in Synthesis / STA role Experience in handling complex data path-oriented multi-million gate synthesis Working Knowledge of Physical synthesis using tools like Genus, Design Compiler Experience in debugging for multi-clock domains hierarchical/flat timing analysis. Hands-on experience in LEC along with strong debugging skills for resolving issues/aborts. Netlist and constraint sign in checks and validation. Prime time constraint development at full chip level and clean up. Multimode multi corner timing knowledge and timing closure at block/top level using tools like DMSA Excellent debugging skills in timing convergence issues and ability to come up with creative solutions . Technical leadership and ability to mentor and make the team deliver. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Senior Staff / Staff Physical Design Engineer - STA Bangalore (Hybrid ) / Hyderabad (Hybrid ) Company Background We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics. Full Time \ Experienced Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Static Timing Analysis Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, but with a special focus on static timing analysis: developing and debugging constraints, specifying timing ECOs, and driving overall timing convergence on a complex, large die size, high-speed networking device. Roles and Responsibilities Perform STA (static timing analysis) at block/full-chip level Specify timing ECOs either manually or via a tool-generated flow Perform noise analysis at the block/full-chip level Develop and debug timing constraints Define and implement MCMM (multi corner, multi-mode) timing closure methodology Drive and implement hierarchical timing methodologies to close timing at full-chip Skills/Qualifications : Proficient in STA tools like Tempus, Tweaker, and PrimeTime Proficient in programming languages like Tcl, python, etc. Experience with timing constraint verification tools, such as TimeVision or FishTail, is a plus Experience defining and developing timing closure methodologies in 7nm, 5nm, and/or 3nm Previous experience integrating timing constraints for high-speed IO such as SerDes and/or DDR Strong understanding of LVF/OCV variation methodologies and their implementation Knowledge of timing convergence in multi-voltage scenarios Working knowledge using timing derates and implementing timing derates into the flows Minimum BSEE/CE + 12 years or MSEE/CE + 10+ years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

This role is based in Bangalore. But youll also get to visit other locations in India and globe, so need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is the role: Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Can you collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution! An ability to work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on groundbreaking technologies (7nm and forward). We require to develop & deploy training and technical support to customers using Siemens EDA tools. We dont need superheroes, just superminds! Experience & Qualifications: We are looking out for a candidate with ME/M.Tech in VLSI or Microelectronics with 7+ years of experience in RTL2GDSII, Physical Design with mainstream synthesis and P&R tools. We are looking for someone with hands on experience in Synthesis, DFT insertion, Logical Equivalence and Physical Design. We need hands-on experience with commercial synthesis tools such as Genus, DC, Fusion Compiler which is a must. Tapeout experience of 2 or more projects or proficient experience in implementation CAD flows and methodology. Hands on knowledge on place & route tools like Synopsys-lCC2, Cadence-Innovus or Aprisa and Logical Equivalence tools like Conformal is an advantage. Good understanding of timing, power, and area trade-offs. Knowledge on Static Timing concepts, hands on knowledge on Tempus, Primetime, knowledge on Physical Verification, DRC/LVS, IR drop analysis, hands on mPower etc is a plus. Do you have the ability to pick up new flows, learn on the job and influence QOR? Strong verbal and written communication skills; good presentation skills; good problem solving and debugging skills.

Senior Principal / Principal / StaffPhysical Design Engineer - STA Bangalore (Hybrid ) / Hyderabad (Hybrid ) Company Background We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics. Full Time \ Experienced Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Static Timing Analysis Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, but with a special focus on static timing analysis: developing and debugging constraints, specifying timing ECOs, and driving overall timing convergence on a complex, large die size, high-speed networking device. Roles and Responsibilities Perform STA (static timing analysis) at block/full-chip level Specify timing ECOs either manually or via a tool-generated flow Perform noise analysis at the block/full-chip level Develop and debug timing constraints Define and implement MCMM (multi corner, multi-mode) timing closure methodology Drive and implement hierarchical timing methodologies to close timing at full-chip Skills/Qualifications : Proficient in STA tools like Tempus, Tweaker, and PrimeTime Proficient in programming languages like Tcl, python, etc. Experience with timing constraint verification tools, such as TimeVision or FishTail, is a plus Experience defining and developing timing closure methodologies in 7nm, 5nm, and/or 3nm Previous experience integrating timing constraints for high-speed IO such as SerDes and/or DDR Strong understanding of LVF/OCV variation methodologies and their implementation Knowledge of timing convergence in multi-voltage scenarios Working knowledge using timing derates and implementing timing derates into the flows Minimum BSEE/CE + 12 years or MSEE/CE + 10+ years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

This role is based in Bangalore. But youll also get to visit other locations in India and globe, so need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is the role: Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Can you collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution! An ability to work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on groundbreaking technologies (7nm and forward). We require to develop & deploy training and technical support to customers using Siemens EDA tools. We dont need superheroes, just superminds! Experience & Qualifications: We are looking out for a candidate with ME/M.Tech in VLSI or Microelectronics with 7+ years of experience in RTL2GDSII, Physical Design with mainstream synthesis and P&R tools. We are looking for someone with hands on experience in Synthesis, DFT insertion, Logical Equivalence and Physical Design. We need hands-on experience with commercial synthesis tools such as Genus, DC, Fusion Compiler which is a must. Tapeout experience of 2 or more projects or proficient experience in implementation CAD flows and methodology. Hands on knowledge on place & route tools like Synopsys-lCC2, Cadence-Innovus or Aprisa and Logical Equivalence tools like Conformal is an advantage. Good understanding of timing, power, and area trade-offs. Knowledge on Static Timing concepts, hands on knowledge on Tempus, Primetime, knowledge on Physical Verification, DRC/LVS, IR drop analysis, hands on mPower etc is a plus. Do you have the ability to pick up new flows, learn on the job and influence QOR? Strong verbal and written communication skills; good presentation skills; good problem solving and debugging skills.

Physical Design Engineer Location: Bangalore, Hyderabad, Noida Skills/Experience: Hands-on experience in complex SOC/sub-systems implementation using Innovus & Fusion Compiler. Proficient in top-down floorplan and Power Grid methodologies. Experience in signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff. Successful track records of taping out complex IPs & SoCs at 16/10/7/5 nm Power user of Cadence implementation tools, such as Genus, Innovus, Quantus, Tempus, PVS, Voltus . Automation and programming-minded, coding experience in Tcl/Tk/Perl. Experience (years) : 3+ Year Education Qualification: B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Key Responsibilities: Perform block-level STA and ensure timing closure at various design stages. Work with Synopsys Primetime, Cadence Tempus, or equivalent timing closure tools for analysis and optimization. Analyze and refine timing constraints at both pre-layout and post-layout stages. Collaborate with PD HM owners to provide timing feedback during placement, CTS, and routing phases. Generate timing ECOs for final timing closure using DMSA/Tweaker . Conduct MPW/MP/TDRC analysis and work with Infinisim tools as required. Analyze timing reports, debug violations, and propose fixes for efficient sign-off. Work closely with PD and STA engineers to meet design sign-off criteria. Preferred Skills: Expertise in Primetime/Tempus scripting and timing report analysis . Strong understanding of clock tree synthesis (CTS), routing strategies, and timing convergence . Experience in multi-corner, multi-mode (MCMM) timing analysis . Familiarity with low-power design techniques and constraint optimizations . Strong problem-solving and debugging skills in STA and PD workflows . Interested candidates can share their resumes to shubhanshi@incise.in

• Well versed with the Timing Closure (STA), Timing closure methodologies • Pre/Post-layout constraint development to Timing Closure • Handshake with the Design team & Develop functional/DFT constraints • Abstraction expertise like Hyperscale/ILM/ETM Required Candidate profile • RC Balancing & scaling analysis of critical data paths of full chip clock • Automation in PERL, TCL and EDA tool-specific scripting • DMSA @ full chip and custom scripts for timing fixes