31 Tempus Jobs

Role Overview: You will be responsible for performing STA timing fixes, ECO, and Synthesis of complex SOCs at Subsystem level, Block level, and Chip level. Proficiency in tools such as Design compiler, Prime time, and Tempus is required for this role. Key Responsibilities: - Perform STA timing fixes for complex SOCs - Execute ECO (Engineering Change Order) tasks effectively - Conduct Synthesis activities at Subsystem, Block, and Chip levels - Utilize tools like Design compiler, Prime time, and Tempus to optimize timing Qualification Required: - B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent - Minimum of 3 years of experience in the field (Note: No additional details of the company are mentioned in the job description),

About the Role: You will be part of Incise Infotech Limited's expanding VLSI Design team, focusing on Static Timing Analysis (STA) for high-performance chip design projects. This role is suited for individuals with a strong passion for full-chip timing closure, constraint development, and timing verification in advanced technology nodes. Key Responsibilities: - Performing Static Timing Analysis at block and full-chip levels using tools like PrimeTime or Tempus. - Identifying and resolving setup, hold, transition, and other timing violations. - Collaborating closely with RTL, Synthesis, and Physical Design teams to achieve timing closure. - Developing, validating, and managing SDC constraints for different design stages. - Ensuring readiness for timing sign-off through the generation and review of timing reports. - Innovating and automating STA flows to enhance efficiency and result quality. - Working with design teams to meet tape-out schedules and quality benchmarks. - Conducting PPA (Power, Performance, Area) analysis and supporting ECO timing closure. - Providing STA inputs during design reviews to support multiple projects. Required Skillsets: - Proficiency in using STA tools such as PrimeTime, Tempus, etc. - Strong grasp of timing concepts, clock domains, and signal integrity. - Expertise in writing and debugging SDC constraints. - Sound knowledge of CMOS, VLSI design flows, and timing closure methods. - Ability to script in TCL and automate STA reports and flows. - Familiarity with synthesis, floorplanning, and interactions in physical design. - Experience with advanced technology nodes like 7nm, 16nm, 28nm is advantageous. - Effective communication and problem-solving abilities. - Capability to work independently and collaboratively in a dynamic work environment.,

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA is seeking passionate, highly motivated, and creative design engineers to be part of a team working on industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What you'll be doing: In this position, you will expected to lead all block/chip level PD activities. PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges. Help team members in debugging tool/design related issues. Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. What we need to see: BE/BTECH/MTECH, or equivalent experience. 1+ years of experience in Physical Design. Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure. Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation. Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA and timing closure. Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. Ability to multi-task and flexibility to work in global environment. Good communication skills and strong motivation, Strong analytical & Problem solving skills. Proficiency using Perl, Tcl, Make scripting is preferred. Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family NVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-Hybrid

Join our ambitious team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our mission is to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You will have the opportunity to work on groundbreaking products and collaborate with talented hardware and software engineers to create disruptive infrastructure solutions that excite our customers. We are seeking talented engineers experienced in physically implementing large-scale networking and computing semiconductor products. You will be part of a dynamic startup environment and contribute to the full lifecycle of complex chip development, from CAD tool flow setup to physical verification and tapeout. This role is based in India, with options for hybrid/remote work. Candidates capable of in-office participation in Hyderabad or Bangalore are preferred. Responsibilities: - Develop and maintain the CAD tool flow for physical implementation in a cloud-first environment. - Collaborate with architects on chip-level floorplan and block partitioning, considering tradeoffs in functional partitioning and interface complexity. - Design major physical structures like clock architecture, power delivery network, and interconnect topologies. - Execute physical implementation at block, cluster, and top levels, including synthesis, floorplan, timing closure, and tapeout. - Liaise with foundry and library partners on 3rd party IP integration and process technology issues. Skills/Qualifications: - Proven track record in physical implementation of high-performance network switching/routing fabrics, NICs, CPUs, or GPUs in the latest silicon process nodes. - Proficiency in CAD tools like Cadence Genus, Synopsys ICC2, and analysis tools such as Redhawk. - Experience with scripting languages like Perl, Python, and SystemVerilog. - Minimum BSEE/CE + 10 years or MSEE/CE + 5 years experience with products shipped in high volume. Company Background: We are a well-funded startup based in Mountain View, CA, founded by industry veterans and backed by top-tier investors. Our diverse team excels in co-designing hardware/software solutions and has a proven track record in processing global data center traffic. Note: The above job description is based on the mentioned details in the provided job description.,

You should have a strong understanding of EDA tools and flows, with specific experience in Tempus/Primetime. Your expertise should include timing closure (STA) and various timing closure methodologies. You will be responsible for pre/post-layout constraint development towards timing closure and collaborating with the design team to establish functional/DFT constraints. Additionally, you will need to integrate IP level constraints and define multi-voltage/switching aware corners. An understanding of RC/C model selection and expertise in abstraction techniques such as Hyperscale/ILM/ETM will be crucial for this role. You will also be expected to perform RC balancing and scaling analysis for full chip clocks and critical data paths. Proficiency in automation using PERL, TCL, and EDA tool-specific scripting is essential. Experience with DMSA at full chip level and developing custom scripts for timing fixes will also be required. Overall, the role demands a deep understanding of timing closure concepts, strong automation skills, and the ability to work closely with the design team to ensure successful implementation of constraints and fixes.,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes a wide range of tasks such as bringing up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. The ideal candidate for this position must have a minimum of 8+ years of relevant experience. Key qualifications and responsibilities include: - Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, latch transparency handling, 0-cycle, multi-cycle path handling. - Hands-on experience with STA tools such as Prime-time and Tempus. - Experience in driving timing convergence at Chip-level and Hard-Macro level. - In-depth knowledge of cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed-through handling. - Knowledge of ASIC back-end design flows and methods and tools like ICC2, Innovus. - Proficiency in scripting languages such as TCL, Perl, Awk. - Basic knowledge of device phy. - Familiarity with Spice simulation tools like Hspice/FineSim, Monte Carlo, and Silicon to spice model correlation. - Experience in design automation using TCL/Perl/Python. - Familiarity with digital flow design implementation RTL to GDS: ICC, Innovous, PT/Tempus. - Ability to work on automation scripts within STA/PD tools for methodology development. - Good technical writing and communication skills, with a willingness to work in a cross-collaborative environment. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. For accommodation during the application/hiring process, individuals can email disability-accommodations@qualcomm.com or call Qualcomm's toll-free number. Qualcomm expects its employees to adhere to all applicable policies and procedures, including security requirements regarding protection of confidential information. Note: Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through Qualcomm's Careers Site. Unsolicited submissions will not be considered. For more information about this role, please contact Qualcomm Careers.,

Are you ready for a career that presents challenges while also instilling a sense of pride in your work At Ambit, we provide an ideal platform for individuals to work and advance in the field of semiconductor design. Our employees enjoy the freedom to work in their own adaptable ways, with the necessary support to continue learning and improving their skills. We firmly believe that in order for a company to achieve significant growth through innovation, its employees must be empowered to experiment and innovate freely. The positive and vibrant work environment at Ambit reflects our management's dedication to our employees and their values. Join us today for a promising future in semiconductor design services. Qualification: - B.Tech / M.Tech or equivalent from a reputable University Experience: - 7 - 10 years of relevant experience Responsibilities: - Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs. - Conduct timing analysis, validation, and debugging across various Process-Voltage-Temperature (PVT) conditions using tools like Primetime and Tempus. - Utilize Primetime and/or Tempus for STA flow optimization and establish Spice to STA correlation. - Assess different timing methodologies and tools across various designs and technology nodes. - Develop automation scripts within STA and Physical Design (PD) tools to enhance methodologies. - Demonstrate proficiency in technical writing and communication skills while being open to working in a collaborative environment. - Experience in design automation using TCL/Perl/Python. - Knowledgeable in digital flow design implementation from Register Transfer Level (RTL) to Graphic Data System (GDS) using tools like ICC, Innovous, PT/Tempus. - Familiarity with process technology enablement including circuit simulations with tools such as Hspice/FineSim and Monte Carlo simulations. Join Ambit today and be part of an innovative team dedicated to semiconductor design excellence.,

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off. 4. Debug and resolve issues related to timing, signal integrity, and power. 5. Drive closure of physical verification issues such as DRC, LVS, and ERC. 6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling. 7. Work closely with EDA tool vendors to improve design flows and methodologies. 8. Generate and maintain comprehensive documentation for physical design flows and guidelines. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 2. 310 years of experience in physical design for VLSI systems. 3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre. 4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent. 5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 6. Expertise in low-power design techniques and methodologies. Solid understanding of DRC/LVS and parasitic extraction. 7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation. 8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges. 9. Strong communication and collaboration skills to work effectively in cross-functional teams. Preferred Qualifications: 1. Hands-on experience with hierarchical design flows and methodologies. 2. Knowledge of 3D IC and advanced packaging technologies. 3. Familiarity with machine learning or AI applications in physical design optimization. 4. Exposure to hardware security aspects in physical design.

About Marvell Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvells custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, youll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications. What You Can Expect This role is based in Bangalore India. You will work with both local and global team members on the physical design of complex chips and lead the development of advanced methodologies that enable scalable, high-performance implementation. As a Principal Engineer, you will operate at the intersection of technical depth and strategic influence, driving innovation across teams and projects. Architect and lead the development of next-generation physical design methodologies and automation flows. Provide deep technical leadership in RTL-to-GDSII implementation, including synthesis, floorplanning, place and route, clock tree synthesis, and timing closure. Serve as a key technical advisor across multiple projects, influencing design decisions and resolving complex implementation challenges. Collaborate with global cross-functional teams, including RTL, verification, and CAD, to ensure cohesive and optimized design execution. Mentor and coach senior and junior engineers, fostering technical growth and promoting best practices across the organization. Evaluate and drive adoption of emerging EDA tools and technologies in partnership with internal CAD and external vendors. Represent the physical design team in strategic technical discussions with internal and external stakeholders, contributing to roadmap planning and methodology evolution. What We&aposre Looking For Bachelors, Masters, or PhD degree in Electrical Engineering, Computer Engineering, or a related field. 12+ years of progressive experience in back-end physical design and verification, including leadership roles. Deep understanding of RTL to GDSII flows, including synthesis, place and route, clock tree synthesis, and timing closure. Strong expertise in static timing analysis (e.g., PrimeTime, Tempus) and power/signal integrity tools (e.g., Voltus, RedHawk). Proficient in scripting languages such as Python, Perl, Tcl, and Makefile for automation and flow development. Demonstrated experience in developing and deploying physical design methodologies and flows. Strong communication and collaboration skills, with the ability to mentor junior engineers and influence cross-functional teams. Experience working with EDA vendors and evaluating new tools and technologies is a plus. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what its like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are seeking an innovative Senior Physical Design & Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and SoCs. This position is a broad opportunity to optimize performance, yield, and reliability through increasingly comprehensive modeling, insightful analysis, and automation. This work will influence the entire next generation computing landscape through critical contributions across NVIDIA's many product lines ranging from consumer graphics to self-driving cars and the growing domain of artificial intelligence. We have crafted a team of highly motivated people whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. If you are fascinated by the immense scale of precision, craftsmanship, and artistry required to make billions of transistors function on every die at technology nodes as deep as 3 nm, this is an ideal role. What You Will Be Doing Collaborate with technology leads, circuits and systems teams, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off timing in design for world-class silicon performance. Understand corner case timing sign-off risks in the latest 3nm and deeper technology nodes. Develop strategies to mitigate and margin for them. Develop tools and methodologies to improve design performance, predictability, and silicon reliability beyond what industry standard tools can offer. Extensively work with our ASIC Physical Design team to help develop methodologies, flows, and tools across a wide spectrum of domains - STA, constraints, floorplanning, timing and power optimization. Develop world class workflow solutions to aid analysis and improve flow efficiency. What We Need To See Master's Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent work experience 4+ years of relevant work experience Deep understanding of backend design process, especially advanced STA In depth understanding of PT and/or Tempus Expertise in coding -- TCL, Perl, Python. C++ is a plus! Strong communication and interpersonal skills Ways To Stand Out From The Crowd Expertise in developing advanced STA flows

Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Physical Design Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus. Experience in DMSA/Tweaker ECO flows for PPA improvements. Experience in manual timing fixes, ECO generation for MCMM mode corners. Good understanding of SDC constraints and able to translate timing requirements into constraints. Responsible for integrating the blocks, analog Ips for full chip timing analysis. Well aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence. Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management. Participate in Mentoring new joiners in the group on technical skills. Provide inputs for CAD/DA team from Design Implementation perspective. Work closely with Logic design team and Analog teams to provide inputs from physical design and STA. Work closely with DFT team on scan aspects and provide inputs from physical design. Continuously work on methodology and productivity improvements. Qualifications Must have at least 8 years should be related to STA/Synthesis . Must have Involved in high Speed design tape-outs and constraint development across modes. Must have detailed knowledge of Constraints , Signoff closure methodology for STA and RTL2GDS flow is desired Experience in Tcl/Tk, PERL is a Plus. About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrows systems. Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation. At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/ . Show more Show less

Qualcomm India Private Limited is a leading technology innovator that drives digital transformation to create a smarter, connected future for all. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaborating with cross-functional teams, Qualcomm Hardware Engineers develop solutions that meet performance requirements. To qualify for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 6 years of Hardware Engineering experience. Alternatively, a Master's degree with 5+ years of experience or a PhD with 4+ years of experience in Hardware Engineering would be considered. The Qualcomm Noida CPU team is currently seeking individuals to develop high-performance and power-optimized custom CPU cores. Responsibilities include handling complex HMs from RTL to GDS [Synthesis, PNR, Timing]. This position offers the opportunity to work with talented engineers and contribute to designs that enhance performance, energy efficiency, and scalability. Desired experience for this role includes: - 12+ years of experience in Physical design, STA - Proficiency in industry standard tools for physical implementation [Genus, Innovus, FC, PT, Tempus, Voltas, and redhawk] - Strong grasp from floorplan to PRO and timing signoff, as well as understanding IR drop and physical verification - Experience in preparing complex ECOs for timing convergence - Knowledge of power minimization techniques - Experience in deep submicron process technology nodes and high performance/low power implementation methods - Proficiency in Perl and TCL languages Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. If you require an accommodation, you may contact disability-accomodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Please note that staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes for job opportunities at Qualcomm. Unsolicited submissions will not be considered. For more information about this role, please reach out to Qualcomm Careers.,

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Interfacing with customers regarding digital reference flows, including Synthesis Floorplanning Clock tree synthesis Power planning Place and route Timing closure Creating baseline flows to be used by customers as starting point for digital implementation Performing digital place and route and sign-off on small customer designs Creating documentation PPA optimization Bachelors degree with at least 4+ years of design/EDA experience or Masters degree. Strong knowledge of Digital Design Fundamentals, Semiconductor Fundamentals and Static Timing Analysis Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced nodes (7nm and below) preferred. Good programming knowledge in Unix, Shell scripting, perl and importantly TCL Strong customer-facing communication and problem solving skills Strong personal drive for continuous learning and expanding professional skill sets Excellent verbal and written communication skills Familiar With EDA Tool Operation, Setup And Debug Digital: Genus, Innovus, Tempus, Voltus, etc Were doing work that matters. Help us solve what others cant. Show more Show less

Job Description We are seeking an experienced Digital Physical Design Lead to join our Motor drivers Digital design team. The ideal candidate will be responsible for leading physical design implementation of complex digital circuits from RTL to GDSII. Qualifications Key Responsibilities: Lead and mentor a team of physical design engineers Drive full chip physical implementation including synthesis, floor planning, power planning, placement, clock tree synthesis, and routing Develop and maintain physical design methodologies and flows Perform timing closure, power analysis, IR drop sign-off activities Interface with system architects, front-end design and verification teams to achieve optimum design closure Provide technical guidance and review design work of team members Participate in technical reviews and design planning meetings Preferred Skills Min 4 years' experience in the area of Digital Physical design. Strong expertise with industry-standard EDA tools (Cadence preferred enus, Innovus, Tempus, Voltus etc. ) Experience with integration of complex Analog and Flash based IP designs, custom routing. Experience working with RTL2GDS flows for digital implementation, optimization for PPA. Knowledge of SDC constraint development and timing closure techniques Understanding of DFT, low power design techniques, and clock domain crossing Scripting skills in Tcl/Perl/Python Familiar with ESD, IO ring creation, Reliability and Signoff checks. Understanding of signal integrity and power integrity concepts Experience with formal ECO flows About Us Why TI Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We&aposre different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com . Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. About The Team TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment. Show more Show less

At Cadence, we are committed to hiring and developing leaders and innovators who aspire to create an impact in the technology industry. We are currently seeking a Lead Application Engineer for our GCS team based in Bangalore or Noida. As a pivotal leader in electronic design, Cadence leverages over 30 years of computational software expertise to deliver cutting-edge software, hardware, and IP solutions that bring design concepts to life. Our customers, who are among the most innovative companies worldwide, rely on us to deliver exceptional electronic products across various dynamic market applications. Joining Cadence offers you the opportunity to work with state-of-the-art technology in an environment that fosters creativity, innovation, and impact. Our employee-friendly policies prioritize the well-being and career development of our employees, providing ample opportunities for learning and growth. Our inclusive "One Cadence - One Team" culture celebrates diversity and equity, enabling us to innovate, grow, and succeed with our customers. As a Lead Application Engineer in the GCS Organization for MSA (Multiphysics System Analysis), your role involves collaborating with Cadence customers globally to offer post-sales technical consultation for IC level Power System analysis products. You will work closely with customers to resolve complex issues, help them leverage the latest tools, and guide them in implementing software within their design methodologies. This role allows you to broaden and deepen your technical knowledge, gain exposure to industry best practices, and contribute high-impact knowledge content. Additionally, you will have the opportunity to contribute to the development of key technology solutions and provide feedback to enhance product offerings. You will work in a supportive and flexible environment, where your success is a collective effort and passion for technology and innovation drives us forward. **Job Responsibilities:** - Provide technical support for Voltus product from the Multiphysics System Analysis (MSA) toolset, focusing on productivity and customer satisfaction - Support multiple tools/methods, requiring general domain knowledge and business experience - Assist in creating impactful knowledge content in the MSA domain - Work independently at Cadence or customer facilities to deliver quality results according to schedule requirements - Work on problems of moderate scope that may require analysis of situations, data, or tool problems **Qualifications:** - Bachelors Degree in Electrical/Electronics/Electronics and Communication/VLSI Engineering with 5-7 years of related experience - OR Masters with 3-4 years of related experience - OR PhD with 1 year of related experience **Experience And Technical Skills Required:** - 3-7 years of relevant industry experience in EMIR analysis, PDN analysis with digital signoff tools, and Digital Physical implementation - Strong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulation fundamentals - Proficiency in debugging Low power and multiple power domain analysis for chip power integrity sign-off - Understanding of Digital design toolsets of Cadence (Genus/Innovus/Tempus/Conformal) and hardware description languages like VHDL, Verilog, System Verilog - Knowledge of TCL, Perl, or Python scripting **Behavioral Skills Required:** - Strong written, verbal, and presentation skills - Ability to establish a close working relationship with both customer peers and management - Creative problem-solving skills and ability to explore unconventional solutions - Effective collaboration across functions and geographies - Commitment to raising the bar while maintaining integrity Join us at Cadence, where we are dedicated to tackling meaningful challenges and pushing the boundaries of what is possible in technology. Let's solve problems that others can't.,

5+ Years of experience (in STA), Timing analysis, validation and debug across multiple PVT conditions using Tempus, Both block level and full chip timing closure at lower nodes 22nm, 16nm, 5nm, tcl, python scripting, ADI flows/ Cadence flows for STA

As STA engineer , the role would expect the candidate to have deployment of new features and or methodologies related to STA and ECO domain . Scope of the work would cover (but not limited to) STA flow/methodology development, continuous efficiency improvement, Flow development/Support for ECO convergence with tools in STA and ECO domain (PrimeTime, Tempus, Tweaker, PrimeClosure to name a few). There would be challenges for timing convergence at both block and Top level on cutting edge technology on high performance designs would have to be resolved for ensuring successful design tapeouts on time with high quality. Basic Hands-on on Scripting is a must to have for candidate. Specific skills & knowledge Bachelor or Master in Electronics Engineering and specialization in VLSI domain. 5-8 years of hands-on experience in SoC and IP level objectives on low geometry nodes (5/14/16/28/40nm). Experience in Synopsys Cadence tools, low geometry node issues, working with EDA team in reviewing & resolving blocking issues in project Proven experience in delivering timing closure methodology of mixed signal SoC with high speed PHYs, IOs, PMU IP etc. closing analog / digital interfaces timing & signal integrity issues Experience in customizing flows & methodology to meet low power & area objectives of SoC and leading team to execute on time Ability to use scripting languages / automation of Physical Implementation methodology creation and deployment Should have proven experience in demonstrating strong technical leadership to deliver on commitment, anticipation of challenges, assertive communication and excellent team player. Excellent communication skills with proven experience in international relationships

STA setup, convergence, reviews, and signoff for scan Review of Unconstrained endpoints and check timing reports Working proficiency with tcl, python scripting Previous experience with ADI flows for STA preferred

You should have 4 to 8 years of experience in RTL to Netlist Synthesis, specifically in Genus and Design Compiler. Meeting all the DC/Genus exit criteria, including PPA meeting and constraints validation, is a basic requirement. Knowledge of floorplan-based synthesis like DCG is essential. Working closely with RTL designers on constraints debug and feedback on a constant basis is a key aspect of the role. Conducting pre-layout timing analysis and reporting out, as well as post-layout timing analysis for placement, CTS & PRO, are part of the responsibilities. You will be involved in clock gating checks, timing closure, ECOs, and final tapeout timing closure skills across corners and modes. Collaborating with the RTL design team, PD team, and HMs team for overall timing closure for SoC is crucial. Having expertise in tools like Primetime and Tempus is essential. Knowledge of leakage recovery, Vmin targets, and performance versus leakage trade-off for final sign-off is required. Deep scripting knowledge is a must, along with strong soft skills for working with stakeholders. About Company: https://7rayssemi.com/ 7Rays Semiconductors is a provider of end-to-end custom SoC design solutions, including SoC Architecture, RTL design, Design verification, DFT, Physical Design & Analog design. The company focuses on offering services to top semiconductor and system companies for the design of their complex SoCs. Collaborating closely with clients, 7Rays Semiconductors builds effective partnerships to deliver high-quality solutions tailored to their needs. With a skilled engineering team and a track record of successful project executions, the company is dedicated to excellence and innovation in SoC Design, Development, and deployment of customers" products.,

The Sr. Staff Physical Design Engineer position at Lattice Semiconductor in Pune, India offers a dynamic opportunity to join the HW design team focused on IP design and full chip integration. As part of a worldwide community of engineers and specialists, you will have the chance to contribute, learn, innovate, and grow within this fast-paced and ambitious organization. Key responsibilities for this role include implementing and leading the RTL to GDSII flow for complex designs, working on various aspects of physical design such as place & route, CTS, routing, floorplanning, powerplanning, timing, and physical signoff. The ideal candidate will have experience in physical design signoff checks, drive efficiency and quality in physical design flow and methodology, collaborate with internal and external teams, and possess scripting knowledge to enhance design efficiency. Additionally, the successful candidate will play a vital role in FPGA design efforts, drive physical design closure of key ASIC blocks & full chip, maintain design quality through quality checks and signoff, develop strong relationships with global teams, mentor colleagues, and may require occasional travel. Requirements for this role include a BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science or equivalent, along with 12+ years of experience in driving physical design activities for ASIC blocks and full chips. Candidates must have multiple tapeout experience and proficiency in industry-standard physical design tools. The ideal candidate should be an independent problem solver, capable of collaborating with diverse groups across different sites and time zones. Lattice Semiconductor values its employees as the cornerstone of its success and offers a comprehensive compensation and benefits program to attract and retain top talent in the industry. As an international developer of low-cost, low-power programmable design solutions, Lattice is committed to customer success and a culture of innovation and achievement. If you thrive in a results-oriented environment, seek individual success within a team-first organization, and are ready to contribute to a collaborative and innovative atmosphere, Lattice Semiconductor may be the perfect fit for you. Feel the energy at Lattice.,

Qualcomm India Private Limited is seeking a Hardware Engineer to plan, design, optimize, verify, and test electronic systems. In this role, you will work on cutting-edge technologies in areas such as Digital/Analog/RF/optical systems, FPGA, and DSP systems to develop world-class products. Collaboration with cross-functional teams is key to meeting performance requirements and creating innovative solutions. Candidates for this position should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 2 years of Hardware Engineering experience. Alternatively, a Master's degree with 1 year of relevant experience or a PhD in a related field is also acceptable. The Qualcomm Noida CPU team is specifically looking for individuals to contribute to the development of high-performance and power-optimized custom CPU cores. Responsibilities include handling the hardening of complex HMs from RTL to GDS, which involves tasks such as Synthesis, PNR, and Timing. Desired experience for this role includes 2-5 years of experience in Physical design and STA. Proficiency in industry-standard tools for physical implementation such as Genus, Innovus, FC, PT, Tempus, Voltas, and redhawk is required. Candidates should have a strong understanding of the design flow from floorplan to PRO, timing signoff, IR drop, and physical verification aspects. Experience in deep submicron process technology nodes and knowledge of high-performance and low-power implementation methods are preferred. Strong fundamentals and expertise in Perl and TCL language are also desired. Qualcomm offers a dynamic and inclusive work environment where employees have the opportunity to collaborate with some of the most talented engineers in the world. The company is committed to providing reasonable accommodations to support individuals with disabilities during the application/hiring process. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies, and individuals represented by an agency are not authorized to apply through the Qualcomm Careers Site. For more information about this role, please reach out to Qualcomm Careers directly.,

Tech node: 7nm and below Tools: Cadence - Innovus and Tempus, Genus

You should have 4 to 8 years of experience in RTL to Netlist Synthesis, specifically in Genus and Design Compiler. Meeting all the DC/Genus exit criteria, including PPA meeting and constraints validation, is a basic requirement. Additionally, you must have floorplan-based synthesis knowledge like DCG, and work closely with RTL designers on constraints debug and feedback on a constant basis. Your responsibilities will include pre-layout timing analysis and reporting, post-layout timing analysis for placement, CTS & PRO, clock gating checks, and timing closure. You should also have experience in ECOs and final tapeout timing closure skills across corners and modes. Collaboration with RTL design team, PD team, and HMs team for overall timing closure for SoC is crucial. Having knowledge of Primetime and Tempus is essential, along with expertise in leakage recovery, Vmin targets, and performance versus leakage trade-off for final sign-off. Deep scripting knowledge is required, as well as soft skills for working effectively with stakeholders. About the Company: 7Rays Semiconductors (https://7rayssemi.com/) is a provider of end-to-end custom SoC design solutions, covering SoC Architecture, RTL design, Design verification, DFT, Physical Design & Analog design. The company is dedicated to assisting top semiconductor and system companies in designing their complex SoCs. At 7Rays Semiconductors, we focus on establishing strong partnerships with our clients to deliver high-quality solutions tailored to their specific needs. With a skilled engineering team and a successful track record in project execution, we prioritize excellence and innovation in SoC Design, Development, and deployment of customers" products.,

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off. 4. Debug and resolve issues related to timing, signal integrity, and power. 5. Drive closure of physical verification issues such as DRC, LVS, and ERC. 6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling. 7. Work closely with EDA tool vendors to improve design flows and methodologies. 8. Generate and maintain comprehensive documentation for physical design flows and guidelines. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 2. 310 years of experience in physical design for VLSI systems. 3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre. 4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent. 5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 6. Expertise in low-power design techniques and methodologies. Solid understanding of DRC/LVS and parasitic extraction. 7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation. 8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges. 9. Strong communication and collaboration skills to work effectively in cross-functional teams. Preferred Qualifications: 1. Hands-on experience with hierarchical design flows and methodologies. 2. Knowledge of 3D IC and advanced packaging technologies. 3. Familiarity with machine learning or AI applications in physical design optimization. 4. Exposure to hardware security aspects in physical design.

Job Title: STA Full-Chip Lead Location: Bangalore / Hyderabad / Noida / Chennai (Hybrid or On-site) Experience: 8 18 Years Job Type: Full-Time | Permanent Industry: Semiconductor / VLSI / ASIC Design Functional Area: Physical Design / STA / Timing Signoff Job Description We are seeking an experienced and detail-oriented Full-Chip STA Lead to join our high-performance ASIC/SOC design team. You will be responsible for leading full-chip static timing analysis (STA) efforts, driving timing convergence, and managing STA signoff activities across multiple blocks and subsystems. This is a lead-level role requiring deep technical expertise in STA flows and tools, as well as the ability to collaborate with cross-functional teams including RTL, PnR, DFT, and physical verification. Key Responsibilities Own and drive full-chip STA flow , methodology, and signoff. Define and manage SDC constraints for top-level and multi-mode/multi-corner (MMMC) analysis. Perform setup/hold, cross-talk, IR drop-aware timing analysis , and provide ECO guidance for convergence. Collaborate with physical design, RTL, and DFT teams to resolve timing issues across partitions. Work closely with tool/methodology teams to define STA automation, reports, and dashboard mechanisms . Perform signoff-level timing checks : SI, CRPR, path-based analysis, and report generation. Drive STA-related reviews, documentation, and inter-team discussions to meet tapeout timelines. Participate in floorplan feasibility and clock architecture discussions to reduce timing risks early. Support timing correlation between RTL vs. netlist, PnR vs. signoff, and signoff vs. silicon validation. Required Skills & Qualifications B.E/B.Tech or M.E/M.Tech in Electronics/ECE/VLSI or equivalent. 814 years of hands-on STA experience in ASIC/SoC designs, including at least 3 years in a full-chip lead role . Proven track record in closing full-chip STA at advanced nodes (7nm, 5nm, 3nm, or 16FF+). Strong hands-on experience with PrimeTime, Tempus , and industry-standard STA flows. Deep understanding of clock tree structures, multi-mode/multi-corner (MMMC) , and signoff flows. Excellent debugging and scripting skills (Tcl, Perl, Python). Experience with low power design (UPF), hierarchical STA, and ECO timing flows. Exposure to physical design flows and PnR tool interactions (ICC2, Innovus) is highly desirable. Nice to Have: Experience with signoff dashboards and automation frameworks. Familiarity with EMIR-aware timing analysis (RedHawk/Voltus). Experience in STA correlation with post-silicon measurements. Why Join Us? Work on next-generation SoCs in AI, Automotive, Mobile, and Networking domains. Opportunity to lead critical tapeout projects with Tier-1 customers. Fast-track leadership growth with technically challenging and rewarding work. Competitive compensation, training, and certification support.