55 Tempus Jobs

Job Description : Senior Staff Engineer - Power Integrity / IR drop analysis Job Description The PI Signoff / IR Drop Analysis Lead is responsible for Signoff level IR drop, Power/Signal EM analysis of a Subsystem and Full SoC. He is responsible for running EM and Static/Dynamic IR analysis for various modes/power scenarios, root cause failures, provide fixing solutions. He should follow/define best practices and strategy as per technology node. He contributes to problem solving related to overall PI analysis. Responsibilities include EM and IR drop analysis (vector and vectorless) for both block and full chip designs for various power modes and scenarios. Provide feedback / improvement / fi...

Responsibilities: Collaborate with cross-functional teams on project deliverables. Develop testbenches using UVM, USB interfaces, Tempus software. Ensure compliance with industry standards and customer requirements.

We are looking for STA Engineer who is having Exp in Tempus Exp: 7+yrs Loc: BLR If Interested, please share your Profile to my mail id sushma.vunnam@modernchipsolutions.com

Are you looking for a unique opportunity to be a part of something great Want to join a 17,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationa...

Are you looking for a unique opportunity to be a part of something great Want to join a 17,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationa...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Product Engineer Grade: T3 Experience: 4-6 Years Location: Bangalore Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications...

Are you looking for a unique opportunity to be a part of something great Want to join a 17,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationa...

Experience in Cadence digital design tools as Innovus, Tempus, QRC, Voltus, Genus, Conformal LEC Physical Verification with Mentor Calibre or Cadence PVS tools. Exposure to Low-power design and UPF methodology. Required Candidate profile Notice Period (Availability) - Immediate to 15 Days. Good knowledge of TCL Shell PERL Python Scripting.

Job Description: Broadcom is looking for a staff level physical design engineer. In this highly visible role, you will be contributing to ASIC for Storage/ AI products. Qualifications: Education and Experience : Master's degree in Electronics/Computer Engineering with over 10 years of experience in physical design. Physical Design Expertise : Extensive experience in Place & Route using Synopsys FC or Cadence Innovus tools is essential. Proficiency in STA using Primetime and/or Tempus. Demonstrated knowledge of Clock Tree Implementation Techniques for High-Speed Design Implementation. Ability to drive front-end and back-end implementation from RTL to GDSII, including synthesis, formal verific...

Job Title: Physical Design Engineer Experience: 4+ Years Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated Physical Design Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure. Key Responsibilities: Own block-level or full-chip implementation from RTL to GDSII. Perform: Floorplanning and placement Clock tree synthesis (CTS) Routing and optimization Run and close timing (STA), IR drop, EM, DRC, LVS, and a...

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will involve working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Your collaboration with cross-functional teams will be essential in developing solutions and meeting performance requirements. **Key Responsibilities:** - Plan, design, optimize, verify, and test electronic systems - Work on circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, ...

Experience in handling STA of multi-power domain designs & constraint mode merging. Job Description In your new role you will: Defining and verification of STA constraint for Functional and Test/SCANModes. Defining PVT's corners required for covering all desired scenarios for a design Knowledge on OCV/AOCV/POCV derates. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues. VASTA timing closure based on chip IR drop. Knowledge on signal SI analysis and PT-PX flow. Your Profile You are best equipped for this task if you have: BE/B.Tech/M.Tech with 8+ years. Project leading knowledge is preferred. Delivery oriented, Passionate to learn and explore...

Strong experience in Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs Job Description In your new role you will: Implement high-performance, low-power, and area-efficient digital designs. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis. Optimize designs for power, performance, and area, and meet PPA goals. Power analysis using PT-PX or equivalent flow. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs. Define and evaluate constraints and signoff Test/DFT mode timing requirement Your Profile You are best equipped for this task if you have: Strong fundamentals and experi...

Description The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. Roles & Responsibilities: - Collaborate with architecture, timing, and logic design teams making a crucial impact on delivering cutting edge & Low power SOCs. - Perform I/O, bump & RDL (redistri...

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world's most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com. Meet the Team Join a dynamic Physical Design team that drives end-to-end SoC implementation, from RTL to ...

As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. Your responsibilities will include: - Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling - Hands-on experience with STA tools such as Prime-time and Tempus - Driving timing convergence at Chip-level and Hard-Macro level - In-depth knowledge of cross-talk noise, Signal Integrity, Layout Pa...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity ...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity ...

Job Title: STA Design Engineer (Backend) Location: Bangalore Experience: 5+ Years Job Description: We are looking for an experienced STA Design Engineer with strong expertise in Static Timing Analysis (STA) for ASIC/SoC backend design. The candidate should have hands-on experience in timing closure, signoff methodologies, and working closely with physical design and RTL design teams to deliver high-quality silicon. Key Responsibilities: Perform Static Timing Analysis (STA) across multiple process, voltage, and temperature (PVT) corners. Drive timing closure at block and full-chip level. Work on constraint development, validation, and optimization (SDC files). Perform setup, hold, recovery, a...

You have 24 years of experience in ASIC Physical Design and Timing Analysis. Your hands-on expertise includes working with tools such as: - Physical Design: Innovus, ICC2, Fusion Compiler, or similar - STA: PrimeTime, Tempus - Physical Verification: Calibre, Pegasus Open positions available: - PD- 2-4 years (Chennai) - STA - Top level or Fullchip - 4+ years (Bangalore/Pune/Hyderabad) You should have an immediate to 30 days notice period.,

Role : Senior STA Engineer Experience Required : 4-5 YEARS Job Location: HYDERABAD Bachelors or Masters degree in Electrical/Electronics Engineering. Preferred Qualifications: Experience with full-chip STA closure. Exposure to low-power design techniques and multi-mode/multi-corner analysis. Knowledge of timing integration for third-party IPs. Required Skills: Strong understanding of STA fundamentals and timing closure methodologies. Proficiency in tools like PrimeTime, Tempus, Tweaker, Timevision, Fishtail. Experience with scripting languages (TCL, Perl, Python) for automation. Familiarity with advanced nodes (e.g., 7nm, 5nm, FinFET). Good grasp of physical design flow and constraints manag...

As a Qualcomm Hardware Engineer, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems for cutting-edge products. Working closely with cross-functional teams, you will develop innovative solutions to meet performance requirements. **Key Responsibilities:** - 5 to 10 years of experience in static timing analysis, constraints, and other physical implementation aspects - Proficiency in industry standard tools PT, Tempus, GENUS, Innovus, ICC, etc. - Expertise in solving extreme critical timing bottleneck paths and p...

Synthesis & STA Engineers: Synthesis & STA engineers will perform RTL Synthesis to achieve the best Performance/ Power/ Area of the designs, DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation. Proven hands-on experience on Design compiler/ Genus/ Fusioncompiler Experience timing analysis/debug and driving the timing convergence for complex blocks and release the netlists to PD team Ability to own and release the complex blocks from RTL to netlist with timing QOR, CLP cleanup, Check timing, DFT constraint integration. Ability to work with RTL design team to identify the must changes in RTL to coverge the timing and work with PD t...

Job Overview As a part of in Arm&aposs Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities Timing analysis and closur...

Role Overview: You will be responsible for performing STA timing fixes, ECO, and Synthesis of complex SOCs at Subsystem level, Block level, and Chip level. Proficiency in tools such as Design compiler, Prime time, and Tempus is required for this role. Key Responsibilities: - Perform STA timing fixes for complex SOCs - Execute ECO (Engineering Change Order) tasks effectively - Conduct Synthesis activities at Subsystem, Block, and Chip levels - Utilize tools like Design compiler, Prime time, and Tempus to optimize timing Qualification Required: - B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent - Minimum of 3 years of experience in the field (Note: No addition...