STA Engineer

Allegis Services India

4 - 8 years

20 - 30 Lacs

hyderabad

Posted:7 hours ago| Platform:

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Skills Required

sta finfet primetime timing closure perl tempus rtl timevision synthesis timing analysis full chip tweaker static timing analysis timing fishtail tcl python

Work Mode

Work from Office

Job Type

Full Time

Job Description

Role

Experience Required

Job Location:

Preferred Qualifications:

Experience with full-chip STA closure.
Exposure to low-power design techniques and multi-mode/multi-corner analysis.
Knowledge of timing integration for third-party IPs.

Required Skills:

Strong understanding of
STA fundamentals and timing closure methodologies.
Proficiency in tools like PrimeTime, Tempus, Tweaker, Timevision, Fishtail.
Experience with scripting languages (TCL, Perl, Python) for automation.
Familiarity with advanced nodes (e.g., 7nm, 5nm, FinFET).
Good grasp of physical design flow and constraints management.
Ability to debug timing issues and propose effective solutions.

Key Responsibilities

Good Experience with writing constraints.
Analyzing timing reports.
Basic scripting knowledge.
Basic understanding of RTL.
Experience with PT(Primetime) and can write DC/PT timing constraints.
Collaborate with physical design and synthesis teams to resolve timing violations.
Analyze timing paths and optimize for setup, hold, and clock skew issues.
Work on multi-voltage domains and low-power design techniques (e.g., UPF).
Support timing signoff and tape-out activities.

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