4.0 - 8.0 years

20 - 30 Lacs

hyderabad

Work from Office

Role : Senior STA Engineer Experience Required : 4-5 YEARS Job Location: HYDERABAD Bachelors or Masters degree in Electrical/Electronics Engineering. Preferred Qualifications: Experience with full-chip STA closure. Exposure to low-power design techniques and multi-mode/multi-corner analysis. Knowledge of timing integration for third-party IPs. Required Skills: Strong understanding of STA fundamentals and timing closure methodologies. Proficiency in tools like PrimeTime, Tempus, Tweaker, Timevision, Fishtail. Experience with scripting languages (TCL, Perl, Python) for automation. Familiarity with advanced nodes (e.g., 7nm, 5nm, FinFET). Good grasp of physical design flow and constraints manag...

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STA(Static Timing Analysis) Engineer Capgemini Engineering

5.0 - 7.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Experience : 5+years Location : Bangalore Job Description: As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process corners. Key Responsibilities: Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages. Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs. Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus). Collaborate with design and archi...

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