STA Engineer

Job Role:

You will collaborate effectively with cross-functional teams, communicate complex timing data clearly.

Roles and Responsibilities:

• 5+ years of related work experience
• Developing timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs.
• Check timing for unconstrained endpoints, no clock, etc.
• Your role may include SDC validation, CDC delay check, and SDC flow development.
• Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.

Preferred Qualifications

• Background in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST.
• Prior working experience with SDC debugging & STA tools: Synopsys GCA/TCM/Primetime.
• Prior working experience with synthesis tools: Synopsys Fusion Compiler.
• Prior working experience with Tessent tool: DFT insertion in RTL.
• Strong communication skills and team player.