Responsibilities: * Collaborate with cross-functional teams on bug resolution. * Ensure software compliance with functional requirements. * Develop verification environments using UVM/SV methodology.
As a Static Timing Analysis (STA) Engineer at the company in Singapore, you will play a crucial role in the SoC design team, focusing on timing signoff and analysis of cutting-edge IPs and chips in advanced process nodes. Your expertise in using Synopsys NanoTime or similar tools will be essential for the success of the projects. Key Responsibilities: - Perform full-chip and block-level Static Timing Analysis using NanoTime - Collaborate with physical design and RTL teams to ensure timing closure - Apply timing constraints and execute timing ECOs as necessary - Run timing analysis across various PVT corners and modes - Provide support for design sign-off activities such as STA, SI, cross-talk, and OCV - Optimize timing performance while considering power and area trade-offs Qualifications Required: - Bachelor's or Master's degree in Electrical/Electronics Engineering or a related field - Minimum of 4 years of experience in STA, preferably with NanoTime or PrimeTime - Proficient in STA concepts, PVT corners, constraints (SDC), and timing reports - Familiarity with advanced process nodes like 7nm, 5nm, or lower - Scripting skills in TCL, Perl, or Python for automation - Good understanding of digital design flow and timing closure,