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Capgemini
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STA Engineer

STA Engineer

Capgemini

5 - 9 years

0 Lacs

karnataka

Posted:1 month ago| Platform: Shine logo

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Skills Required

static timing analysis synopsys primetime perl python soc design upf serdes gpio cadence tempus tcl asic constraint debugging plls adcdac hsio lowpower design techniques

Work Mode

On-site

Job Type

Full Time

Job Description

Role Overview: As an STA Engineer, your primary responsibility will be timing closure and verification of complex ASIC or SoC designs. You will collaborate closely with cross-functional teams, including physical design, logic design, and architecture, to ensure timing requirements are met across various design stages and process corners. Key Responsibilities: - Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages - Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs - Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus) - Collaborate with design and architecture teams to define timing requirements and resolve violations - Analyze timing scenarios, margins, and corner cases - Integrate third-party IPs and derive timing signoff requirements - Optimize timing paths and reduce signoff corners by merging modes - Automate STA flows using scripting languages - Support test mode timing closure (e.g., scan shift, scan capture, BIST) Qualifications Required: - Strong expertise in Static Timing Analysis (STA) using tools like Synopsys PrimeTime and Cadence Tempus - Proficient in writing and validating SDC constraints - Skilled in TCL, Perl, Python for automation - Solid understanding of ASIC/SoC design flows, including synthesis and physical design - Experience with corner and mode analysis, process variations, and signal integrity - Familiarity with constraint debugging tools like Synopsys GCA (Galaxy Constraint Analyzer) - Exposure to tools such as Genus, Timevision, Fishtail, Tweaker - Knowledge of low-power design techniques (UPF, multi-voltage domains, power gating) - Experience integrating custom IPs (PLLs, SerDes, ADC/DAC, GPIO, HSIO) - Strong communication and collaboration skills - Ability to mentor junior engineers - Familiarity with advanced process nodes (3nm, 5nm, 7nm, FinFET) (Note: Any additional details of the company were not present in the provided job description.),

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STA Engineer