STA Engineer

Job Title: Static Timing Analysis (STA) Engineer

Job Overview

Static Timing Analysis (STA) Engineer

Key Responsibilities

• Perform

  Static Timing Analysis

  (setup, hold, recovery, removal) across all PVT corners and modes.
• Create, refine, and validate

  SDC constraints

  including clocks, generated clocks, false paths, and multi-cycle paths.
• Drive

  timing closure

  during synthesis, place & route, and final signoff.
• Debug timing violations related to

  clocking, logic depth, routing, buffering,

  and

  cell sizing

  .
• Work closely with RTL, Physical Design, CTS, and DFT teams to resolve timing issues.
• Run STA using tools such as

  Synopsys PrimeTime

  or

  Cadence Tempus

  .
• Analyze

  SI/crosstalk

  ,

  OCV/AOCV/POCV

  , and apply advanced timing methodologies.
• Ensure full timing signoff criteria are met before tape-out.

Required Qualifications

• 310 years

  of hands-on STA experience (can adjust based on your needs).
• Bachelor's or Master's in

  Electrical Engineering

  ,

  Electronics

  ,

  VLSI

  , or related field.
• Strong understanding of

  digital logic, timing concepts, and CMOS fundamentals

  .
• Experience with

  PrimeTime, Tempus, ICC2, Fusion Compiler, or Innovus

  .
• Solid knowledge of

  SDC

  , timing exceptions, and multi-clock domain analysis.
• Proficiency in

  Tcl

  , with additional scripting (Python/Perl) being a plus.

Preferred Skills

• Experience with

  SoC-level

  STA and hierarchical timing flows.
• Knowledge of

  clock tree synthesis (CTS)

  and clock architecture.
• Familiarity with

  low-power design

  (UPF/CPF).
• Understanding of

  DFT timing

  , scan modes, and test constraints.

Soft Skills

• Strong analytical and debugging abilities.
• Excellent communication and documentation skills.
• Ability to work in a fast-paced, cross-functional environment.