9 Sdc Constraints Jobs

About the Role: You will be part of Incise Infotech Limited's expanding VLSI Design team, focusing on Static Timing Analysis (STA) for high-performance chip design projects. This role is suited for individuals with a strong passion for full-chip timing closure, constraint development, and timing verification in advanced technology nodes. Key Responsibilities: - Performing Static Timing Analysis at block and full-chip levels using tools like PrimeTime or Tempus. - Identifying and resolving setup, hold, transition, and other timing violations. - Collaborating closely with RTL, Synthesis, and Physical Design teams to achieve timing closure. - Developing, validating, and managing SDC constraints for different design stages. - Ensuring readiness for timing sign-off through the generation and review of timing reports. - Innovating and automating STA flows to enhance efficiency and result quality. - Working with design teams to meet tape-out schedules and quality benchmarks. - Conducting PPA (Power, Performance, Area) analysis and supporting ECO timing closure. - Providing STA inputs during design reviews to support multiple projects. Required Skillsets: - Proficiency in using STA tools such as PrimeTime, Tempus, etc. - Strong grasp of timing concepts, clock domains, and signal integrity. - Expertise in writing and debugging SDC constraints. - Sound knowledge of CMOS, VLSI design flows, and timing closure methods. - Ability to script in TCL and automate STA reports and flows. - Familiarity with synthesis, floorplanning, and interactions in physical design. - Experience with advanced technology nodes like 7nm, 16nm, 28nm is advantageous. - Effective communication and problem-solving abilities. - Capability to work independently and collaboratively in a dynamic work environment.,

Job Description : KEY RESPONSIBILITIES: Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Ensuring timing correlation between PnR <-> STA and timely feedbacks to PD team Generating block level HS session and using Top context from SoC for Block-SoC Interface timing closure. Generating timing ECO using Tweaker/PrimeClosure. Job Requirement: PREFERRED EXPERIENCE: 5+ years of experience in timing closure of high frequency blocks (> GHz range) Analyzing the timing reports and identifying both design and constraints related issues. Worked on blocks with multiple power and voltage domains Preferred EDA tool experience: Primetime, Tweaker/PrimeClosure, Innovus Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation Strong understanding of SDC constraints, OCV,AOCV,POCV analysis Strong TCL/scripting knowledge is mandatory. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electrical Engineering

Lead and develop timing methodologies, establish SDC constraints, and automate processes for special timing checks, ensuring design convergence and managing ECOs effectively. Perform static timing analysis setup and sign-off for multi-corner, multi-voltage processes to align with PPA targets, initially at the hierarchical level and subsequently at the top-level, reviewing the timing arcs for the .lib generation. Collaborate closely with RTL, DFT, and IP teams to ensure smooth integration and address physical design concerns affecting scan shift and scan capture modes for DFT. Identify opportunities to optimize clock skew and insertion delay across various corners and modes. Evaluate the clock/reset-domain-crossing (CDC/RDC) issues at the netlisting stage and offer feedback on design fixes or establish waivers if the changes are not feasible. Implement power-saving strategies, such as power gating, multi-voltage domains, and clock gating, to meet low-power objectives while preserving performance standards. Create and refine custom scripts using Tcl, Perl, or Python to enhance workflow efficiency and streamline physical design operations. Mentor and support junior physical design engineers, disseminating best practices and providing technical guidance to elevate team proficiency and performance. PREFERRED EXPERIENCE: Over 8-10+ years of professional experience in constraints generation, synthesis, static timing analysis (STA), and IP-level timing and physical design, with a preference for high-performance SerDes designs. Proven ability in timing analysis, convergence, timing ECOs, and .lib generation. Experience with STA closure on PHYs & understanding the timing requirements across digital and analog macro interfaces is a plus. Proficient in physical design tools such as Synopsys ICC2, Primetime, and the ASIC design flow. Skilled in scripting with Tcl, Python, or Perl to automate and streamline physical design tasks. Excellent problem-solving, leadership, and communication skills and values team culture. Capable of thriving in fast-paced environments and managing multiple projects simultaneously.

Experience : 5+years Location : Bangalore Job Description: As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process corners. Key Responsibilities: Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages. Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs. Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus). Collaborate with design and architecture teams to define timing requirements and resolve timing violations. Analyze timing scenarios, margins, and corner cases. Integrate third-party IPs and derive timing signoff requirements. Optimize timing paths and reduce signoff corners by merging modes. Automate STA flows using scripting languages. Support test mode timing closure (e.g., scan shift, scan capture, BIST). Primary Skills: Static Timing Analysis (STA): Deep expertise in STA tools like Synopsys PrimeTime, Cadence Tempus. Timing Constraints Development: Proficient in writing and validating SDC constraints. Scripting Languages: Strong skills in TCL, Perl, Python for automation. ASIC/SoC Design Knowledge: Understanding of synthesis, physical design, and backend flows. Corner and Mode Analysis: Experience with timing corners, process variations, and signal integrity. Constraint Debugging: Familiarity with tools like Synopsys GCA (Galaxy Constraint Analyzer). Secondary Skills: Tool Proficiency: Experience with tools like Genus, Timevision, Fishtail, Tweaker. Low-Power Design: Knowledge of UPF, multi-voltage domains, and power gating. Custom IP Integration: Handling of PLLs, SerDes, ADC/DAC, GPIO, HSIO. Communication & Collaboration: Strong interpersonal skills for cross-functional teamwork. Mentorship: Ability to guide and mentor junior engineers. Process Node Experience: Familiarity with advanced nodes (3nm, 5nm, 7nm, FinFET). Show more Show less

Back Lead Physical Design Engineer Bangalore, India 10+ Full-Time We are seeking an experienced Lead Physical Design Engineer to take ownership of Place-and-Route (PNR) for complex flat SoC designs using Cadence flow. You will lead physical implementation from floorplanning to timing closure, collaborating closely with RTL, STA, DFT, and verification teams. Key Responsibilities Lead physical design execution for flat SoC projects from RTL handoff through GDSII. Perform floorplanning, partitioning, power planning, and clock tree synthesis (CTS). Execute placement, routing, optimization, and sign-off using Cadence Innovus or equivalent tools. Develop and maintain SDC constraints for PNR stages. Drive physical verification (DRC, LVS, antenna checks) and resolve violations. Perform congestion analysis and optimization for flat SoC designs. Work with methodology teams to improve PNR flow and scalability. Mentor junior engineers on PNR best practices and advanced Cadence Innovus features. Qualifications Must-Have: Bachelors or Masters degree in Electrical/Electronics/Computer Engineering or related field. 1012 years of hands-on physical design and PNR experience. Proven ability to handle flat SoC designs in Cadence flow Strong knowledge of floorplanning, CTS, routing, optimization, and sign-off closure. Solid understanding of STA, SDC creation, and ECO flows for physical implementation. Prior technical leadership or mentoring experience. Nice-to-Have Automotive semiconductor experience Low-power implementation (UPF/CPF). Experience with scripting (Tcl, Perl, Python) for automation. Show more Show less

Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Physical Design Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus. Experience in DMSA/Tweaker ECO flows for PPA improvements. Experience in manual timing fixes, ECO generation for MCMM mode corners. Good understanding of SDC constraints and able to translate timing requirements into constraints. Responsible for integrating the blocks, analog Ips for full chip timing analysis. Well aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence. Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management. Participate in Mentoring new joiners in the group on technical skills. Provide inputs for CAD/DA team from Design Implementation perspective. Work closely with Logic design team and Analog teams to provide inputs from physical design and STA. Work closely with DFT team on scan aspects and provide inputs from physical design. Continuously work on methodology and productivity improvements. Qualifications Must have at least 8 years should be related to STA/Synthesis . Must have Involved in high Speed design tape-outs and constraint development across modes. Must have detailed knowledge of Constraints , Signoff closure methodology for STA and RTL2GDS flow is desired Experience in Tcl/Tk, PERL is a Plus. About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrows systems. Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation. At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/ . Show more Show less

We are looking foran adaptive, self-motivative design verification engineer to join our growing team. As a key contributor,you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. TheVerification Engineering team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: we'll versed with timing signoff methodology and corner definitions Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring block/SS level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure PREFERRED EXPERIENCE: 3+ years of experience for timing closure of block/SS Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory. Good understanding of SDC construct( clock generation , false path , multi cycle paths..) ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

As an engineer at Synopsys, you will be a key player in driving innovations that shape the future of technology. Your role will involve working with cutting-edge tools and technologies to ensure the high quality and reliability of Synopsys's PrimeTime tool. You will collaborate with cross-functional teams to tackle complex technical challenges and provide valuable insights that influence the development and validation of future product releases. Your primary responsibilities will include executing and leading product validation of the PrimeTime tool, understanding requirements and functional specifications, and performing in-depth root cause analysis to enhance product quality. You will use your expertise in Static Timing Analysis (STA) and tools like Synopsys PrimeTime to diagnose issues, propose innovative solutions, and ensure the readiness of the product for customer deployment. Your exceptional debugging skills and proficiency in scripting languages like Perl, Tcl, and Python will enable you to streamline processes and improve efficiency. In this role, you will have a significant impact on enhancing customer satisfaction, driving continuous improvements in product design, and contributing to the overall success of Synopsys. You will play a crucial part in deploying cutting-edge technologies in high-performance designs, shaping the future of the semiconductor industry. Your attention to detail, analytical thinking, and problem-solving mindset will be key to maintaining high standards of product quality and reliability. To excel in this role, you should have deep domain knowledge in Static Timing Analysis, a Bachelor's or Master's degree in Electrical Engineering or equivalent, and a minimum of 3-5 years of related experience. Experience with Synopsys PrimeTime, timing analysis, ECO flows, power, SDC constraints, and scripting skills are essential. As a collaborative team player with excellent communication skills, a proactive and self-motivated individual, and someone who thrives in a fast-paced environment, you will be a valuable addition to the product validation team for Synopsys's PrimeTime tool. Join us at Synopsys to transform the future through continuous technological innovation and be part of a team dedicated to ensuring the high quality of tools that drive the semiconductor industry forward.,

Position: STA Lead Engineer Cluster Level Location: Bangalore, India Experience: 8–12 years in Static Timing Analysis (STA) About the Role We are seeking a Static Timing Analysis (STA) Lead to drive cluster-level timing closure for advanced SoCs. The role involves owning STA strategy, guiding a team of 7–8 engineers, and collaborating across RTL, Physical Design, and Sign-off teams to ensure robust, production-ready silicon. Key Responsibilities Lead and mentor a team of STA engineers, providing technical direction, task allocation, and performance feedback. Own cluster-level STA sign-off , including setup/hold, clock skew, jitter, crosstalk, and OCV analysis. Develop and validate SDC constraints and timing methodologies for multiple functional and test modes Collaborate closely with Physical Design, RTL, and DFT teams to achieve timing closure. Drive ECO implementation for timing fixes without impacting functionality. Interface with EDA vendors to resolve tool and flow issues. Ensure delivery schedules are met with high-quality, sign-off-ready timing reports. Contribute to timing methodology improvements and automation for enhanced productivity. Required Skills & Experience 7+ years of hands-on STA experience Strong command over PrimeTime or Cadence Tempus and SDC constraint development. Deep understanding of multi-mode, multi-corner (MMMC) analysis . Proven experience in ECO flow and debugging complex timing paths. Strong leadership, mentoring, and cross-functional coordination skills. Preferred Qualifications Exposure to high-performance computing, AI, or networking SoCs . Familiarity with power-aware STA and UPF/CPF flows. Experience in developing STA automation scripts (Tcl/Perl/Python). Why Join Us? Work on cutting-edge, high-performance SoCs in a collaborative environment where technical leadership and innovation are valued. Be a key contributor to silicon success in next-gen computing architectures.