Senior STA Engineer Advanced Micro Devices (AMD)

3.0 - 8.0 years

4 - 8 Lacs

Bengaluru, Karnataka, India

On-site

We are looking foran adaptive, self-motivative design verification engineer to join our growing team. As a key contributor,you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. TheVerification Engineering team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: we'll versed with timing signoff methodology and corner definitions Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring block/SS level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure PREFERRED EXPERIENCE: 3+ years of experience for timing closure of block/SS Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory. Good understanding of SDC construct( clock generation , false path , multi cycle paths..) ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

Posted 3 days ago

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Test & Validation Engineer, Staff Synopsys

3.0 - 7.0 years

0 Lacs

karnataka

On-site

As an engineer at Synopsys, you will be a key player in driving innovations that shape the future of technology. Your role will involve working with cutting-edge tools and technologies to ensure the high quality and reliability of Synopsys's PrimeTime tool. You will collaborate with cross-functional teams to tackle complex technical challenges and provide valuable insights that influence the development and validation of future product releases. Your primary responsibilities will include executing and leading product validation of the PrimeTime tool, understanding requirements and functional specifications, and performing in-depth root cause analysis to enhance product quality. You will use your expertise in Static Timing Analysis (STA) and tools like Synopsys PrimeTime to diagnose issues, propose innovative solutions, and ensure the readiness of the product for customer deployment. Your exceptional debugging skills and proficiency in scripting languages like Perl, Tcl, and Python will enable you to streamline processes and improve efficiency. In this role, you will have a significant impact on enhancing customer satisfaction, driving continuous improvements in product design, and contributing to the overall success of Synopsys. You will play a crucial part in deploying cutting-edge technologies in high-performance designs, shaping the future of the semiconductor industry. Your attention to detail, analytical thinking, and problem-solving mindset will be key to maintaining high standards of product quality and reliability. To excel in this role, you should have deep domain knowledge in Static Timing Analysis, a Bachelor's or Master's degree in Electrical Engineering or equivalent, and a minimum of 3-5 years of related experience. Experience with Synopsys PrimeTime, timing analysis, ECO flows, power, SDC constraints, and scripting skills are essential. As a collaborative team player with excellent communication skills, a proactive and self-motivated individual, and someone who thrives in a fast-paced environment, you will be a valuable addition to the product validation team for Synopsys's PrimeTime tool. Join us at Synopsys to transform the future through continuous technological innovation and be part of a team dedicated to ensuring the high quality of tools that drive the semiconductor industry forward.,

Posted 4 days ago

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