Static Timing Analysis Engineer

About the Role: You will be part of Incise Infotech Limited's expanding VLSI Design team, focusing on Static Timing Analysis (STA) for high-performance chip design projects. This role is suited for individuals with a strong passion for full-chip timing closure, constraint development, and timing verification in advanced technology nodes. Key Responsibilities: - Performing Static Timing Analysis at block and full-chip levels using tools like PrimeTime or Tempus. - Identifying and resolving setup, hold, transition, and other timing violations. - Collaborating closely with RTL, Synthesis, and Physical Design teams to achieve timing closure. - Developing, validating, and managing SDC constraints for different design stages. - Ensuring readiness for timing sign-off through the generation and review of timing reports. - Innovating and automating STA flows to enhance efficiency and result quality. - Working with design teams to meet tape-out schedules and quality benchmarks. - Conducting PPA (Power, Performance, Area) analysis and supporting ECO timing closure. - Providing STA inputs during design reviews to support multiple projects. Required Skillsets: - Proficiency in using STA tools such as PrimeTime, Tempus, etc. - Strong grasp of timing concepts, clock domains, and signal integrity. - Expertise in writing and debugging SDC constraints. - Sound knowledge of CMOS, VLSI design flows, and timing closure methods. - Ability to script in TCL and automate STA reports and flows. - Familiarity with synthesis, floorplanning, and interactions in physical design. - Experience with advanced technology nodes like 7nm, 16nm, 28nm is advantageous. - Effective communication and problem-solving abilities. - Capability to work independently and collaboratively in a dynamic work environment.,