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Static Timing Analysis Engineer

5 - 9 years

0 Lacs

coimbatore tamil nadu

Posted:1 week ago| Platform: Shine logo

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Skills Required

timing closure eda tools communication leadership mentoring cross functional coordination sta methodologies timing constraints development problemsolving design flow management

Work Mode

On-site

Job Type

Full Time

Job Description

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world's most innovative companies unleash their potential. Our digital and software technology experts provide unique R&D and engineering services across all industries. Join us for a career full of opportunities where you can make a difference and experience diverse challenges every day. Key Responsibilities: - Timing Analysis & Closure: Perform setup, hold, and skew analysis at Full-Chip, Sub-system, and IP levels to achieve timing closure by resolving violations and optimizing paths. - Constraint Development: Define and validate timing constraints including clocks, I/O delays, and false/multi-cycle paths. Integrate constraints from multiple IPs for hierarchical STA. - Tool Usage & Flow Integration: Utilize STA tools like Synopsys PrimeTime, Cadence Tempus, or equivalent. Integrate STA into the overall design flow and automate processes for efficiency. Job Description: As an expert in STA methodologies, you will provide guidance on setup and hold time analysis, clock domain crossing, and multi-cycle paths for Full Chip, Sub-system, and complex IP timing closure. You will define and implement timing constraints such as clock definitions, input/output delays, and path constraints to ensure accurate timing analysis. Additionally, you will integrate existing timing constraints from various IPs for comprehensive timing analysis. Your deep knowledge of STA tools like Synopsys PrimeTime, Cadence Tempus, or Mentor Graphics" ModelSim will be essential in guiding the integration of these tools into the overall design flow for optimal performance. You will oversee the process of achieving timing closure, address any timing violations, and guide optimizations to meet performance goals. Primary Skills: - Deep Technical Knowledge: Demonstrated in-depth understanding of STA concepts, EDA tools, and methodologies. - Problem-Solving Skills: Strong analytical and problem-solving abilities to address complex timing issues. - Communication Skills: Ability to effectively communicate complex technical concepts to various stakeholders. - Leadership and Mentoring: Experience in leading teams and mentoring less experienced engineers in STA practices. Secondary Skills: - Design Flow Management: Improve execution efficiency through flow automation and other value-added processes. - Cross-Functional Coordination: Collaborate closely with other teams such as RTL design, Physical design, verification, and manufacturing to ensure seamless timing closure of physical design. Educational Qualifications: Bachelors or Masters Degree in Electrical Engineering, Electronics & Communication Engineering, VLSI Design, Computer Engineering, or related fields. Capgemini is a global business and technology transformation partner, helping organizations accelerate their transition to a digital and sustainable world. With a diverse team of over 340,000 members across 50 countries, Capgemini leverages its strong heritage and expertise to deliver end-to-end services and solutions. The group's 2023 global revenues were reported at 22.5 billion, demonstrating its commitment to unlocking the value of technology for its clients.,

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Capgemini

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