Company Description Incise Infotech Pvt Ltd is a technology company specializing in Semiconductor Design & IT Services, Semiconductor Product Development, and IT Products. The company is known for providing top talent in various domains, including SOC Verification, IP Verification, RTL Design, and Physical Design, among others. Incise is dedicated to architecting future generations of Semiconductor SOC's and Software Solutions to simplify the life of mankind. Experience : 8+Years Role Description This is a full-time on-site role for a Lead Physical Design Engineer at Incise Infotech Pvt Ltd located in Hyderabad. The Lead Physical Design Engineer will be responsible for tasks related to Physical Design, Physical Verification, Logic Design, Circuit Design, and RTL Design on a day-to-day basis. Qualifications Physical Design and Physical Verification skills Logic Design and Circuit Design skills RTL Design skills Experience in semiconductor design and physical layout Knowledge of STA, Synthesis, and PnR Strong problem-solving and analytical skills Bachelor's or Master's degree in Electrical Engineering or related field Experience with EDA tools like Cadence or Synopsys is a plus Show more Show less
As an Analog Layout Engineer with 3-5 years of experience in advanced semiconductor technologies (5nm and below), you will be responsible for executing full custom layout designs for high-speed analog and mixed-signal blocks. Your expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre will be crucial in collaborating closely with circuit design teams to interpret and implement layout specifications. Your key responsibilities will include performing layout verification, ensuring compliance with foundry design rules and layout best practices, addressing issues related to electromigration, IR drop (EMIR), and layout-dependent effects, as well as optimizing layouts for performance, area, and reliability across PVT corners. Additionally, you will support tape-out and post-layout verification activities, participate in design reviews, and maintain proper documentation of layout guidelines and review skills. You should have proven experience in custom analog layout for high-speed and precision circuits, a strong working knowledge of FinFET nodes, proficiency in layout tools like Cadence Virtuoso and Calibre, and sound knowledge of DRC, LVS, and EMIR verification methodologies. Understanding of layout effects such as matching, shielding, symmetry, and noise isolation, as well as familiarity with EDA scripting (Skill, Tcl, Python), will be beneficial. Strong problem-solving skills, attention to detail, and good communication and collaboration abilities in a team-based environment are essential for success in this role. Join us to work on cutting-edge layout challenges with the latest process technologies and be a part of a fast-growing semiconductor team working on impactful silicon designs. Competitive compensation and career development opportunities await you in this exciting opportunity.,
Company Description Incise Infotech Ltd is a technology company specializing in semiconductor design, IT services, and product development. The company provides services in SOC and IP verification, RTL design, virtual prototyping, memory layout design, IO layout design, analog mixed-signal design, and more. Incise Infotech invites the world's top talent to work on cutting-edge semiconductor SOCs and software solutions, aiming to produce the best practices and products to simplify life. The company's diverse expertise makes it a leader in the technology domain. Role Description This is a full-time, on-site role for a Lead Memory Layout Design Engineer located in Noida. The Lead Memory Layout Design Engineer will be responsible for designing and verifying memory layouts, working on circuit design, and ensuring the quality and functionality of analog circuits. Day-to-day tasks will include layout design, physical verification, and collaborating with other teams to optimize design processes and achieve project goals. 𝐄𝐱𝐩𝐞𝐫𝐢𝐞𝐧𝐜𝐞 : 7+ 𝐘𝐞𝐚𝐫𝐬 𝐋𝐨𝐜𝐚𝐭𝐢𝐨𝐧 : 𝐍𝐨𝐢𝐝𝐚 𝐑𝐞𝐪𝐮𝐢𝐫𝐞𝐝 𝐒𝐤𝐢𝐥𝐥𝐬 & 𝐄𝐱𝐩𝐞𝐫𝐢𝐞𝐧𝐜𝐞 : 🔹7+ years of experience in memory layout design. 🔹Strong expertise in SRAM, ROM, Register File, and other memory architectures. 🔹Proficiency with EDA tools: Cadence Virtuoso, Synopsys Custom Compiler, Mentor Graphics Calibre (DRC/LVS), etc. 🔹Solid understanding of deep sub-micron technologies (16nm, 7nm, 5nm, etc.). 🔹Knowledge of parasitic effects, IR drop, electromigration, and reliability considerations. 🔹Strong debugging, problem-solving, and teamwork skills. 𝐇𝐨𝐰 𝐭𝐨 𝐀𝐩𝐩𝐥𝐲 𝐈𝐧𝐭𝐞𝐫𝐞𝐬𝐭𝐞𝐝 𝐜𝐚𝐧𝐝𝐢𝐝𝐚𝐭𝐞𝐬 𝐜𝐚𝐧 𝐬𝐡𝐚𝐫𝐞 𝐭𝐡𝐞𝐢𝐫 𝐂𝐕 𝐚𝐭 madhuri.tomar@incise.in 𝐰𝐢𝐭𝐡 𝐭𝐡𝐞 𝐬𝐮𝐛𝐣𝐞𝐜𝐭 𝐥𝐢𝐧𝐞: 👉𝐀𝐩𝐩𝐥𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐟𝐨𝐫 𝐌𝐞𝐦𝐨𝐫𝐲 𝐋𝐚𝐲𝐨𝐮𝐭 𝐃𝐞𝐬𝐢𝐠𝐧 𝐄𝐧𝐠𝐢𝐧𝐞𝐞𝐫 – 𝐍𝐨𝐢𝐝𝐚
Requirements 4 to 7 years of experience. Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a related field. Strong expertise in JavaCard technology, GlobalPlatform, and ISO 7816/14443 standards. Hands-on experience in JavaCard applet Testing, secure elements, and smart card testing. This job was posted by Surya Sundar from Incise Infotech.
Immediate Joiners Preferred About the Role : Incise Infotech Limited is expanding its VLSI Design team and is looking for skilled Static Timing Analysis (STA) Engineers to contribute to high-performance chip design projects. This role is ideal for engineers passionate about full-chip timing closure, constraint development, and timing verification in advanced technology nodes. Key Responsibilities Perform Static Timing Analysis at both block and full-chip levels using industry-standard tools such as PrimeTime or Tempus Analyze and debug setup, hold, transition, and other timing violations Work closely with RTL, Synthesis, and Physical Design (PD) teams to drive timing closure Develop, validate, and manage SDC constraints for various design stages Ensure timing sign-off readiness by generating and reviewing timing reports Innovate and automate STA flows for improving efficiency and quality of results Collaborate with design teams to support tape-out schedules and quality metrics Perform PPA (Power, Performance, Area) analysis and support ECO timing closure Support multiple projects by providing STA inputs during design reviews Required Skillsets Hands-on experience in STA tools like PrimeTime, Tempus, etc. Strong understanding of timing concepts, clock domains, and signal integrity Expertise in writing and debugging SDC constraints Solid knowledge of CMOS, VLSI design flows, and timing closure methodologies Proficient in TCL scripting and automation of STA reports and flows Familiarity with synthesis, floorplanning, and physical design interactions Experience with advanced technology nodes (e.g., 7nm, 16nm, 28nm) is a plus Good communication and problem-solving skills Ability to work independently and collaboratively in a fast-paced environment (ref:hirist.tech)
Required Skills / Experience Bachelor's degree in Computer Science (or a related discipline) 4 to 5 years of experience as SDET/Developer Strong analytical and problem solving and communication(both verbal and written)skills Have exposure to frameworks like Rest assured, Selenium and Appium Exposure to AWS or any other cloud ecosystem Good exposure to GIT, Jenkins or similar tools Roles & Responsibilities Collaborate with developers, product managers, and QA teams to design, develop, and execute automated test scripts. Build and maintain automation frameworks using Rest Assured, Selenium, and Appium for web, API, and mobile testing. Ensure high-quality software delivery by identifying, documenting, and tracking bugs, and working with the team to resolve them. Participate in code reviews, design discussions, and contribute to improving test strategies and best practices. Integrate test automation into CI/CD pipelines using Jenkins, Git, or similar tools. Leverage AWS (or other cloud platforms) for testing, deployment, and environment setup. Write clear and concise test plans, test cases, and technical documentation. Continuously enhance automation coverage, optimize execution time, and ensure scalability of test suites. Stay updated with emerging tools, trends, and best practices in test automation and software development. Communicate effectively across teams to ensure clarity on requirements, timelines, and quality goals. Who You Are You are driven to do all kinds of destructive testing You are passionate for Automation First approach You are hands-on and stay up to date with the latest technologies You love problem solving and attention to detail (ref:hirist.tech)
About the Role: You will be part of Incise Infotech Limited's expanding VLSI Design team, focusing on Static Timing Analysis (STA) for high-performance chip design projects. This role is suited for individuals with a strong passion for full-chip timing closure, constraint development, and timing verification in advanced technology nodes. Key Responsibilities: - Performing Static Timing Analysis at block and full-chip levels using tools like PrimeTime or Tempus. - Identifying and resolving setup, hold, transition, and other timing violations. - Collaborating closely with RTL, Synthesis, and Physical Design teams to achieve timing closure. - Developing, validating, and managing SDC constraints for different design stages. - Ensuring readiness for timing sign-off through the generation and review of timing reports. - Innovating and automating STA flows to enhance efficiency and result quality. - Working with design teams to meet tape-out schedules and quality benchmarks. - Conducting PPA (Power, Performance, Area) analysis and supporting ECO timing closure. - Providing STA inputs during design reviews to support multiple projects. Required Skillsets: - Proficiency in using STA tools such as PrimeTime, Tempus, etc. - Strong grasp of timing concepts, clock domains, and signal integrity. - Expertise in writing and debugging SDC constraints. - Sound knowledge of CMOS, VLSI design flows, and timing closure methods. - Ability to script in TCL and automate STA reports and flows. - Familiarity with synthesis, floorplanning, and interactions in physical design. - Experience with advanced technology nodes like 7nm, 16nm, 28nm is advantageous. - Effective communication and problem-solving abilities. - Capability to work independently and collaboratively in a dynamic work environment.,