Incise Infotech Limited

Company Description Incise Infotech Pvt Ltd is a technology company specializing in Semiconductor Design & IT Services, Semiconductor Product Development, and IT Products. The company is known for providing top talent in various domains, including SOC Verification, IP Verification, RTL Design, and Physical Design, among others. Incise is dedicated to architecting future generations of Semiconductor SOC's and Software Solutions to simplify the life of mankind. Experience : 8+Years Role Description This is a full-time on-site role for a Lead Physical Design Engineer at Incise Infotech Pvt Ltd located in Hyderabad. The Lead Physical Design Engineer will be responsible for tasks related to Physical Design, Physical Verification, Logic Design, Circuit Design, and RTL Design on a day-to-day basis. Qualifications Physical Design and Physical Verification skills Logic Design and Circuit Design skills RTL Design skills Experience in semiconductor design and physical layout Knowledge of STA, Synthesis, and PnR Strong problem-solving and analytical skills Bachelor's or Master's degree in Electrical Engineering or related field Experience with EDA tools like Cadence or Synopsys is a plus Show more Show less

Job Title : STA Engineer Experience : 3- 5 Years Location : Noida Immediate Joiners Preferred About the Role : Incise Infotech Limited is expanding its VLSI Design team and is looking for skilled Static Timing Analysis (STA) Engineers to contribute to high-performance chip design projects. This role is ideal for engineers passionate about full-chip timing closure, constraint development, and timing verification in advanced technology nodes. Key Responsibilities Perform Static Timing Analysis at both block and full-chip levels using industry-standard tools such as PrimeTime or Tempus Analyze and debug setup, hold, transition, and other timing violations Work closely with RTL, Synthesis, and Physical Design (PD) teams to drive timing closure Develop, validate, and manage SDC constraints for various design stages Ensure timing sign-off readiness by generating and reviewing timing reports Innovate and automate STA flows for improving efficiency and quality of results Collaborate with design teams to support tape-out schedules and quality metrics Perform PPA (Power, Performance, Area) analysis and support ECO timing closure Support multiple projects by providing STA inputs during design reviews Required Skillsets Hands-on experience in STA tools like PrimeTime, Tempus, etc. Strong understanding of timing concepts, clock domains, and signal integrity Expertise in writing and debugging SDC constraints Solid knowledge of CMOS, VLSI design flows, and timing closure methodologies Proficient in TCL scripting and automation of STA reports and flows Familiarity with synthesis, floorplanning, and physical design interactions Experience with advanced technology nodes (e.g., 7nm, 16nm, 28nm) is a plus Good communication and problem-solving skills Ability to work independently and collaboratively in a fast-paced environment (ref:hirist.tech)

As a Static Timing Analysis (STA) Engineer at Incise Infotech Limited in Noida, you will be a key contributor to the VLSI Design team, working on high-performance chip design projects. Your role will involve performing STA at block and full-chip levels using tools such as PrimeTime or Tempus. You will analyze and debug timing violations, collaborate with RTL, Synthesis, and Physical Design teams for timing closure, and develop SDC constraints for various design stages. Your expertise in timing concepts, clock domains, and signal integrity will be crucial for ensuring timing sign-off readiness and supporting tape-out schedules. Additionally, you will innovate and automate STA flows, support PPA analysis, and provide inputs during design reviews for multiple projects. To excel in this role, you should have hands-on experience with STA tools, a strong understanding of timing concepts, and expertise in writing and debugging SDC constraints. Your solid knowledge of CMOS, VLSI design flows, and timing closure methodologies will be essential. Proficiency in TCL scripting, familiarity with synthesis and physical design interactions, and experience with advanced technology nodes like 7nm, 16nm, or 28nm will be advantageous. Good communication, problem-solving skills, and the ability to work both independently and collaboratively in a fast-paced environment are also required. If you are a passionate engineer looking to contribute to full-chip timing closure, constraint development, and timing verification in advanced technology nodes, this role offers an exciting opportunity to drive innovation and quality in chip design projects at Incise Infotech Limited.,

As a Senior SoC Verification Engineer with over 6 years of industry experience in SoC-level verification, you will play a crucial role in our team. Your responsibilities will include developing and maintaining UVM-based testbenches and testcases, ensuring high verification coverage, and collaborating with design and architecture teams to understand design intent and verification scope. Your expertise in UVM, ARM M-core architecture, and C programming for embedded systems will be essential as you perform functional verification of SoC designs with a focus on quality, coverage, and performance. Utilizing industry tools like Cadence/Synopsys VIP and SimVision for simulation and debugging, you will validate ARM M-core based subsystems and interfaces, including AHB/APB, DMA, Interrupts, and Cache systems. In this high-impact role, your strong debug skills will be put to use as you conduct debug using waveforms, disassembly, and Tarmac trace to isolate and resolve issues. You will also contribute to automation and continuous integration (CI) initiatives to improve verification efficiency. To excel in this role, you must possess excellent verbal and written communication skills for cross-team collaboration, along with good analytical and problem-solving skills with attention to detail. If you are passionate about working on cutting-edge technologies in a collaborative and fast-paced environment, we are excited to hear from you.,