Analog Layout Engineer

As an Analog Layout Engineer with 3-5 years of experience in advanced semiconductor technologies (5nm and below), you will be responsible for executing full custom layout designs for high-speed analog and mixed-signal blocks. Your expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre will be crucial in collaborating closely with circuit design teams to interpret and implement layout specifications. Your key responsibilities will include performing layout verification, ensuring compliance with foundry design rules and layout best practices, addressing issues related to electromigration, IR drop (EMIR), and layout-dependent effects, as well as optimizing layouts for performance, area, and reliability across PVT corners. Additionally, you will support tape-out and post-layout verification activities, participate in design reviews, and maintain proper documentation of layout guidelines and review skills. You should have proven experience in custom analog layout for high-speed and precision circuits, a strong working knowledge of FinFET nodes, proficiency in layout tools like Cadence Virtuoso and Calibre, and sound knowledge of DRC, LVS, and EMIR verification methodologies. Understanding of layout effects such as matching, shielding, symmetry, and noise isolation, as well as familiarity with EDA scripting (Skill, Tcl, Python), will be beneficial. Strong problem-solving skills, attention to detail, and good communication and collaboration abilities in a team-based environment are essential for success in this role. Join us to work on cutting-edge layout challenges with the latest process technologies and be a part of a fast-growing semiconductor team working on impactful silicon designs. Competitive compensation and career development opportunities await you in this exciting opportunity.,