148 Cadence Virtuoso Jobs

JD: Analog Layout, TSMC, Intel, Samsung Foundries Nodes - Finfet like 2nm, 3nm, 5nm, 7 nm Location - HYD interested candidate, Kindly share with me your updated profile to anand.arumugam@modernchipsolutions.com Or call me 9900927620 for Discussion

Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in Analog Layout design Expertise in planar technology node / higher node (180nm - 28nm) is mandatory Expertise in EMIR analysis, ESD, antenna and related layout solutions Knowledge of advanced technology nodes (7nm & below) Good understanding of advanced semiconductor technology process and device physics Full-custom circuit layout/verification and RC extraction experience Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional

Physical Deisgn Lead Location: Bangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl Well versed with timing constraints, STA and timing closure. Mandatory Skills: VLSI Physical Place and Route. Experience: 5-8 Years.

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualification BE/BTech from any reputed University Masters Preferred Experience Between 3 to 10 years Hands on with any of the spice simulators (Hspice/ Spectre)

About The Role : To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification. Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below). Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects. Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks. Primary Skills : Analog Layout Design(Block/IP level) LVS/DRC Debugging FinFET Technology Node Experience(5nm, 7nm, 10nm, 14nm and below) EDA Tools Cadence Virtuoso Editor Calibre RVE Layout Optimization Area estimation Floorplanning Routing Secondary Skills : These support the primary responsibilities and enhance performance: Understanding of Physical Design Concepts: Matching Electromigration (EM) Electrostatic Discharge (ESD) Latch-Up Shielding Parasitics Short Channel Effects Critical Thinking & Problem Solving Interpersonal and Communication Skills Team Collaboration Educational Qualification: Bachelor"s or Master"s Degree.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: Analog Layout . Experience: 3-5 Years .

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory

Key Responsibilities: Perform custom layout design of high-performance and low-power memory blocks (SRAM, ROM, Register Files, CAM, etc.). Work on floorplanning, transistor-level layout, device matching, and parasitic optimization. Ensure DRC/LVS clean layouts with adherence to foundry design rules. Collaborate with circuit design teams to achieve optimal PPA (Performance, Power, Area). Conduct parasitic extraction, EM/IR analysis, and reliability checks for memory layouts. Deliver high-quality layouts meeting project deadlines and silicon success. Required Skills: Strong expertise in memory layout (SRAM, ROM, CAM, Register Files). Hands-on experience with Cadence Virtuoso, Mentor Calibre, Synopsys tools. Deep knowledge of foundry design rules (DRC, LVS, ERC, ANT, etc.). Familiarity with advanced process nodes (7nm/5nm/3nm preferred). Strong understanding of layout-dependent effects (LDE), electromigration, IR drop. Good communication and ability to work in cross-functional teams. Good to Have: Experience with automation scripts (Perl/Python/Tcl) for layout productivity. Knowledge of EDA flow development for memory layout. Experience in custom analog layout is a plus. Education: B.E/B.Tech/M.Tech in Electronics, Electrical, VLSI, or related field.

About The Role This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; About The Role - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

The Reference Design t eam, Bangalore , is looking for a talented and motivated candidate to work in the broad area of Silicon Photonics circuit design The candidate should have strong background in: 1. Silicon photonics device physics, circuit design fundamentals. 2. Hands-on experience with Ansys Lumerical suite, and other simulation softwares 3. Hands-on experience with Cadence Virtuoso Schematic and Layout editors , Klayout Your Job : Design the various silicon photonics circuits to meet target specifications a nd cater to different applications . Layout of the designed circuits Measure the design on hardware and analyze the results Analyze the impact of device characteristics on circuit-level performance Understand the critical circuit specifications which are important for achieving system-level performance Help with automation and other efficiency improvement projects Other Responsibilities: Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs. Required Qualifications : Requires Master s Degree ( M.S/ M.Tech ) with Specialization in Electronics or Electrical Engineering ( Photonics and related fields) from a reputed university, with g ood academic records and with minimum 6 years of experience or a PhD with Specialisation in Photonics or Integrated Optics from a reputed university, with good academic records with minimum 4 years of experience Must be self-motivated and excellent team player Must have good technical verbal and written communication skills and ability to work with cross functional global teams Be able to collaborate with program and technical design leads on multiple concurrent projects. Preferred Qualifications: Knowledge in various technologies , process and characterization techniques is desired Patents and publications will be a good advantage. Exceptional Spoken and Written Proficiency in English Strong analytical and problem-solving skills. Strong ability to learn and explore new technologies , opportunities, and continuous improvement. Ability to interact effectively with both external and internal customers at all levels and from various cultural backgrounds.

Design the various silicon photonics circuits to meet target specifications a nd cater to different applications . Layout of the designed circuits Measure the design on hardware and analyze the results Analyze the impact of device characteristics on circuit-level performance Understand the critical circuit specifications which are important for achieving system-level performance Help with automation and other efficiency improvement projects Other Responsibilities: Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

As an Analog Design Engineer at our company, you will utilize your 6+ years of experience to design and develop high-speed SerDes systems for CHIP to CHIP Communication interfaces. You will be responsible for creating and validating high-performance, low-power analog circuits, focusing on core analog building blocks such as RC circuits, Operational Amplifiers, Bandgap References, Comparators, and more. Your role will also involve architecting and implementing components like Phase-Locked Loops, Voltage/Current Controlled Oscillators, and Charge Pumps. Collaborating closely with layout, digital, and verification teams, you will design and simulate analog blocks in advanced CMOS nodes, ensuring attention to power, area, and performance. Additionally, you will participate in silicon bring-up, validation, and debug processes while documenting design specifications, simulation results, and test plans. To excel in this role, you should hold a Bachelors/Masters/PhD in Electrical Engineering or a related field, demonstrating a strong grasp of analog fundamentals and building blocks. Proficiency in analog simulation tools like Spectre, HSPICE, MATLAB, and Cadence Virtuoso is essential. Experience with mixed-signal verification, CMOS process, and high-speed SerDes systems (e.g., PCIe, USB, Ethernet) will be advantageous. Furthermore, any prior work on PAM4-based Tx/Rx designs, tapeout experience with high-speed analog/mixed-signal IP, or hands-on experience with lab testing and debug tools (e.g., oscilloscope, BERT, VNA) will be highly valued. Join our world-class engineering team to innovate in cutting-edge communication technologies, work on rewarding projects with industry impact, and enjoy competitive compensation, benefits, and career growth opportunities.,

- Good knowledge on different types of Memory architecture. - Hands on experience on SRAM leafcell gds from scratch till top level integration. - Expertise in working on memory layout design for advanced nodes (TSMC : 7nm/5nm/3nm) is must. - Proficient in various physical verification flow debug, like DRC, LVS, DFM, PERC, ERC, EM, IR.. - Proficient in Cadence virtuoso layout editor and caliber Physical verification flow. - Synopsys Custom compiler experience is huge plus. - Understanding and working knowledge of good layout practices in lower process nodes like 7nm and 5nm. - Expertise working on FinFET architecture and challenges such as variability and manufacturability - Expertise in working on address process-dependent effects like electro-migration (EM), IR drop Expertise in optimizing layouts for yield enhancement and manufacturing robustness - Expertise in performing debugging of silicon failures and identify layout-related issues - Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler - Perform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Schematic) rules - Work closely with circuit designers to ensure the layout meets electrical and performance specifications, such as timing, power, and area (PPA) - Provide feedback on circuit designs to improve layout efficiency - Utilize EDA tools for layout design, simulation, and verification, ensuring compliance with foundry-specific PDKs (Process Design Kits) - Automate repetitive tasks and improve workflow efficiency using scripting (e.g., Python, SKILL) - Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations - Preferred resources with valid regional work permit.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Timing models for AMS macros in multiple formats as required. Review path, topology etc. reports Methodology and flow improvements using automation Characterization of Analog Mixed Signal macros Analog Digital interface timing model extraction Correlated timing model data to Hspice simulations for accuracy checks Follow QA checks for consistency and correctness. Skills Must have 3-4yrs hands-on exp in lib characterization for AMS macros. Must have experience with NanoTime Solid understanding of timing fundamentals. Experience in Hspice/Spectre simulators is desirable. Automation using shell/perl/tcl or python is a must. Nice to have Organized and methodical with effective communication skills.

You will be responsible for designing high-speed SerDes Tx and Rx blocks such as Serializer, Output Driver, High-speed clock distribution, Duty cycle correction, CDR, CTLE, VGA, DFE, and DeSerializer. Your role will involve working on Analog Circuits, analog design, Cadence Virtuoso, and Serdes. The ideal candidate should have at least 5 years of industry experience with successful Silicon Tape-outs, specifically with Tier-1 companies. You should be proficient in working independently with minimal guidance. This role requires you to be a High-Speed SerDes Analog Design Engineer who can contribute effectively to the team. The team consists of 1 Tx engineer and 2 Rx engineers specializing in high-speed SerDes analog design.,

Job Description: Role and Responsibilities: Develops and prepares stdcells layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. Checks dimensions, writes specifications, and verifies completed drawings, artwork or digitized plots. Check design layouts and detailed drawings. 3-5 years of experience. Qualification/Requirements: Must have 3-5 of experience in standard cell layout, analog, mixed-signal and custom digital block designs in advanced CMOS process. Should have expertise in multiple standard cell layout library developments. Should be able to perform standard cell layout development and physical verification activities for complex designs as per provided specifications. Should have expertise in layout area and routing optimization, design rules, yield and reliability issues. Good understanding of layout fundamentals i.e., Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc. Should have adequate knowledge of schematics, interface with circuit designer and CAD team. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc., Excellent in problem-solving skills in solving area, power, performance, and physical verification of custom layout. Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Caliber- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques. Should have leadership qualities and able to do multi-tasking as required. Should be able to work in a team environment and able to guide and provide technical support to the fellow team members. Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills. Knowledge of Skill coding and layout automation is a plus. mandatory skillset: stdcells layout || cadence virtuoso || physical verifications checks

Position: IO Design Engineer (SI510FT RM 3539) Job Description: Bachelors/Masters degree in Electronics & Communication/Electrical engineering Working experience (5 to 10 years) in IO Design Hands-on experience in TX and RX design architectures for high speed applications such as DDR4, full custom high speed design such as DDR PHY or SERDES along with timing budget analysis Experience in high-speed design techniques including SERDES , equalization etc. will be added advantage Should have hands-on experience in IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration, HV tolerant and Fail-safe IOs, Crystal oscillator etc. Should have good understanding of ESD phenomenon, familiarity in ESD circuits design and associated ESD guideline. Conversant with tools such as Cadence Virtuoso/Synopsys custom compiler/Hspice/Spectre/Finesim including statistical simulation methodologies Experience in creating EDA model such as Verilog model, Liberty etc. will be of added advantage Should have deep understanding and working knowledge of CMOS process including FINFET technologies such as 5nm and the associated DSM issues Very analytical in nature and able to work in a multi-disciplinary environment Strong theoretical background with a pragmatic approach Good documentation and presentation skills High level of integrity and commitment to quality and timelines Job Category: Others Job Type: Full Time Job Location: Bangalore Experience: 5 - 10 years Notice period: 0-30 days

This position is for an Analog Layout Engineer role who should have the below required knowledge and skills - - Should have good understanding of semiconductor / Analog Layout & Physical verification basics. - Good hands-on Block level scratch Layout work, floor plan, placement, routing - Hands on in 28nm/22nm/ 14nm/ 7nm/ 5nm is desirable - Should understand Analog layout concepts on BGR / LDO/ OPAMP/ ADC/ DAC etc - Hands on Layout exposure to matching techniques like Inter-digitization and common centroid on current mirrors and differential pairs. - Should have good understanding of full custom layout implementation and Layout dependent effects - Good matching and other analog layout related concepts and hands-on implementation from scratch. - Work hands-on critical tasks as and when needed Requirements Requirements Experience: - 5 - 10 years of Analog Layout experience is required - 5nm/7nm/ 10nm/14nm/16nm with Finfet experience is a MUST. - Hands-on expertise in layout techniques such as matching / Shielding / Handling Clocks Etc - Experience in block-level floor-plan, hierarchical layout methodologies / including Power Mesh - Should have performed Physical Verification checks (DRC/LVS/DFM checks) - Experience in analyzing and resolving failure mechanisms EM/IR/ANT/DENSITY/Latch-up - Experience in Tools like Cadence-Virtuoso -XL / Calibre/ PVS/ Custom Compiler/ ICV - Strong scripting skills with Perl/Python/SKILL is a plus Benefits Benefits Whats in it for you - Work on leading edge technologies - An opportunity for career development and growth - Competitive compensation & Exceptional benefits

You are looking for Analog Mixed Signal Designers to join our team and work on designing building blocks for high-speed IPs such as DDR, LPDDR, HBM, UCIe, and PCIe. As a member of our team, your responsibilities will include deriving circuit block level specifications from top-level specifications, designing optimized transistor-level analog and custom digital blocks, conducting Spice simulations to meet detailed specifications, guiding layout design for optimal performance, matching, and power delivery, performing performance characterization of designs in various conditions including reliability checks, and generating/delivering behavioral, timing, and physical models of circuits. You will also be involved in conducting design reviews at different phases of the design process. To be successful in this role, you should have a BE/M-Tech degree in Electrical & Electronics, strong fundamentals in RLC circuits, CMOS devices, digital design building blocks, and prior experience with custom design environments and spice simulators. A collaborative and positive attitude is essential for working effectively in our team. Depending on your experience level, you will be designated as a Design Team Member (0-4 years), a Technical Lead/Mentor (4-7 years), or a Team Lead/Manager (7+ years). Some example designs you may work on include Wireline channel transmitters, receivers, equalization circuits, serializers, deserializers, bandgap references, PLLs, DLLs, phase interpolators, comparators, DACs, and ADCs. Joining our team will provide you with opportunities for growth and learning, including close collaboration with experienced mentors and exposure to advanced process technologies such as 12nm, 7nm, 5nm, 3nm, and 2nm. We offer a fast-paced environment for high-performance individuals who are ready to take on challenges and advance their careers. If you are interested in this fantastic opportunity, please reach out to poojakarve@arf-design.com to learn more.,

Job Description Position: IO Layout Engineer Location: Bangalore, India Duration: Full Time Responsibilities: Custom layout development on block level to Top level I/O layout for GPIO, HSTL, HCSL, VTMON, LVCMOS, DDR, LVDS etc. Knowledge on Latchup, ESD and EM. Exposure to lower nodes N3E, 5nm etc. Skills: LVS/DRC/ERC/Litho Checks/Antenna/ESD-LU/Density etc. Should possess good knowledge on CMOS functionality, CMOS fabrication process, foundries and challenges in latest technology nodes. Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required. Qualifications: Bachelor s degree or higher in Computer Science or a related field. 5 11 years of relevant experience.

The Layout Engineer is responsible for the physical layout of pSemis handset, wireless infrastructure, and broadband integrated circuits. You will be working on a diverse range of product lines that include high-performance sensors for barometric pressure, magnetic, gas, gyro, and accelerometers, multi-throw RF switches, digital step attenuators, mixers, amplifiers, prescalers, DC-DC converters, and PLLs. Your contribution will be crucial to the growth of the product portfolio utilizing pSemis proprietary UltraCMOS process technology. Collaboration with global design teams within pSemi will be an essential aspect of this role, based in our India Design Center in Chennai, India. Your responsibilities will include the development of critical module-level layout and full chip integration support. It will be your responsibility to take complete ownership of assigned layout tasks and ensure on-time delivery of block-level layouts. You will be optimizing layouts based on performance and area, conducting floor planning, and estimating die size. Additionally, verifying and cleaning DRC/LVS/ERC/ANT checks for layouts will be part of your responsibilities, along with understanding and implementing high-quality layouts based on design constraints. To be successful in this role, you should have 0-3 years of related Analog Layout experience and possess knowledge of device physics and process/fabrication technology. Understanding Deep Submicron issues and layout techniques is essential, along with a good grasp of Analog Layout concepts and fundamentals. Knowledge in Cadence Virtuoso environment and PVS for Physical Verification checks is required. Your ability to work in a team-oriented, self-motivated manner across diverse areas and environments will be crucial. A Bachelor's or Master's Degree in Electrical/Electronics Engineering is a prerequisite for this position. The job operates in a professional office environment, utilizing standard office equipment. The physical demands of the job include occasional lifting of office products and supplies up to 20 pounds. Excellent verbal and written communication skills, along with exceptional collaboration and communication skills across distributed teams, are essential attributes for this role.,

Job Description: As an Analog Layout Engineer at SILCOSYS Solutions Pvt. Ltd., you will be responsible for custom circuit layout, physical verification, and RC extraction. We are looking for a talented individual with 3 to 7 years of experience in the field. Proficiency in Cadence Virtuoso and a solid understanding of DRC, LVS, and DFM methodologies are essential for this role. Key Requirements: - Demonstrated expertise in AMS and high-speed layout design - Exposure to components such as Temperature Sensors, SRAM, TCAM, ROM, MRAM, ESD - Track record in advanced technology nodes, with experience in 5nm/3nm considered a plus - Familiarity with Totem EMIR tools and methodologies This position offers a unique opportunity to contribute to cutting-edge semiconductor technologies within a dynamic and innovative work environment. If you meet these qualifications and are ready to take on this exciting challenge, please share your resume with us at info@silcosys.com. We are looking forward to hearing from you!,

As a High-Speed Analog Layout Engineer at our company, you will be responsible for designing and implementing high-speed analog and mixed-signal layouts, focusing on advanced FinFET nodes such as TSMC 2nm, 3nm, 5nm, and 7nm. With your 3+ years of experience in this field, you will play a crucial role in ensuring the success of our projects. Your main responsibilities will include: - Creating custom layouts for high-speed IPs like PLLs, SERDES, clock buffers, and data paths, utilizing your strong hands-on experience in this area. - Utilizing tools such as Cadence Virtuoso, Calibre DRC/LVS, and PEX flows to ensure accurate and efficient layout designs. - Demonstrating a proven track record of delivering clean layouts with successful DRC/LVS/EM/IR sign-offs through multiple tapeouts. - Applying expertise in layout techniques for matching, shielding, parasitic control, and achieving GHz-speed performance. - Having a solid understanding of floorplanning, symmetry, and addressing advanced process challenges. - Holding a Bachelors degree in Electrical or Electronics Engineering to support your technical knowledge. - Demonstrating strong problem-solving skills and a collaborative mindset to work effectively within our team. If you are a detail-oriented and skilled Analog Layout Engineer with a passion for high-speed design and a desire to contribute to cutting-edge projects, we encourage you to apply. Join us in our mission to drive innovation and excellence in the field of analog layout engineering.,

Job Description for Memory Design Location - Bangalore - To work on development of embedded memory compilers ( SRAM, ROM, RF). - Architecture exploration and choosing one based on PPA requirements. - Schematic design and simulations - Margin and characterization simulations - Critical path modeling and optimization - Interface with layout team to define the floor plan and layout guidelines for schematics. Layout review to get optimum design. - Interface with char team to define measurement points needed for timing data generation. - Running robustness checks on the compiler. - Running equivalence verification (ex: ESPCV) - Experience/Skills required : - Experience in design of emJob responsibility: bedded memory compilers - Understanding of memory architectures and the tradeoffs involved. - Sound fundamentals in CMOS basics and custom CMOS Circuit design - Good understanding of bitcell operation and different assist techniques required in advanced nodes. - Familiar with complete memory design ie architecture definition, circuit design, physical design, timing char and- design kit development - Familiarity with EDA tools like cadence Virtuoso, spice simulators . - Knowledge of scripting language like Perl,shell etc - B.E. / B.Tech / M.E. / M.Tech

At Capgemini Engineering, the world leader in engineering services, you will be a part of a global team of engineers, scientists, and architects dedicated to helping the world's most innovative companies reach their full potential. From cutting-edge technologies like autonomous cars to life-saving robots, our digital and software technology experts are always thinking outside the box to provide unique R&D and engineering services across all industries. Join us for a rewarding career filled with endless opportunities where you can truly make a difference, and where no two days are ever the same. As an Analog Layout Designer, you will work independently on block-level analog layout design tasks, encompassing everything from Floorplan to Routing and Verifications. Your role will involve hands-on experience in the critical analog layout design of various blocks such as Temperature sensors, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, and Differential Amplifiers, among others. You should possess a strong proficiency in LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. A solid understanding of concepts such as Matching, EM, ESD, Latch-Up, Shielding, Parasitic, and short channel effects is essential for this role. Familiarity with EDA tools like Cadence VLE/VXL, PVS, Assura, and Calibre DRC/LVS is a must. You should also be able to comprehend how layout decisions impact circuit performance metrics like speed, capacitance, power, and area, and effectively implement design constraints to produce high-quality layouts. Experience with multiple tape outs will be advantageous, along with possessing good interpersonal skills and critical thinking abilities to address technical issues professionally. Excellent communication skills are vital for this role, as you will be responsible for executing layout designs in a timely manner while maintaining high quality standards. Key Skills: - Analog Layout Design - Process or technology experience: TSMC 7nm, 5nm, 10nm, 28nm, 45nm, 40nm - EDA Tools: Cadence Virtuoso Layout Editor (L, XL), Physical verification tools (DRC, LVS, Calibre) In summary, this role at Capgemini Engineering offers a dynamic opportunity to work on challenging projects, collaborate with a diverse team of professionals, and contribute to the advancement of innovative technologies across various industries. If you are someone who thrives in a fast-paced and cutting-edge environment, we welcome you to join us on this exciting journey towards engineering excellence and innovation.,