238 Cadence Virtuoso Jobs - Page 5

Design the various silicon photonics circuits to meet target specifications a nd cater to different applications . Layout of the designed circuits Measure the design on hardware and analyze the results Analyze the impact of device characteristics on circuit-level performance Understand the critical circuit specifications which are important for achieving system-level performance Help with automation and other efficiency improvement projects Other Responsibilities: Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

As an Analog Design Engineer at our company, you will utilize your 6+ years of experience to design and develop high-speed SerDes systems for CHIP to CHIP Communication interfaces. You will be responsible for creating and validating high-performance, low-power analog circuits, focusing on core analog building blocks such as RC circuits, Operational Amplifiers, Bandgap References, Comparators, and more. Your role will also involve architecting and implementing components like Phase-Locked Loops, Voltage/Current Controlled Oscillators, and Charge Pumps. Collaborating closely with layout, digital, and verification teams, you will design and simulate analog blocks in advanced CMOS nodes, ensurin...

- Good knowledge on different types of Memory architecture. - Hands on experience on SRAM leafcell gds from scratch till top level integration. - Expertise in working on memory layout design for advanced nodes (TSMC : 7nm/5nm/3nm) is must. - Proficient in various physical verification flow debug, like DRC, LVS, DFM, PERC, ERC, EM, IR.. - Proficient in Cadence virtuoso layout editor and caliber Physical verification flow. - Synopsys Custom compiler experience is huge plus. - Understanding and working knowledge of good layout practices in lower process nodes like 7nm and 5nm. - Expertise working on FinFET architecture and challenges such as variability and manufacturability - Expertise in work...

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Timing models for AMS macros in multiple f...

You will be responsible for designing high-speed SerDes Tx and Rx blocks such as Serializer, Output Driver, High-speed clock distribution, Duty cycle correction, CDR, CTLE, VGA, DFE, and DeSerializer. Your role will involve working on Analog Circuits, analog design, Cadence Virtuoso, and Serdes. The ideal candidate should have at least 5 years of industry experience with successful Silicon Tape-outs, specifically with Tier-1 companies. You should be proficient in working independently with minimal guidance. This role requires you to be a High-Speed SerDes Analog Design Engineer who can contribute effectively to the team. The team consists of 1 Tx engineer and 2 Rx engineers specializing in h...

Job Description: Role and Responsibilities: Develops and prepares stdcells layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. Checks dimensions, writes specifications, and verifies completed drawings, artwork or digitized plots. Check design layouts and detailed drawings. 3-5 years of experience. Qualification/Requirements: Must have 3-5 of experience in standard cell layout, analog, mixed-signal and custom digital block designs in advanced CMOS process. Should have expertise in multiple standard cell layout library developments. Should be abl...

Position: IO Design Engineer (SI510FT RM 3539) Job Description: Bachelors/Masters degree in Electronics & Communication/Electrical engineering Working experience (5 to 10 years) in IO Design Hands-on experience in TX and RX design architectures for high speed applications such as DDR4, full custom high speed design such as DDR PHY or SERDES along with timing budget analysis Experience in high-speed design techniques including SERDES , equalization etc. will be added advantage Should have hands-on experience in IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration, HV tolerant and Fail-safe IOs, Crystal oscillator etc. Should have good understanding of ESD phenomenon, familiarity in ESD circu...

This position is for an Analog Layout Engineer role who should have the below required knowledge and skills - - Should have good understanding of semiconductor / Analog Layout & Physical verification basics. - Good hands-on Block level scratch Layout work, floor plan, placement, routing - Hands on in 28nm/22nm/ 14nm/ 7nm/ 5nm is desirable - Should understand Analog layout concepts on BGR / LDO/ OPAMP/ ADC/ DAC etc - Hands on Layout exposure to matching techniques like Inter-digitization and common centroid on current mirrors and differential pairs. - Should have good understanding of full custom layout implementation and Layout dependent effects - Good matching and other analog layout relate...

You are looking for Analog Mixed Signal Designers to join our team and work on designing building blocks for high-speed IPs such as DDR, LPDDR, HBM, UCIe, and PCIe. As a member of our team, your responsibilities will include deriving circuit block level specifications from top-level specifications, designing optimized transistor-level analog and custom digital blocks, conducting Spice simulations to meet detailed specifications, guiding layout design for optimal performance, matching, and power delivery, performing performance characterization of designs in various conditions including reliability checks, and generating/delivering behavioral, timing, and physical models of circuits. You will...

Job Description Position: IO Layout Engineer Location: Bangalore, India Duration: Full Time Responsibilities: Custom layout development on block level to Top level I/O layout for GPIO, HSTL, HCSL, VTMON, LVCMOS, DDR, LVDS etc. Knowledge on Latchup, ESD and EM. Exposure to lower nodes N3E, 5nm etc. Skills: LVS/DRC/ERC/Litho Checks/Antenna/ESD-LU/Density etc. Should possess good knowledge on CMOS functionality, CMOS fabrication process, foundries and challenges in latest technology nodes. Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required. Qualifications:...

The Layout Engineer is responsible for the physical layout of pSemis handset, wireless infrastructure, and broadband integrated circuits. You will be working on a diverse range of product lines that include high-performance sensors for barometric pressure, magnetic, gas, gyro, and accelerometers, multi-throw RF switches, digital step attenuators, mixers, amplifiers, prescalers, DC-DC converters, and PLLs. Your contribution will be crucial to the growth of the product portfolio utilizing pSemis proprietary UltraCMOS process technology. Collaboration with global design teams within pSemi will be an essential aspect of this role, based in our India Design Center in Chennai, India. Your responsi...

Job Description: As an Analog Layout Engineer at SILCOSYS Solutions Pvt. Ltd., you will be responsible for custom circuit layout, physical verification, and RC extraction. We are looking for a talented individual with 3 to 7 years of experience in the field. Proficiency in Cadence Virtuoso and a solid understanding of DRC, LVS, and DFM methodologies are essential for this role. Key Requirements: - Demonstrated expertise in AMS and high-speed layout design - Exposure to components such as Temperature Sensors, SRAM, TCAM, ROM, MRAM, ESD - Track record in advanced technology nodes, with experience in 5nm/3nm considered a plus - Familiarity with Totem EMIR tools and methodologies This position o...

As a High-Speed Analog Layout Engineer at our company, you will be responsible for designing and implementing high-speed analog and mixed-signal layouts, focusing on advanced FinFET nodes such as TSMC 2nm, 3nm, 5nm, and 7nm. With your 3+ years of experience in this field, you will play a crucial role in ensuring the success of our projects. Your main responsibilities will include: - Creating custom layouts for high-speed IPs like PLLs, SERDES, clock buffers, and data paths, utilizing your strong hands-on experience in this area. - Utilizing tools such as Cadence Virtuoso, Calibre DRC/LVS, and PEX flows to ensure accurate and efficient layout designs. - Demonstrating a proven track record of ...

Job Description for Memory Design Location - Bangalore - To work on development of embedded memory compilers ( SRAM, ROM, RF). - Architecture exploration and choosing one based on PPA requirements. - Schematic design and simulations - Margin and characterization simulations - Critical path modeling and optimization - Interface with layout team to define the floor plan and layout guidelines for schematics. Layout review to get optimum design. - Interface with char team to define measurement points needed for timing data generation. - Running robustness checks on the compiler. - Running equivalence verification (ex: ESPCV) - Experience/Skills required : - Experience in design of emJob responsi...

At Capgemini Engineering, the world leader in engineering services, you will be a part of a global team of engineers, scientists, and architects dedicated to helping the world's most innovative companies reach their full potential. From cutting-edge technologies like autonomous cars to life-saving robots, our digital and software technology experts are always thinking outside the box to provide unique R&D and engineering services across all industries. Join us for a rewarding career filled with endless opportunities where you can truly make a difference, and where no two days are ever the same. As an Analog Layout Designer, you will work independently on block-level analog layout design task...

As an Analog Mixed-Signal IC Layout Lead Engineer, you will play a critical role in designing advanced node Bi-CMOS / CMOS products You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout You will work to build state-of-the art high speed circuits minimizing layout parasitics, while applying techniques to reduce skew and crosstalk Meeting EM/IR compliance requirements is essential You will ensure strict adherence to DRC, LVS, ANT, and density rules Additionally, awareness of ESD and latch-up design practices is expected to ensure robust and reliable layout implementations You will apply a solid foundation...

The Allegro team is united by a clear purpose advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business from breakthrough product development and customer success to how we show up for each other and the communities we serve. The Opportunity As a Senior Layout Engineer at Allegro MicroSystems, you will be a key contributor to our integrated circuit development team, responsible for the physical implementation of complex analog and mixed-signal designs. You will work closely with design engineers to translate schematics into high-quality, ...

You are an AMS Verification engineer with a B.Tech/M.Tech degree and 5-11 years of industry experience in analog/mixed signal behavioral modeling. Your responsibilities include full chip verification at various levels using SV RNM or Custom UDNs. You should have a good understanding of analog design concepts and mixed signal design architectures, working with products integrating various Analog/Mixed-Signal building blocks. Your experience should cover verification plan development, UVM verification environment development/debug, and verification of complex mixed signal products at different levels. Familiarity with Analog/Mixed-Signal/RF design architectures, debug experience with schematic...

Key Responsibilities: Min 4 Years of overall experience in ASIC Verification Should have worked on AMS Verification for minimum of 2 years Develop and execute verification plans for AMS designs. Create testbenches and run simulations using tools like Cadence Virtuoso, Spectre, or AMS Designer. Verify mixed-signal blocks (e.g., ADCs, DACs, PLLs) and ensure proper analog-digital interaction. Debug and resolve design issues in collaboration with design teams. Document verification results and ensure compliance with design specifications.

You will be responsible for developing block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Your role will involve applying an understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. You will conduct analyses, tests, and verify designs using different tools and techniques to identify and troubleshoot issues. It is essential to stay abreast of new verification methods and work collaboratively with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. To qualify for this posi...

Job Description: Role and Responsibilities: Develops and prepares stdcells layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. Checks dimensions, writes specifications, and verifies completed drawings, artwork or digitized plots. Check design layouts and detailed drawings. 3-5 years of experience. Qualification/Requirements: Must have 3-5 of experience in standard cell layout, analog, mixed-signal and custom digital block designs in advanced CMOS process. Should have expertise in multiple standard cell layout library developments. Should be abl...

We are looking for a highly skilled and experienced Lead Engineer to join our team and contribute to the verification of mixes Signal. The ideal candidate should have a deep understanding of the Cadence, AMS along with expertise in system-level development and debugging What You Will Do Proficient in Verilog-AMS, System Verilog, and UVM methodologies Experience with Cadence Spectre or similar AMS simulation tools Strong understanding of analog circuit design principles (op-amps, transistors, etc.) What You Need to Be Successful Proficient in Verilog-AMS, System Verilog, and UVM methodologies Bonus Points if You Have Experience with Cadence Spectre or similar AMS simulation tools Strong under...

Cadence is looking for Principal Design Engineer to join our dynamic team and embark on a rewarding career journey Health and Safety Compliance: Ensure that construction projects comply with health and safety regulations, guidelines, and industry standards Risk Assessment: Identify and assess potential health and safety risks associated with the project's design, construction methods, and materials Design Coordination: Collaborate with architects, engineers, project managers, and other stakeholders to integrate health and safety principles into the project's design and planning Hazard Identification: Identify and document potential hazards related to the project, including those arising from...

Collaborate withcross-functional teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits. * Create and optimize layout designs usingindustry-standard EDA tools. * Perform physical verification and design rule checks to ensure design integrity andmanufacturability. * Participate in design reviews and provide feedback to improve design quality. * Work closely with circuit designers to understand design specifications and constraints. * Contribute to the development and enhancement of layout design methodologies and best practices. * Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: * Ensur...

General Summary Qualcomm is a company of inventors revolutionizing the CPU market in an age of innovation. As an SRAM Mask Layout Designer , you will be part of a high-performance CPU team, collaborating with top engineering talent to deliver designs that push the limits of performance, energy efficiency, and scalability. This role offers a dynamic and creative environment, with opportunities to impact next-generation products used around the world. In this role, you will develop block or macro-level layouts and floorplans for high-performance custom memories, ensuring alignment with design schematics and project requirements. You will apply industry best practices, work with cutting-edge te...