238 Cadence Virtuoso Jobs - Page 6

Circuit design and verification of the CMOS I2C IO and GPIO libraries. Develop I2C IO and GPIO (operation up to 200MHz) architecture to meet the specifications. Develop 3.3V architecture using 1.8V MOS to meet the design & reliability specifications. Optimisation of the design, verification of the functionality, performance, power using Cadence Virtuoso circuit design suite (ADE-XL) Working knowledge of the layout to guide the layout engineers on the implementation of the critical structures for matching, shielding and routing requirements. Strong problem-solving skills, results orientation, attention to detail, and effective communication skills are the key for this position. Experience: 5 ...

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: Are you an Analog Design Engineer with hands-on experience designing components like Bandgap references, High-Speed IO circuits, Low Dropout Regulators (LDOs), and Phase-Locked Loops (PLLs)? If you have a minimum of 2 years in the semiconductor industry, this role offers exciting challenges and opportunities to contribute to groundbreaking projects. Responsibilities: 1. Collaborat...

Skills/Experience: Hands on debugging skills in different physical verification checks like LVS, DRC, ERC, PERC, Antenna, ESD and DFM using Calibre, ICV and Pegasus PV tools Knowledge of basic device physics and PV fixing using various PnR tools like Innovus/ICC2 is required. Working experience in cutting edge technologies such as 3/4/5nm and 7nm process nodes is desired Experience (years) : 4+ Year Education Qualification: B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

About The Role About The Role : 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Ma...

Skills/Experience: Experience with high speed circuits like serializer, deserializer, Rx, Tx,PLL, ADC etc Strong VLSI Fundamentals, Circuits design & Digital Systems deep submicron CMOS design based on FinFETs technology. Solid fundamentals in circuit analysis and Clock/Memory Circuit design. Experience (years) : 2+ Year Education Qualification: BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

About the Role : We are seeking a talented Implementation Engineer to join our dynamic team. The successful candidate will be responsible for leading and executing Synthesis and STA for complex AI SOC with multi-mode and multi power domain design, ensuring the quality and reliability of our products. This is what you are responsible for : - Synthesis and STA (static timing analysis). - Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL. - Professional experience with ECO implementation, both functional and timing closure. - Experience with multi-clock, multi-power domain designs and multi-mode timing constraints. - Familiarity with D...

Perform full-custom analog layout design for blocks such as PLLs, ADCs, DACs, SerDes, High-Speed IOs, Power Management Circuits, and Standard Cells. Work on deep sub-micron process nodes (TSMC 3nm to 16nm) ensuring compliance with foundry rules. Execute layout of matched devices, current mirrors, differential pairs, and high-precision analog/mixed-signal circuits. Perform floorplanning, placement, routing, parasitic extraction, and LVS/DRC verification . Collaborate with circuit designers to ensure performance, reliability, and yield requirements are met. Work on layout optimization for area, performance, and manufacturability (DFM) . Support design reviews and contribute to timely tape-outs...

Skills/Experience: Independent layout development of High Speed blocks like SerDes, Rx, Tx, , PLL, ADC, LDO, Bandgap etc Strong debug skills and good communication Education Qualification: BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

We are looking for a highly skilled EDA Engineer with expertise in Cadence Virtuoso environments and a profound knowledge of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and automation of schematic/layout tools. In this role, you will collaborate closely with AI/EDA development teams to establish seamless design flows and robust automation for our AI-powered analog design platform. Your responsibilities will include developing, maintaining, and optimizing analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. You will also be tasked with creating, modifying, and optimizing SKILL scripts for automating layout, schematic, verification, and design ...

We are looking for a highly skilled EDA Engineer with expertise in Cadence Virtuoso environments and a strong understanding of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and schematic/layout tool automation. In this role, you will collaborate closely with AI/EDA development teams to establish seamless design flows and efficient automation for our AI-powered analog design platform. Your responsibilities will include developing, maintaining, and optimizing analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. You will be tasked with creating, modifying, and optimizing SKILL scripts for automating layout, schematic, verification, and design envi...

As an Analog Layout Engineer with 3-5 years of experience in advanced semiconductor technologies (5nm and below), you will be responsible for executing full custom layout designs for high-speed analog and mixed-signal blocks. Your expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre will be crucial in collaborating closely with circuit design teams to interpret and implement layout specifications. Your key responsibilities will include performing layout verification, ensuring compliance with foundry design rules and layout best practices, addressing issues related to electromigration, IR drop (EMIR), and layout-dependent effects, as well...

You are a Senior Manager responsible for leading the Reference Design team for GlobalFoundries" Fotonix platform, a cutting-edge Silicon Photonics technology. Your role involves driving innovation, creating high-quality reference designs, and ensuring the success and growth of the platform. You will collaborate with stakeholders, manage project timelines, and provide technical leadership to the team. Key Responsibilities - Lead and manage a team of designers in developing Silicon Photonics Reference Designs. - Collaborate with cross-functional teams to define project requirements, timelines, and deliverables. - Drive innovation and development of new silicon photonics technologies and soluti...

Qualcomm India Private Limited is seeking a Layout Engineer to develop block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. In this role, you will utilize your understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. You will conduct analyses, tests, and verify designs using various tools and techniques to identify and troubleshoot issues, while staying updated on new verification methods. Collaborating with multiple internal and external stakeholders, you will align on projects, provide updates, and resolve issues. The id...

As an EDA Engineer, you will be responsible for developing, maintaining, and optimizing analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. Your role will involve creating, modifying, and optimizing SKILL scripts for automation of layout, schematic, verification, and design environment tasks. You will manage Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries. Working extensively with the OpenAccess (OA) database API, using C++, Python, and Tcl, will be a key aspect of your responsibilities. You will be involved in reading, writing, and manipulating design data, including schematic, layout, connectivity, and...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and meticulous engineer with a deep commitment to excellence in analog and high-speed mixed signal layout design. With a minimum of 2 years of hands-on experience in advanced technology nodes (5nm and below), you thrive in dynamic, collaborative environments w...

The ideal candidate for this position should have 1-2 years of experience in AMS design verification. You will be responsible for developing Verilog/VerilogA/VerilogAMS models for signal and power management modules to support top-level verification. Experience in full chip DV would be an added advantage. You will contribute to the development of the Full-Chip AMS-DV plan and own significant pieces of this verification process. It is essential to have the ability to drive best practices in the field of AMS-DV. In this role, you will work independently to identify bugs and resolve them formally with cross-functional teams. An understanding of analog power IPs will be beneficial as it can help...

Location: Bangalore, India Experience: 2+ Years Notice Period: Immediate to 1 Month Preferred About Genisup India Private Limited Genisup India Private Limited is a leading semiconductor and system design company headquartered in Bangalore. We specialize in Foundational IP Fabless Design, Semiconductor & Product Engineering, and IoT solutions. Our client portfolio includes top-tier companies such as NXP, Qualcomm, and Analog Devices. We are committed to delivering innovative solutions and technical excellence in the semiconductor industry. Role Overview We are looking for an experienced Senior Analog Layout Design Engineer with strong expertise in standard cell layout design to join our team...

Analog Design Engineer with exposure to ADC/DAC/ PLL designs . Job Description In your new role you will: Be a part of the SRSS team in India, where you will: Own and contribute towards designing of Analog I/P . Design and test analog electronic circuits, including sensor interfaces, data converters, multiplexers, active and passive filters, and power distribution systems. Simulate analog or mixed-signal circuits to ensure that performance, noise, timing, and power requirements are satisfied including worst-case and/or statistical design verification and de-rating analysis. Perform the block level and transistor level layout design and optimization of sensor array readout circuits using CAD ...

As an AMS Verification Engineer, you will be responsible for working on Analog Mixed-Signal (AMS) Verification for SoCs, subsystems, and IPs. Your role will involve hands-on experience with AMS simulation environments using tools such as Cadence, Synopsys, or Mentor. It is essential to have a solid understanding of analog and mixed-signal circuits, including comparators, op-amps, switched-cap circuits, ADCs/DACs, current mirrors, charge pumps, and regulators. Your expertise in Verilog, Verilog-A, Verilog-AMS, and Verilog-D for behavioral modeling will be crucial for block-level and chip-level AMS verification. This includes top-level testbench development, self-checking testbenches, and regr...

As an Analog Layout Engineer at AISemiCon, you will play a critical role in the design and development of high-performance analog and mixed-signal integrated circuits (ICs). Your main responsibility will be to create layout designs for analog blocks and ensure their adherence to design rules, specifications, and performance targets. You will collaborate closely with cross-functional teams, including circuit designers, verification engineers, and process engineers, to achieve optimal layout implementation. We are seeking individuals with a strong passion for analog layout, deep expertise in IC design, and a keen eye for detail. The key responsibilities for this role include, but are not limit...

The detailed JD is given below Requirements : - B.Tech/M.Tech with 5+ Years of industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification (AMS and DMS DV) using SV RNM or Custom UDN s. Good understanding of analog design concepts and mixed signal design architectures. Exposure to products that integrate a wide variety of Analog/Mixed-Signal building blocks such as Power Management, PLL/Synthesizers, ADC, DAC, bandgap references, oscillators/clocking circuits, Phase Interpolators, SerDes etc. and related digital control and signal processing. Demonstrated experience of verification plan development, UVM verification environment d...

You will be responsible for Analog Layout tasks with a focus on AMS/IO Memory, Full-custom circuit layout/verification, and RC extraction. Your role will involve working with lower nodes from TSMC, specifically focusing on ESD Blocks. As an Experienced Layout Engineer at ACL Digital, you should hold a Bachelor's or Master's Degree with a minimum of 4 years of Analog Layout experience. In this position, you will need to demonstrate leadership skills acquired over at least 3 years, including hiring, nurturing talent, leading project execution, and managing clients and stakeholders effectively. Your excellent communication skills will be crucial, along with a hands-on approach to your work. An ...

As an Analog Layout Engineer at ARF Design Pvt Ltd, you will be responsible for designing and developing analog layout IP blocks and integrating them into full-chip designs. Your expertise in lower technology nodes, physical layout techniques, and verification processes will be crucial for success in this role. You will collaborate with circuit design teams to optimize layout quality and performance, ensuring that layouts meet design matching and parasitic constraints. Working with advanced nodes like 7nm, 16nm, and 28nm, you will play a key role in advancing the company's cutting-edge projects. Key Responsibilities: - Design and develop analog layout IP blocks and full-chip integration - Pe...

B.Tech/M.Tech with 5+ Years of industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification (AMS and DMS DV) using SV RNM or Custom UDN’s

We are seeking a highly skilled Senior Analog Design Engineer with 6+ years of experience in designing, simulating, and validating analog and mixed-signal circuits. The ideal candidate should have hands-on expertise across the full custom design flow, from specification to silicon validation. Key Responsibilities: Design and develop analog/mixed-signal IPs such as ADCs, DACs, LDOs, Bandgaps, PLLs, Op-Amps, etc. Perform schematic entry, simulations (pre-layout/post-layout), and layout supervision. Drive transistor-level design using industry-standard tools (Cadence/Synopsys). Lead block-level design reviews, documentation, and verification. Collaborate with layout, digital, and validation tea...