84 Cadence Virtuoso Jobs - Page 4

About The Role Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. ? Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from design, selection of materials, low level system software development and verification. Needs by displaying complete understanding of product vision and business requirements Develop architectural designs for the new and existing products Part Implementation of derived solution Debug and Solve critical problems during implementation Evangelize Architecture to the Project and Customer teams to achieve the final solution. Constant analysis and monitoring of the product solution Continuously improve and simplify the design, optimize cost and performance Understand market- driven business needs and objectives; technology trends and requirements to define architecture requirements and strategy Create a product-wide architectural design that ensures systems are scalable, reliable, and compatible with different deployment options Develop theme-based Proof of Concepts (POCs) in order to demonstrate the feasibility of the product idea and realise it as a viable one Analyse, propose and implement the core technology strategy for product development Conduct impact analyses of changes and new requirements on the product development effort ? Provide solutioning of RFPs received from clients and ensure overall product design assurance as per business needs Collaborate with sales, development, consulting teams to reconcile solutions to architecture Analyse technology environment, enterprise specifics, client requirements to set a product solution design framework/ architecture Provide technical leadership to the design, development and implementation of custom solutions through thoughtful use of modern technology Define and understand current state product features and identify improvements, options & tradeoffs to define target state solutions Clearly articulate, document and sell architectural targets, recommendations and reusable patterns and accordingly propose investment roadmaps Validate the solution/ prototype from technology, cost structure and customer differentiation point of view Identify problem areas and perform root cause analysis of architectural design and solutions and provide relevant solutions to the problem Tracks industry and application trends and relates these to planning current and future IT needs Provides technical and strategic input during the product deployment and deployment Support Delivery team during the product deployment process and resolve complex issues Collaborate with delivery team to develop a product validation and performance testing plan as per the business requirements and specifications. Identifies implementation risks and potential impacts. Maintain product roadmap and provide timely inputs for product upgrades as per the market needs Competency Building and Branding Ensure completion of necessary trainings and certifications Develop Proof of Concepts (POCs), case studies, demos etc. for new growth areas based on market and customer research Develop and present a point of view of Wipro on product design and architect by writing white papers, blogs etc. Attain market referencsability and recognition through highest analyst rankings, client testimonials and partner credits Be the voice of Wipro??s Thought Leadership by speaking in forums (internal and external) Mentor developers, designers and Junior architects for their further career development and enhancement Contribute to the architecture practice by conducting selection interviews etc ? Deliver No.Performance ParameterMeasure1.Product design, engineering and implementationCSAT, quality of design/ architecture, FTR, delivery as per cost, quality and timeline, POC review and standards2.Capability development% trainings and certifications completed, mentor technical teams, Thought leadership content developed (white papers, Wipro PoVs) ? Mandatory Skills: Analog Layout. Experience8-10 Years. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

locationsIndia, Bangaloreposted onPosted Today job requisition idJR0275251 Job Details: About The Role : Intel is at the forefront of the wireless communication industry, offering cutting-edge products that set the standard for performance and innovation. We are seeking a highly skilled SerDes PHY System Engineer to join our team. In this pivotal role, you will be responsible for the design and development of physical layer components for high-speed SerDes systems, ensuring their performance and reliability. Key Responsibilities: SerDes PHY DesignLead the design and development of the physical layer for SerDes systems, including transmitter and receiver architectures, equalization techniques, and signal integrity. Simulation and ValidationConduct comprehensive simulations using MATLAB and Python, along with lab testing, to validate the performance and compliance of the SerDes PHY, optimizing it for high-speed data transmission. Calibration TechniquesDevelop and implement calibration methods to enhance the performance of the SerDes PHY, ensuring high-quality data transmission. CollaborationWork closely with cross-functional teams, including digital design, hardware, and software, to ensure seamless integration of the PHY layer into the overall SerDes system. DocumentationMaintain detailed and up-to-date documentation of design specifications, test plans, and results. Problem-SolvingAddress and resolve complex technical issues related to the SerDes PHY, ensuring optimal performance. Quality AssuranceImplement quality control measures and best practices to ensure the reliability and robustness of the SerDes PHY. Qualifications: Bachelor's degree in Electrical Engineering; a Master's degree in a relevant field is preferred. Minimum of 5 years of experience in wired or wireless communication systems. Proven experience and enthusiasm for lab work, collaboration, and solution development. Prior experience in DDR/PCI/GDDR7/UCI will be added advantage. Proficiency in scripting and programming languages such as C, C#, MATLAB, and Python. Experience in silicon development and SerDes technologies is advantageous. Strong problem-solving abilities and analytical skills. Self-motivated and capable of executing tasks in uncertain environments. Demonstrated leadership skills and ability to drive initiatives in a matrix organization. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Role: Execute Layout Design of SRAM/CAM/RF compiler memories in N3P, N2P technology. Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Knowledge of EM/IR requirements. Compiler level integration, verification of Compiler/Custom memories. Should possess good knowledge on CMOS fabrication process, foundries and challenges in latest technology nodes. Skills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required. Behavioural Traits: Ability to follow established procedures and work in a distributed team environment. Work independently to deliver high quality results on time.

Job TitleHR-food/spices Job Code HREQ2017/12/66 --> Job Location Kolkata Experience 3-5years Gender Male/ Female Job Details Urgently required an HR with experience of 3-4years in the field of food & spices Salary Per Year 2-4lpa Apply Now

The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary As a product Validation engineer you will be part of Cadence Virtuoso Product validation team and will be contributing to the Development & executing test plans for Virtuoso features. You will be working closely with the Virtuoso Product Engineering and Development teams. Knowledge of analog design flow and analog design/verification tools will be beneficial. Job Responsibilities As a Lead Product Validation (PV) engineer, you will be responsible for quality engineering for Cadence Virtuoso product line including: Working with Product engineering (PE) and development teams to understand customer requirements Developing & executing test plans based on the requirements Execute on test plans and perform unit, integration, solutions level validation Ensure product quality by providing inputs to improve functionality, , usability, reliability, performance and stability. Maintaining regression tests for regular test cycles and reporting failures in bug tracking system Working with PE and Field teams to integrate customer test cases as part of regression suite Experience and Technical Skills required 4+ to 8 years of experience in the EDA or VLSI industry Good understanding of analog design flow and design tools Knowledge of designs in advanced technology nodes is desirable. . Familiarity with Shell & PERL scripting, SKILL know-how will be a big plus Strong problem-solving skills and Effective communication & interpersonal skills Team player with capability/drive to work in a multi geo cross-functional environment Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronics or equivalent Behavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity

Design and development of analog and mixed-signal IC blocks such as amplifiers, ADCs/DACs, voltage regulators, PLLs, bandgap references, and filters. Perform transistor-level circuit design, simulations (pre- and post-layout), using cadence Virtuoso.

Areas of Responsibility Circuit design and verification of the CMOS I2C IO and GPIO libraries. Develop I2C IO and GPIO (operation up to 200MHz) architecture to meet the specifications. Develop 3.3V architecture using 1.8V MOS to meet the design & reliability specifications. Optimisation of the design, verification of the functionality, performance, power using Cadence Virtuoso circuit design suite (ADE-XL) Working knowledge of the layout to guide the layout engineers on the implementation of the critical structures for matching, shielding and routing requirements. Strong problem-solving skills, results orientation, attention to detail, and effective communication skills are the key for this position. position Requirement: Experience: 5 10 years of experience in the areas of analog and IO circuit design, with good experience in designing Overvoltage, Failsafe & I2C compatible IO interfaces. Desired Skills : Strong hands on experience in CMOS IO design, programmable driver Impedance control, Impedance matching of transmission line. Solid hands on experience working with Cadence Virtuoso circuit design suite (ADE-XL) Good technical knowledge of power-performance trade-offs. Strong understanding of the impact of device parameter variation on design performance. Basic understanding of IO library views like .lib, IBIS generation Basic understanding of ESD & LU concepts. Independent ownership of circuit blocks. Clear communication and diligent documentation of the work. Good team player in a multi-site work environment Analog Circuit Design

RF, Analog & Mixed Signal level designs for various applications using CMOS, BiCMOS and GaAs processes on industry standard EDA tools.Must be an efficient user of Cadence (Virtuoso)/Agilent ADS tools. Good knowledge of IC design,simulations & Layout

Role & responsibilities 1.Job description - Analog Layout: Exciting Opportunity for Analog Layout Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm Expertise on complete PNR flow CTS,routing, Timing Closure. Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Experience in AMS IP integration in full chip according to the guidelines demanded by the Full Chip needs Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout Qualifications:- BTECH/MTECH Location: Bangalore & Noida Experience:- The Engineers with 5 to 10 years of Experience 2.Job description - Physical Verification- Exciting Opportunity for Physical Verification Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Design Rule Checking (DRC): Run DRC checks using industry-standard tools to identify violations of manufacturing design rules. Collaborate with layout designers to resolve DRC issues. Layout vs. Schematic (LVS) Verification: Perform LVS checks to ensure that the physical layout accurately matches the schematic and that there are no electrical connectivity discrepancies. Electrical Rule Checking (ERC): Verify that the layout adheres to electrical constraints and requirements, such as voltage and current limitations, ensuring that the IC functions as intended. Design for Manufacturing (DFM): Collaborate with design and manufacturing teams to optimize the layout for the semiconductor fabrication process. Address lithography and process variation concerns. Process Technology Calibration: Calibrate layout extraction tools and parameters to match the specific process technology used for fabrication. Resolution Enhancement Techniques (RET): Implement RET techniques to improve the printability of layout patterns during the photolithography process. Fill Insertion: Insert fill cells into the layout to improve planarity and reduce manufacturing-related issues, such as wafer warping and stress. Multi-Patterning and Advanced Nodes: Deal with challenges specific to advanced process nodes, including multi-patterning, coloring, and metal stack variations. Hotspot Analysis: Identify and address potential hotspot areas that may lead to manufacturing defects or yield issues. Post-Processing Simulation: Perform post-processing simulations to verify that the layout is compatible with the manufacturing process and does not introduce unwanted parasitics. Process Integration Checks: Collaborate with process integration teams to ensure the smooth integration of the design with the semiconductor fabrication process. Documentation: Maintain detailed documentation of verification processes, methodologies, and results. Qualifications:- BTECH/MTECH Experience:- The Engineers with 5 to 10 years of Experience Location:- Bangalore/ Noida