241 Cadence Virtuoso Jobs - Page 4

We are looking for a skilled SAP DRC Engineer with 7 to 12 years of experience. The ideal candidate will have expertise in the SAP DRC module and BTP of SAP, SD, FI, E-Doc Cockpit, and project management skills. This position is available in PAN India, including Bangalore, Hyderabad, Chennai, Noida, Pune, and Gurgaon. Roles and Responsibility Design and implement SAP DRC solutions to meet business requirements. Collaborate with cross-functional teams to ensure seamless integration of SAP DRC with other modules. Develop and maintain documentation for SAP DRC projects. Provide training and support to end-users on SAP DRC functionality. Troubleshoot and resolve technical issues related to SAP D...

AMS Verification Job Location: Bangalore Job Description: 4-6 yrs of exp in mixed-signal verification of chip Experience with mixed signal / co-simulation (analog, digital) verification methodologies Experience writing verification plans, creating test benches and automating regression test suites, preparing and presenting detailed verification reviews Experience developing behavioral models for analog IPs in WREAL, Verilog-AMS Understand and debug digital RTL and analog schematics Working knowledge of state-of-the-art EDA tools: Cadence Virtuoso, Cadence Incisiv/Xcelium, Cadence Vmanager Strong background in verification languages and methodologies (e.g. Verilog, SystemVerilog, UVM, SVA). E...

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualificatio...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Roles and Responsibilities Design analog layouts using Cadence Virtuoso for FinFET devices with PLL and SerDes interfaces. Perform DRC, LVS, and mixed signal simulations to ensure design integrity. Collaborate with cross-functional teams to resolve design issues and optimize designs. Develop expertise in Caliber technology for high-speed I/O applications. Ensure compliance with industry standards and company guidelines.

Responsibilities Perform full-custom analog layout for advanced nodes (28nm and below ,TSMC,FinFET/CMOS technologies) .Work on block-level and top-level layouts of circuits such as: PLLs, ADCs, DACs, LDOs, Bandgaps, High-speed IOs, SerDes, RF blocks

Role Overview: As a skilled professional in Standard Cell Library Development, you will leverage your hands-on experience and expertise to contribute effectively to the characterization processes. Your solid understanding of CMOS and FinFET technologies will be key in ensuring the success of the projects at hand. Exposure to Verilog modeling will be advantageous in this role, although it is not mandatory. Your role will require strong debugging and problem-solving skills specifically related to cell design, SPICE simulation, and characterization. This will enable you to address challenges effectively and ensure the quality of the developed libraries. Key Responsibilities: - Contribute effect...

You will be responsible for the further development of concepts and methods for the EDA design environments with focus on analog / mixed signal CAD flows. Expert level proficiency in one or more of the programming/scripting languages SKILL, Python, Unix, Perl and TCL. Expertise in Virtuoso suite of tools and Analog Design environment (finesim/PrimeSim) Solid understanding of Calibre Physical Verification decks(SVRF) and ICV LVS decks with hands-n experience in integrating various PV flows in CAD environment. Solid experience in Layout Automation and Utilities development in Cadence SKILL/SKILL++. Development and validation of PV tools and flows like parasitic extraction, EMIR drop and substr...

General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, El...

We are seeking a highly skilled Senior Analog Design Engineer with 6+ years of experience in designing, simulating, and validating analog and mixed-signal circuits. The ideal candidate should have hands-on expertise across the full custom design flow, from specification to silicon validation. Key Responsibilities: Design and develop analog/mixed-signal IPs such as ADCs, DACs, LDOs, Bandgaps, PLLs, Op-Amps, etc. Perform schematic entry, simulations (pre-layout/post-layout), and layout supervision. Drive transistor-level design using industry-standard tools (Cadence/Synopsys). Lead block-level design reviews, documentation, and verification. Collaborate with layout, digital, and validation tea...

Description: Description: Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Excellent problem-solving skills in physical verification of custom layout. • Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. • Ability to guide junior team-members in their execution of Sub block-level layouts & r...

Role Overview: The member joining this position will work at an experienced (band/level) and be part of a team of R&D. This team-focused role will involve collaboration and support within a dynamic work environment. Travel may be required to a few regions for discussions with stakeholder/vendors as well as to maintain strong customer relationships. The member will work with various stakeholders, including teams from Digital Business Leaders, Customer Support Division and Branch engineers, ensuring smooth project execution and effective communication to meet company and customer expectations. Purpose of the Role: To develop Electronics hardware for instrumentation products used in the process...

Designation :- Member Technical Staff No.of positions : 1 Experience : 5 to 10 Years Education : MTech / BE / BTech / ECE/EEE Industry Type : Education / E-Learning / Semiconductor Filter: Full- time- Work from OfficeNotice Period: Immediate to 30 days Role Overview We are seeking an experienced Analog Design Trainer to deliver high-quality training programs in analog and mixed-signal circuit design . The trainer will be responsible for designing training modules, conducting workshops, mentoring engineers, and equipping participants with the technical and practical skills required in the semiconductor/VLSI industry Key Responsibilities: Develop and deliver training content, labs, and worksho...

Job Description for Memory Layout Location: Bangalore Experience 3yrs-10 Yrs - Memory leaf cell layout development - Migration of layout from one tech node to another - Block and top level integration - Quality and timely delivery - EM-IR, area intensive layouts, Quality checks (QC) - Understanding of design rules for 90nm and below - Understanding of design rules for 14ff and 16ff is a plus. - Drive multiple projects and provide necessary technical guidance to the engineers - Understanding of DFM and DFY - Understanding of memory compiler architectures - Good debugging skills - Knowledge of scripting in PERL/Shell/TCL scripting etc - Proficient with tools like Cadence Virtuoso, Calibre LVS ...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Analog Layout Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will engage in a dynamic work environment where you will analyze, design, code, and test various components of application code across multiple clients. Your typical day will involve collaborating with team members to perform maintenance and enhanc...

About The Role Project Role : Software Development Lead Project Role Description : Develop and configure software systems either end-to-end or for a specific stage of product lifecycle. Apply knowledge of technologies, applications, methodologies, processes and tools to support a client, project or entity. Must have skills : Analog Layout Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Lead, you will be responsible for developing and configuring software systems, either end-to-end or for specific stages of the product lifecycle. Your typical day will involve collaborating with vari...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Design Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, your typical day involves analyzing, designing, coding, and testing various components of application code across multiple clients. You will engage in maintenance and enhancement tasks, ensuring that the software remains efficient and effective. Coll...

Hands-on technical, finfet expertise (nodes 12nm or below) and manage a team of 5+ members. Proven track record of managing a team of >5 members. Experience within the service industry. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective...

JD: Analog Layout, TSMC, Intel, Samsung Foundries Nodes - Finfet like 2nm, 3nm, 5nm, 7 nm Location - HYD interested candidate, Kindly share with me your updated profile to anand.arumugam@modernchipsolutions.com Or call me 9900927620 for Discussion

Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in Analog Layout design Expertise in planar technology node / higher node (180nm - 28nm) is mandatory Expertise in EMIR analysis, ESD, antenna and related layout solutions Knowledge of advanced technology nodes (7nm & below) Good understanding of advanced semiconductor technology process and device physics Full-custom circuit layout/verification and RC extraction experience Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are...

Physical Deisgn Lead Location: Bangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology no...

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualificatio...

About The Role : To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimizat...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer ...