236 Cadence Virtuoso Jobs - Page 7

Analog Layout Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech ESSENTIAL DUTIES AND RESPONSIBILITIES: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon e...

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred...

As an Analog Layout Engineer at ARF Design Pvt Ltd, you will be responsible for designing and developing analog layout IP blocks and full-chip integration. Your role will involve performing and resolving LVS/DRC violations independently, collaborating with circuit design teams to optimize layout quality and performance, and ensuring layouts meet design matching and parasitic constraints. You will have the opportunity to work with advanced nodes like 7nm, 16nm, and 28nm, leveraging your 3+ years of relevant Analog Layout experience. Key Responsibilities: - Design and develop analog layout IP blocks and full-chip integration - Perform and resolve LVS/DRC violations independently - Collaborate ...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from de...

: 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shi...

Senior Engineer - Standard Cell Layout Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12161 Remote Eligible No Date Posted ...

As a Layout Design Engineer at Micron Technology, you will play a crucial role in developing critical analog, mixed-signal, and custom digital blocks. Your responsibilities will include designing and developing layout designs, performing layout verification such as LVS/DRC/Antenna, conducting quality checks, and providing support documentation. It will be your responsibility to ensure timely delivery of block-level layouts with acceptable quality while taking ownership of area estimation, scheduling, and execution to meet project deadlines. Collaboration with team members and being a supportive team player are essential aspects of this role. To be successful in this position, you should have...

As a Layout Design Engineer at Micron Technology, you will be responsible for the design and development of critical analog, mixed-signal, and custom digital blocks. Your role will involve performing layout verification tasks such as LVS/DRC/Antenna checks, ensuring quality, and supporting documentation. It will be crucial for you to deliver block-level layouts on time with acceptable quality, taking ownership of area estimation, scheduling, and execution to meet project deadlines. Collaboration with team members and being a strong team player are essential aspects of this role. To qualify for this position, you should have 2 to 5 years of experience in analog/custom layout design in advance...

Job Requirements Bachelor or master Degree with 3-10 years of Analog Layout experience. Good understanding of advanced semiconductor technology process and device physics. Full-custom circuit layout/verification and RC extraction experience. Experience in one or more of the following areas is preferable: Mixed signal/analog/high speed layout, e. g. PLL, IO, RF, PMIC, OSC, DC-DC convertor, Temperature sensor, SRAM, TCAM, ROM, MRAM, ESD Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC, LVS, DFM, etc). Experiences in advanced technology node under 16nm/14nm/7nm. 5nm/3nm will be an added advantage. Must have expertise on Totem EMIR & Self-heating e...

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Job Overview: As an Analog Mixed-Signal IC Layo...

Education Graduation in Pharmacy Long Description The person should have knowledge in Manufacturing equipments. He should have exposure in equipment’s such as FBE,Fette/KORSCH M/C & auto coater M/C He should be able to handle equipment trouble shoot in Manufacturing department. He should have exposure in regulatory organization . He must have faced the USFDA ,MHRA & other regulatory audits. He should have the exposure in Caliber QAMS, elog, track wise ,SAP ,WIND ,CDAS & other software. He should have the exposure in process simplification/optimization ,SABA ,elog & SCADA. Competencies Work Experience 3-6 years work experience in Fette compression machine

We are hiring an experienced Analog Layout Engineer to join a high-performance team working on advanced node technologies. This is a great opportunity to work with a global leader in semiconductor technology. Location: Bangalore Experience: 8 10 Years Employment Type: [Contract] Key Responsibilities: Handle block-level and top-level analog layout. Work on matching techniques, layout parasitics, and advanced layout methodologies. Work independently and collaboratively in a cross-functional team. Ensure quality layout delivery meeting DRC, LVS, and reliability checks. Required Skills: Solid understanding of analog layout fundamentals and design methodologies. Proficiency in 28nm, 22nm, and 16f...

Position: EDA Analog Design/Technology Porting EngineerLocation: Noida, IndiaExperience: 5+ yearsTarget Domain: Analog Design FlowClient: [Confidential / NXP] Key Skills: Virtuoso, Analog Design, Technology Porting, Linux, EDA, IC Design Job Description: As part of the Design Enablement – Analog team, the candidate will contribute to developing and supporting custom EDA design flows. The primary focus is on enabling migration of analog, mixed-signal, and RF designs across technologies/foundries. Key Responsibilities: Setup and execute design/technology porting flows using EDA tools Define migration plans with Business Line teams Work with PDK and Device teams for technology mapping Enable sc...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in additi...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

About Tessolve: Tessolve offers a unique combination of design, test, and product engineering services, enabling our customers to bring products from concept to high-volume production. With a strong presence in semiconductor engineering, we provide a robust environment for growth, learning, and career development. Job Description: We are looking for a skilled and motivated Analog Layout Engineer with 1 3 years of experience in deep sub-micron analog/mixed-signal layout design. The ideal candidate will be responsible for implementing transistor-level layout of analog and mixed-signal blocks while ensuring best practices in layout techniques for matching, parasitic reduction, and reliability. ...

Hands on experience in Circuit Design implementation of IPs including LDOs, Band Gap reference, Good working knowledgein Current Generators, POR, ADC/DACs, PLLs, Oscillators, Good working knowledge in General Purpose IOs, Temperature sensor, SERDES, PHYs, Good in Die to Die interconnect, High-speed IOs,

90/130/150nm and higher node with PMIC layout experience. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective actions if needed until result is successful Performs layout in such a way that final result meets the foundry layout rules. Pr...

Design and develop RF and analog circuits such as LNAs, mixers, power amplifiers, VCOs, PLLs, and ADC/DACs. Perform system-level analysis to optimize RF performance parameters like gain, noise figure, linearity, and phase noise. Conduct circuit simulations using tools like Cadence Spectre, ADS, HFSS, Momentum, and EMX. Collaborate with layout engineers to ensure optimal floorplanning, parasitic extraction, and RF routing. Conduct post-layout verification and EM simulations for high-frequency designs. Participate in lab validation and characterization of fabricated ICs, debugging issues, and improving performance. Work closely with system architects and digital design teams for mixed-signal i...

Lead the design, development, and verification of RF and analog IC blocks, including LNAs, mixers, power amplifiers, PLLs, VCOs, and ADC/DACs. Drive system architecture decisions for RF front-end and transceiver designs. Guide and mentor junior engineers, ensuring high-quality design practices. Perform top-level integration, ensuring seamless connectivity and performance of RF, analog, and mixed-signal circuits. Oversee simulation, layout reviews, and post-layout verification, optimizing for performance and manufacturability. Collaborate with layout, test, and product engineering teams for silicon validation and characterization. Define and execute design methodologies for efficiency, robust...

Lead and manage the analog and RF layout team for high-performance semiconductor products Oversee layout planning, floorplanning, and routing for RF, analog, and mixed-signal IC designs. Work closely with circuit design teams to optimize layouts for performance, area, and manufacturability. Ensure DFM (Design for Manufacturability), DRC (Design Rule Check), LVS (Layout vs. Schematic), and EM (Electromigration) compliance. Drive automation and layout methodologies to improve efficiency and quality. Collaborate with foundry partners for process design kits (PDKs), layout guidelines, and tape-out requirements. Provide technical mentorship to layout engineers and review critical blocks. Own full...

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualificatio...

Responsible for Memory Compiler layout development and verification. Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work. Contribute to effective project-management. Effec...