148 Cadence Virtuoso Jobs - Page 2

As an Analog Mixed-Signal IC Layout Lead Engineer, you will play a critical role in designing advanced node Bi-CMOS / CMOS products You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout You will work to build state-of-the art high speed circuits minimizing layout parasitics, while applying techniques to reduce skew and crosstalk Meeting EM/IR compliance requirements is essential You will ensure strict adherence to DRC, LVS, ANT, and density rules Additionally, awareness of ESD and latch-up design practices is expected to ensure robust and reliable layout implementations You will apply a solid foundation...

The Allegro team is united by a clear purpose advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business from breakthrough product development and customer success to how we show up for each other and the communities we serve. The Opportunity As a Senior Layout Engineer at Allegro MicroSystems, you will be a key contributor to our integrated circuit development team, responsible for the physical implementation of complex analog and mixed-signal designs. You will work closely with design engineers to translate schematics into high-quality, ...

You are an AMS Verification engineer with a B.Tech/M.Tech degree and 5-11 years of industry experience in analog/mixed signal behavioral modeling. Your responsibilities include full chip verification at various levels using SV RNM or Custom UDNs. You should have a good understanding of analog design concepts and mixed signal design architectures, working with products integrating various Analog/Mixed-Signal building blocks. Your experience should cover verification plan development, UVM verification environment development/debug, and verification of complex mixed signal products at different levels. Familiarity with Analog/Mixed-Signal/RF design architectures, debug experience with schematic...

Key Responsibilities: Min 4 Years of overall experience in ASIC Verification Should have worked on AMS Verification for minimum of 2 years Develop and execute verification plans for AMS designs. Create testbenches and run simulations using tools like Cadence Virtuoso, Spectre, or AMS Designer. Verify mixed-signal blocks (e.g., ADCs, DACs, PLLs) and ensure proper analog-digital interaction. Debug and resolve design issues in collaboration with design teams. Document verification results and ensure compliance with design specifications.

You will be responsible for developing block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Your role will involve applying an understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. You will conduct analyses, tests, and verify designs using different tools and techniques to identify and troubleshoot issues. It is essential to stay abreast of new verification methods and work collaboratively with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. To qualify for this posi...

Job Description: Role and Responsibilities: Develops and prepares stdcells layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. Checks dimensions, writes specifications, and verifies completed drawings, artwork or digitized plots. Check design layouts and detailed drawings. 3-5 years of experience. Qualification/Requirements: Must have 3-5 of experience in standard cell layout, analog, mixed-signal and custom digital block designs in advanced CMOS process. Should have expertise in multiple standard cell layout library developments. Should be abl...

We are looking for a highly skilled and experienced Lead Engineer to join our team and contribute to the verification of mixes Signal. The ideal candidate should have a deep understanding of the Cadence, AMS along with expertise in system-level development and debugging What You Will Do Proficient in Verilog-AMS, System Verilog, and UVM methodologies Experience with Cadence Spectre or similar AMS simulation tools Strong understanding of analog circuit design principles (op-amps, transistors, etc.) What You Need to Be Successful Proficient in Verilog-AMS, System Verilog, and UVM methodologies Bonus Points if You Have Experience with Cadence Spectre or similar AMS simulation tools Strong under...

Cadence is looking for Principal Design Engineer to join our dynamic team and embark on a rewarding career journey Health and Safety Compliance: Ensure that construction projects comply with health and safety regulations, guidelines, and industry standards Risk Assessment: Identify and assess potential health and safety risks associated with the project's design, construction methods, and materials Design Coordination: Collaborate with architects, engineers, project managers, and other stakeholders to integrate health and safety principles into the project's design and planning Hazard Identification: Identify and document potential hazards related to the project, including those arising from...

Collaborate withcross-functional teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits. * Create and optimize layout designs usingindustry-standard EDA tools. * Perform physical verification and design rule checks to ensure design integrity andmanufacturability. * Participate in design reviews and provide feedback to improve design quality. * Work closely with circuit designers to understand design specifications and constraints. * Contribute to the development and enhancement of layout design methodologies and best practices. * Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: * Ensur...

General Summary Qualcomm is a company of inventors revolutionizing the CPU market in an age of innovation. As an SRAM Mask Layout Designer , you will be part of a high-performance CPU team, collaborating with top engineering talent to deliver designs that push the limits of performance, energy efficiency, and scalability. This role offers a dynamic and creative environment, with opportunities to impact next-generation products used around the world. In this role, you will develop block or macro-level layouts and floorplans for high-performance custom memories, ensuring alignment with design schematics and project requirements. You will apply industry best practices, work with cutting-edge te...

Circuit design and verification of the CMOS I2C IO and GPIO libraries. Develop I2C IO and GPIO (operation up to 200MHz) architecture to meet the specifications. Develop 3.3V architecture using 1.8V MOS to meet the design & reliability specifications. Optimisation of the design, verification of the functionality, performance, power using Cadence Virtuoso circuit design suite (ADE-XL) Working knowledge of the layout to guide the layout engineers on the implementation of the critical structures for matching, shielding and routing requirements. Strong problem-solving skills, results orientation, attention to detail, and effective communication skills are the key for this position. Experience: 5 ...

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: Are you an Analog Design Engineer with hands-on experience designing components like Bandgap references, High-Speed IO circuits, Low Dropout Regulators (LDOs), and Phase-Locked Loops (PLLs)? If you have a minimum of 2 years in the semiconductor industry, this role offers exciting challenges and opportunities to contribute to groundbreaking projects. Responsibilities: 1. Collaborat...

Skills/Experience: Hands on debugging skills in different physical verification checks like LVS, DRC, ERC, PERC, Antenna, ESD and DFM using Calibre, ICV and Pegasus PV tools Knowledge of basic device physics and PV fixing using various PnR tools like Innovus/ICC2 is required. Working experience in cutting edge technologies such as 3/4/5nm and 7nm process nodes is desired Experience (years) : 4+ Year Education Qualification: B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

About The Role About The Role : 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Ma...

Skills/Experience: Experience with high speed circuits like serializer, deserializer, Rx, Tx,PLL, ADC etc Strong VLSI Fundamentals, Circuits design & Digital Systems deep submicron CMOS design based on FinFETs technology. Solid fundamentals in circuit analysis and Clock/Memory Circuit design. Experience (years) : 2+ Year Education Qualification: BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

About the Role : We are seeking a talented Implementation Engineer to join our dynamic team. The successful candidate will be responsible for leading and executing Synthesis and STA for complex AI SOC with multi-mode and multi power domain design, ensuring the quality and reliability of our products. This is what you are responsible for : - Synthesis and STA (static timing analysis). - Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL. - Professional experience with ECO implementation, both functional and timing closure. - Experience with multi-clock, multi-power domain designs and multi-mode timing constraints. - Familiarity with D...

Perform full-custom analog layout design for blocks such as PLLs, ADCs, DACs, SerDes, High-Speed IOs, Power Management Circuits, and Standard Cells. Work on deep sub-micron process nodes (TSMC 3nm to 16nm) ensuring compliance with foundry rules. Execute layout of matched devices, current mirrors, differential pairs, and high-precision analog/mixed-signal circuits. Perform floorplanning, placement, routing, parasitic extraction, and LVS/DRC verification . Collaborate with circuit designers to ensure performance, reliability, and yield requirements are met. Work on layout optimization for area, performance, and manufacturability (DFM) . Support design reviews and contribute to timely tape-outs...

Skills/Experience: Independent layout development of High Speed blocks like SerDes, Rx, Tx, , PLL, ADC, LDO, Bandgap etc Strong debug skills and good communication Education Qualification: BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

We are looking for a highly skilled EDA Engineer with expertise in Cadence Virtuoso environments and a profound knowledge of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and automation of schematic/layout tools. In this role, you will collaborate closely with AI/EDA development teams to establish seamless design flows and robust automation for our AI-powered analog design platform. Your responsibilities will include developing, maintaining, and optimizing analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. You will also be tasked with creating, modifying, and optimizing SKILL scripts for automating layout, schematic, verification, and design ...

We are looking for a highly skilled EDA Engineer with expertise in Cadence Virtuoso environments and a strong understanding of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and schematic/layout tool automation. In this role, you will collaborate closely with AI/EDA development teams to establish seamless design flows and efficient automation for our AI-powered analog design platform. Your responsibilities will include developing, maintaining, and optimizing analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. You will be tasked with creating, modifying, and optimizing SKILL scripts for automating layout, schematic, verification, and design envi...

As an Analog Layout Engineer with 3-5 years of experience in advanced semiconductor technologies (5nm and below), you will be responsible for executing full custom layout designs for high-speed analog and mixed-signal blocks. Your expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre will be crucial in collaborating closely with circuit design teams to interpret and implement layout specifications. Your key responsibilities will include performing layout verification, ensuring compliance with foundry design rules and layout best practices, addressing issues related to electromigration, IR drop (EMIR), and layout-dependent effects, as well...

You are a Senior Manager responsible for leading the Reference Design team for GlobalFoundries" Fotonix platform, a cutting-edge Silicon Photonics technology. Your role involves driving innovation, creating high-quality reference designs, and ensuring the success and growth of the platform. You will collaborate with stakeholders, manage project timelines, and provide technical leadership to the team. Key Responsibilities - Lead and manage a team of designers in developing Silicon Photonics Reference Designs. - Collaborate with cross-functional teams to define project requirements, timelines, and deliverables. - Drive innovation and development of new silicon photonics technologies and soluti...

Qualcomm India Private Limited is seeking a Layout Engineer to develop block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. In this role, you will utilize your understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. You will conduct analyses, tests, and verify designs using various tools and techniques to identify and troubleshoot issues, while staying updated on new verification methods. Collaborating with multiple internal and external stakeholders, you will align on projects, provide updates, and resolve issues. The id...

As an EDA Engineer, you will be responsible for developing, maintaining, and optimizing analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. Your role will involve creating, modifying, and optimizing SKILL scripts for automation of layout, schematic, verification, and design environment tasks. You will manage Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries. Working extensively with the OpenAccess (OA) database API, using C++, Python, and Tcl, will be a key aspect of your responsibilities. You will be involved in reading, writing, and manipulating design data, including schematic, layout, connectivity, and...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and meticulous engineer with a deep commitment to excellence in analog and high-speed mixed signal layout design. With a minimum of 2 years of hands-on experience in advanced technology nodes (5nm and below), you thrive in dynamic, collaborative environments w...