Role & responsibilities Experience in C++ programming Experience in Software Development Good hands-on in data structures, STL, Algorithms Experience with Linux operating systems Experience with TCP/IP, Socket Programming Experience with application development on Linux platform Good problem solving skills

Responsible for Memory Compiler layout development and verification. Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work. Contribute to effective project-management. Effectively communicate with engineering teams in the India & Korea teams to assure the success of the layout project.

Experienced in rtl design using verilog / system Verilog Asic designers with experiences in all aspects of rtl design flow from specification/microarchitecture definition to design and verification, timing analysis, dft and implementation Integration, rtl signoff tools, upf/low power signoff and cdc/rdc, lint Strong domain knowledge of clocking, system modes. Power management, debug, interconnect, safety, security and other architectures

Physical Design Engineer Lead - InSemi Tech Physical Design Engineer Lead Bangalore | 8 Years Key Responsibilities Technologies Below 14nm 10nm,7nm,latest one ..3nm Block level floor planning and IR drop analysis Block level timing closure with sign off STA Proficient in physical Design methodology which include logic synthesis, placement ,clock tree synthesis, routing

Experience in Static Timing Analysis (STA) for ASIC designs Experience in developing timing constraints Experience in timing closure and optimization Proficiency in using scripting languages such as Perl and TCL Familiarity with EDA tools such as PrimeTime and Design Compiler Experience in Physical Design and/or DFT is a plus Bachelor s or Master s degree in Electrical/Electronics/Computer Science Engineering or related field

Senior Design Verification Engineer - InSemi Tech Senior Design Verification Engineer Bangalore & Hyderabad | 5+ Years Key Responsibilities: Expertise in SOC/IP verification Expertise in System Verilog Coding Experience in OVM/UVM/methodology Working environment in APB/AHB/AXI/PCIe/DDR protocol Experience in Test Bench Development Understanding in Gate Level simulation/debug

Experience in dft scan insertion, atpg at ip and soc level Hands on experience in atpg timing and no-timing simulations Proficient in doing basic unit-level verification using simulations. Scan/atpg patterns & test flows development, debug, test and characterization

Role & responsibilities DriverKit System Extensions creation, entitlement mgmt, lifecycle (activate, deactivate, upgrade) Endpoint Security (ES) framework proc/file I/O, exec, mmap, socket events & high-throughput filtering Installer & On-boarding UI (SwiftUI/AppKit) wizard for System-Extension approval, FDA/Screen-Recording, menu-bar item Interactive Notifications (User Notifications) UNUserNotificationCenter, custom actions, APNs tokens, category/action callbacks Privileged helper & update flow SMAppService / SMJobBless, authorization services, delta updates, rollback XNU & user-land internals AMFI/SIP, sandbox profiles, TCC/privacy DBs Language expertise C/C++17+, Objective-C, Swift interop, dispatch/blocks Memory & concurrency ARC vs manual, GCD, pthreads, atomics/locks Mach & XPC IPC design secure messaging between agent, helper, and system-extension File-system monitoring – FSEvents, APFS snapshots/clones, extended attributes for tagging Code signing / notarization – Developer ID certs, hardened runtime, entitlements, secure-boot chain Packaging & deployment – notarized PKG, system-extension activation via MDM, PPPC/TCC profiles Debugging & telemetry – lldb, Instruments, dtrace, sysdiagnose triage Interested Candidate can share their resumes to swagatika.nayak@insemitech.com